JP2644515B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, in particular, a power MOSFET (metal MOSFET).
Oxide semiconductor field effect transistor)
The present invention relates to a semiconductor device such as a MOSIC incorporating a single unit or a power MOSFET.

[Conventional technology]

Power MOSFETs have been used in many industrial fields in recent years because they have many features such as excellent frequency characteristics, high switching speed, and low power consumption. For example, in the May 19, 1986 issue of Nikkei McGraw-Hill, Nikkei Electronics, p.
It is stated that the focus of MOSFET development is shifting to low voltage products and high voltage products. This document also states that
It is stated that the on-resistance of power MOSFET chips of 100 V or less has been reduced to the level of 10 mΩ.This is because the use of LSI microfabrication in the manufacture of power MOSFETs or the modification of the cell shape has been described. It has been described that the channel width per area can be increased.

Also, this document states that the on-resistance of a low-breakdown-voltage MOSFET is substantially determined by the resistance of the channel. The resistance of the channel can be reduced by increasing the number of cells connected in parallel.
Fine processing survives. Is also described.

Further, a method for increasing the cell density is described as follows. That is, "an effective method for increasing the cell density is a trench MOSFET. A V-groove has been used for a long time. The trench side surface becomes a channel, and a current flows in the vertical direction.
Further, a U-shaped groove having a rounded V-shaped tip is employed to reduce the electric field at the tip of the groove. This is to increase the cell density and reduce the on-resistance.

To further increase the cell density, a groove may be dug perpendicular to the Si substrate. The U-groove was not vertical. Thus, a MOSFET in which the pitch between adjacent vertical grooves was 17 μm was developed. The on-resistance of the 50-V MOSFET was 13 mΩ, and the product of the on-resistance and the area was 187 mΩ · mm ² . If the pitch of the groove is set to 10 μm or less or the groove is deepened, the on-resistance is further reduced. It is described.

On the other hand, in a MOS memory, a trench capacitor in which a capacitor is formed using a deep groove (trench) has been developed as a structure providing higher integration. For example, for trench capacitors, refer to “Monthly Semiconductor World (Se
micon-ductor World), October 1986, September 1986
Published on the 15th, P65-P69. In this document,
The following is described as a problem in the gate oxide film forming technique. In other words, "The technology for forming a gate oxide film in a trench capacitor is summarized as to how to suppress the leak current at the convex or concave corner which always exists. The causes of the increase in the leak current at the corner are roughly classified into two. One is the electric field concentration due to the corner itself, and the other is due to the phenomenon that the oxide film formed at the corner becomes thinner.
This can be dealt with by rounding sharp corners immediately after RIE trench processing. In the rounded corner, the gate oxide film formed there is suppressed from being thinned, and the electric field concentration is also reduced. Is described.

[Problems to be solved by the invention]

In recent years, power MOSFETs have been
The on-resistance has been reduced to the Ω level. This miniaturization technology has been realized by reducing the unit cell size of the MOSFET to about 20 μm. The tendency of low on-resistance (R _ON ) is remarkable for all companies in the low breakdown voltage 60V-100V class. However, due to miniaturization, it is necessary to secure the breakdown voltage characteristics at shallow junctions and to restrict the planar structure (DSA type) photoresist. There is a limit to cell reduction.

FIG. 13 shows a cross-sectional structure of a conventional planar type vertical MOSFET. The cell 1 of the MOSFET is provided with n ⁻ provided on a semiconductor substrate 2 made of silicon (Si) of a first conductivity type, for example, n ⁺ type.
A plurality of low-concentration layers 3 are regularly and vertically formed on the surface of the low-concentration layer 3.

A p-type well region 4 having a substantially rectangular shape is provided in a surface portion of the low concentration layer 3. The plurality of well regions 4 are formed on the main surface of the semiconductor substrate 2 at predetermined intervals (c) vertically and horizontally. Therefore, on the main surface of the semiconductor substrate 2, the low-concentration layer 3 having a width of c and being exposed in a lattice pattern is formed, and the drain surface layer portion 5 is formed.

In the surface region of the well region 4, an n ^{+ -type} source region 6 is provided in a ring shape along the periphery of the well region 4. Further, on the outer peripheral portion of the well region 4, that is, on the lattice portion along the drain surface layer portion 5, the gate oxide film 7, the gate electrode 8 provided on the gate oxide film 7, and the gate electrode 8 and the gate oxide film. 7 is provided. A source electrode 10 is provided on the main surface of the semiconductor substrate 2, and a drain electrode (not shown) is provided on the back surface. The source electrode 10 is configured to be in electrical contact with the source region 6 and the drain surface layer 5.

In such a MOSFET cell, portions that restrict the cell size are roughly classified into a to d. a is the insulation distance between the gate and the source, b is the channel length, c is the length of the drain region between the base junctions, and d is the source contact length. Of these, a and d are in the direction of shortening with miniaturization, while b and c have optimum lengths due to element characteristics (breakdown voltage, on-resistance, etc.) and are restricted.

Therefore, the present inventor has noticed that the cell size can be further reduced by forming a power MOSFET cell using a trench having the narrowest groove width.

However, when the power MOSFET cell is formed as it is using the trench according to the related art, the following problem occurs.

That is, as shown in FIG. 14, a gate oxide film (insulating film) 7 is provided on the inner wall of the trench 11 provided in the semiconductor substrate 2, and then the gate oxide film 7 is overlapped with the gate oxide film 7 and filled in the trench 11. When the electrode 8 is provided, as described above, in the trench 11 according to the conventional technique, the growth state of the film at the time of forming the insulating film is poor at the bottom corner (corner E ₁ ) of the trench 11, and the portion of E ₁ However, there is a problem that the quality of the film provided is low and the film thickness becomes thin. As a result, the breakdown voltage of the insulating film is reduced, and a breakdown occurs between the gate electrode 8 and the drain formed by the semiconductor substrate 2.

The drain - When a voltage is applied between the gate, decrease in breakdown voltage characteristic is generated in the substrate portion E ₂ of the trench Sokosumi unit electric field is concentrated, conventional such decrease in breakdown strength as a whole occurs VMOS structure identical to the Problems arise.

An object of the present invention is to provide a power MOSFET having a high breakdown strength.

Another object of the present invention is to provide a semiconductor device having a structure capable of miniaturizing the cell size of a MOSFET.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The following is a brief description of an outline of typical inventions disclosed in the present application.

That is, the trench-type vertical power MOSFET of the present invention,
A channel forming layer for forming a channel is provided on an upper surface of a semiconductor substrate having a low concentration layer on a main surface, and a source region is provided on a surface portion of the channel forming layer. A trench reaching the drain region is provided at the center of the source region, and a gate oxide film is provided on an inner wall of the trench. In addition, a high-concentration reach-through layer that is close to the impurity concentration of the semiconductor substrate is provided at an interface between the trench and the semiconductor substrate and the low-concentration layer. The impurity concentration and thickness of the low-concentration layer are appropriately selected such that breakdown occurs in the reach-through layer portion at a voltage lower than that at the bottom corner of the trench. In the gate oxide film, the thickness of the bottom of the trench is thicker than other portions such as the side wall of the trench. A gate electrode is provided on the gate oxide film so as to fill the trench. Further, the gate electrode surface is covered with an insulating film,
A source electrode in contact with the source region and the channel formation layer is provided on the insulating film.

[Action]

According to the above means, the trench type vertical power MOSFET of the present invention is provided with a trench reaching the drain at the center of a source region provided on a partial surface of a channel forming layer, and the trench has a gate oxide. Since the structure is such that the gate electrode is provided with the film interposed, the cell density can be increased, the on-resistance can be reduced, and the chip size can be reduced or the degree of integration can be increased. Further, the trench type vertical power MOSF of the present invention
In the case of ET, since the reach-through layer is provided, the breakdown is performed by this reach-through layer, so that the breakdown voltage is stable compared to the breakdown occurring at the bottom corner of the trench. Can be guaranteed. Further, the trench type vertical power MO of the present invention
In the SFET, since the thickness of the gate oxide film provided on the inner wall of the trench is 4 to 6 times or more the thickness of the side wall of the trench, even if the film quality of the gate oxide film is not necessarily good, The dielectric strength is improved. In addition, the partial thickening of the gate oxide film alleviates the electric field concentration at the corner of the bottom of the trench and improves the withstand voltage.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view showing a part of a vertical power MOSFET according to one embodiment of the present invention, FIG. 2 is a flowchart showing a manufacturing process of the vertical power MOSFET, and FIGS. FIGS. 3A and 3B are views showing respective stages of manufacturing a power MOSFET, FIG. 3 is a sectional view of a wafer in which a source region is formed, FIG. 4 is a sectional view of a wafer in which a trench is provided, and FIG. FIG. 6 is a cross-sectional view of a wafer provided with a film, FIG. 6 is a cross-sectional view of a wafer showing a state in which an upper insulating film is etched in a different direction, and FIG. FIG. 8 is a sectional view of the wafer showing a state where an insulating film on the side wall of the trench is removed, FIG. 9 is a sectional view of the wafer showing a state where a gate oxide film is formed, FIG. FIG. 11 is a cross-sectional view of a wafer showing a state where a polysilicon film is formed, and FIG. Sectional view of a wafer in a state of forming the over gate electrode, FIG. 12 is a sectional view of a wafer in a state of forming the source electrode.

The main part of the trench type vertical power MOSFET of this embodiment, that is, the cell part has a structure as shown in FIG. In the drawing, a portion between the dashed lines W is a single cell 1 portion (cell length) in cross section, and a region surrounded by a dashed line frame is a single cell 1 portion viewed in plan. Such cells 1 are provided in a single vertical power MOSFET, and are arranged regularly in a large number of rows and columns.

The cell 1 has a main surface (upper surface) of a semiconductor substrate 2 of the first conductivity type.
Is provided. A first conductivity type low concentration layer 3 is provided on a main surface of the semiconductor substrate 2. The semiconductor substrate 2
Of thickness about 100μm impurity concentration is about 10 ²¹ cm ^-3 n ⁺
The first conductive type is formed of silicon.
Further, the low concentration layer 3 is n thick 5μm~10μm the impurity concentration is about 10 ¹⁵ cm ^{-3 -} is formed by the shape of the epitaxial layer. Further, a p-type channel forming layer 20 having a thickness of 3 μm having an impurity concentration of about 10 ¹⁷ cm ⁻³ is provided on the semiconductor substrate 2. An n ^{+ -type} source region 6 having an impurity concentration of about 10 ²⁰ cm ⁻³ is provided on the main surface of the semiconductor substrate 2, that is, on the surface layer of the channel forming layer 20. The source region 6 is provided on the main surface of the semiconductor substrate 2 in a lattice shape. The width of the source region 6 is about 7 μm, and the pitch of the source region is
It is about 10 μm. Further, the source region 6 has a capacity of 0.
The depth is 5 μm.

4. Trench (deep groove) along the center of the source region 6
11 are provided. This trench 11 has a width of 1 μm.
m, and the depth is, for example, 5 μm so as to reach the low concentration layer 3 on the surface of the semiconductor substrate 2 through the channel forming layer 20. The trench 11 is provided with a gate oxide film 7 so as to cover the inner wall of the trench 11. The gate oxide film 7 has a thickness of 500 ° at the side wall of the trench 11 and has a thickness of 22 at the bottom of the trench 11.
It is between 000Å and 3000Å. A gate electrode 8 made of polysilicon is provided in the trench 11 so as to overlap the gate oxide film 7 and fill the trench 11.

On the other hand, between the semiconductor substrate 2 and the low-concentration layer 3 between adjacent trenches 11, an n ^{+ -type} reach-through layer 18 having an impurity concentration as high as 10 ²⁰ × 10 ²¹ cm ^-3 is provided. I have. The trench 11 is provided with an insulating film 21 having a constant width. This insulating film 21 has a thickness of, for example, 6000 mm.
And covers the gate electrode 8 and slightly overhangs the edge of the trench 11 to cover a part of the source region 6. The insulating film 21 and the source region 6 and the exposed surface of the channel forming layer 20 have a thickness of 3 μm.
A source electrode 10 made of aluminum (Al) having a thickness of about m to 3.5 μm is provided. Further, on the back surface (lower surface) of the semiconductor substrate 2, a drain electrode 22 having a thickness of several μm is provided.

In such a trench type vertical power MOSFET,
Since the gate oxide film 7 is provided on the side wall of the trench 11 and the gate electrode 8 is buried in the trench 11, the cell size (W) can be reduced to 10 μm.
As a result, the on-resistance of the low breakdown voltage power MOSFET can be reduced to 2-3 mΩ. In addition, by reducing the cell size, the power MOSFET chip can be downsized or highly integrated (the number of cells can be increased).

In this trench type vertical power MOSFET, the gate electrode 8 is provided in a narrow and deep trench 11;
The gate oxide film 7 provided on the inner wall surface of the trench 11 is a bottom portion of the trench 11 other than the gate oxide film directly involved in the FET operation (for convenience of description, this portion is also referred to as a thick insulating film 19 hereinafter). Is the gate oxide film 7 directly involved in the FET operation.
Since the thickness is 2000 to 3000 degrees, which is 4 to 6 times that of 00 degrees, the withstand voltage of the gate oxide film is improved.
Generally, the intrinsic oxide withstand voltage is 8 MV / cm to 10 MV / cm,
At the bottom of the trench, the breakdown voltage is expected to be reduced to half or less due to the deterioration of the film quality. Therefore, simply doubling the film thickness can approach the intrinsic oxide film breakdown voltage. In this example, the thickness of the gate oxide film 7 at the bottom of the trench 11 is 4 to 6 times the thickness of the side wall of the trench 11, so that the intrinsic oxide film withstand voltage is sufficient.

Further, according to this structure, the electric field between the gate and the drain is reduced by increasing the thickness of the gate oxide film at the bottom of the trench, so that the drain withstand voltage is improved. Further, in this example, the breakdown voltage is improved by increasing the gate breakdown voltage and the drain breakdown voltage.

On the other hand, in this trench type vertical power MOSFET,
A reach through layer 18 is provided between the semiconductor substrate 2 and the low concentration layer 2b. The reach-through layer 18 has an impurity concentration
10 ²⁰ × 10 ²¹ cm ^-3 , which is close to that of the semiconductor substrate 2. For this reason, the thickness of the n ⁻ -type low-concentration layer 3 below the pn junction 17 is reduced.
Therefore, before a high electric field acts on the bottom corner of the trench 11 to cause a breakdown, the depletion layer in the low concentration layer 3 of the semiconductor substrate 2 reaches the reach-through layer 18 and breaks at the reach-through layer 18. Down happens. In this reach-through, since the concentration and thickness of the low-concentration layer 3 are parameters of the withstand voltage characteristic, if the numerical values are appropriately selected, a desired voltage can be obtained before breakdown at the bottom corner of the trench 11. It can be set to break down.

Next, a method for manufacturing such a trench-type vertical power MOSFET will be described.

As shown in the flowchart of FIG. 2, the cell portion of the trench-type vertical power MOSFET is formed by deposition, epitaxial growth, formation of a source region, formation of a trench, formation of a trench bottom insulating film, formation of a gate oxide film, and formation of a gate electrode. And a drain electrode formation process.

In the manufacture of trench type vertical power MOSFET,
As shown in the figure, a semiconductor substrate 2 made of n ⁺ -type silicon is prepared. This semiconductor substrate 2 has a thickness of 400 μm.
And the impurity concentration is 10 ²¹ cm ⁻³ . Thereafter, an impurity is deposited in a region where the reach-through layer 18 is formed. Then, the epitaxial growth process, the impurity concentration of 10 ¹⁵ cm is about ^-3 n ^- the shape of the low concentration layer 3 is provided. This low concentration layer 3 has a thickness of about 5 μm to 10 μm. A channel forming layer 20 having a thickness of 3 μm is provided on the low concentration layer 3 by the epitaxial growth. In addition, during the epitaxial growth, the deposited impurities diffuse, and n ⁺
A shaped buried layer, ie, a reach-through layer 18, is formed. The reach-through layer 18 has an impurity concentration of 10 ²⁰ to 10 ²¹ cm.
^−3, which is similar to the semiconductor substrate 2. The low-concentration layer 3 on the reach-through layer 18 has a thickness of several μm, and breaks down at the reach-through layer 18 before breaking down at the bottom corner of the trench 11 described later. I have.

On the other hand, n ⁺
A shaped source region 6 is provided. This sole area 6
Has a width of 7 μm and a depth of 0.5 μm. The source region 6 has an impurity concentration of
It is 10 ²⁰ cm ^-3 . The pitch (W) of the source regions 6 provided in a lattice is 10 μm. And this pitch W becomes the length of the single cell 1.

Next, as shown in FIG. 4, an insulating film 24 is provided on the main surface of the wafer 23, and a trench (deep groove) 11 is formed along the center of the source region 6 by ordinary photolithography. You. Since the trenches 11 are provided along the center of the source region 6, they are provided on the main surface of the wafer 23 in a lattice pattern. A region surrounded by the trench 11, more precisely, a width region of W extending over the center of the trench 11 becomes a single cell 1. The trench 11 has a groove width of 1 μm and a depth of 5 μm, and penetrates the channel formation layer 20 below the source region 6 to reach the low concentration layer 3. During the formation of the trench 11, etching conditions are selected so that the corner at the bottom of the trench 11 is rounded, and the insulating film formed later is thinned at the corner or the film quality is deteriorated. As much as possible.

Next, the insulating film 24 is removed. Thereafter, as shown in FIG. 5, the main surface of the wafer 23 has a 400 mm thick S
iO ₂ film 25 and 1200 ° Si ₃ superimposed on this SiO ₂ film 25
N ₄ film 26 is provided. After that, by anisotropic etching (plasma etching), the Si ₃ N
_Four film 26 is etched. As a result, as shown in FIG. 6, Si ₃ N ₄ film 26 on the bottom major surface and the trench 11 of the wafer 23 is removed, only the Si ₃ N ₄ on the side wall surface substantially extending perpendicularly of the trench 11 The film 26 remains.

Next, an oxidation treatment (LOCOS method) is performed in this state. That is, as a result of the oxidation treatment of the wafer 23, as shown in FIG. 7, an SiO ₂ film of 2000 to 3000 ° is formed on the main surface of the wafer 23 and the bottom of the trench 11. Due to the LOCOS process, this thick SiO ₂ film portion (thick film insulating film 19) has a bird's beak structure at both ends, that is, a bottom corner portion of the trench 11, and a portion extending from the side surface of the trench 11 to the bottom of the trench 11 is formed. The thickness of the Si ₃ N ₄ film 26 gradually increases.

Note that this structure in which the insulating film gradually becomes thicker from the side surface to the bottom of the trench can be used even when the Si ₃ N ₄ film 26 and the SiO ₂ film 25 on the side surface of the trench 11 are removed and a gate oxide film is formed again. This occurs due to the balance with the remaining thick insulating film 19, which leads to an improvement in the breakdown voltage at the bottom corner of the trench 11.

Next, as shown in FIG. 8, the Si ₃ N ₄ film 26 and the SiO ₂ film 25 on the side surfaces of the trench 11 are removed by etching. The Si ₃ N ₄ film 26 is etched using a hot phosphoric acid etchant, and the thick insulating film 19 is etched using a hydrofluoric acid etchant. Through this series of etching, the thick film insulating film 19 at the bottom of the trench 11 and the SiO ₂ film 25 on the main surface of the wafer 23 remain.

Next, as shown in FIG. 9, an insulating film made of a SiO ₂ film having a thickness of 500 ° is formed again on the entire main surface of the wafer 23. This insulating film is used as a gate oxide film 7 on the side surface of the trench 11. Thick insulating film 19 at the bottom of trench 11
Is 2000 to 3000, which is 4 to 6 times the thickness of the gate oxide film 7 on the side surface of the trench 11. In addition, the gate oxide film 7 at a corner portion from the side surface of the trench 11 to the bottom of the trench 11 has a so-called bird beak structure in which the thickness gradually increases toward the bottom.

Next, as shown in FIG. 10, a polysilicon (Poly Si) film is formed on the entire main surface of the wafer 23 by vapor deposition. At this time, boron (B ⁺ ) is simultaneously doped. As a result,
This polysilicon film 27 has a low electric resistance. The polysilicon film 27 is formed in an amount sufficient to fill the trench 11 having a width of less than 1 μm.

Next, as shown in FIG.
The SiO ₂ film 25 and the polysilicon film 27 existing above the upper surface of the substrate are etched away. As a result, trench 11
The gate electrode 8 is formed by the polysilicon film 27 therein. Thereafter, as shown in FIG. 12, an insulating film 21 made of a PSG (phosphor silicate glass) film having a thickness of 6000 ° is formed on the trench 11 by a CVD technique and ordinary photolithography. The insulating film 21 has both sides projecting beyond the edge of the trench 11 and extending over the edge of the source region 6 on the trench 11 side.

Next, as shown in FIG. 12, the main surface of the wafer 23 is made of aluminum (Al) to a thickness of 3 μm to 3.5 μm.
Is deposited to form a source electrode 10 made of Al. Thereafter, the back surface (lower surface) of the wafer 23 is etched. By this etching, the semiconductor substrate 2 has a thickness of about 100 μm.

Next, on the back surface of the wafer 23, a drain electrode is formed. Thereby, the manufacture of the cell 1 of the trench type vertical power MOSFET is completed.

In such a trench type vertical power MOSFET,
The following effects are obtained.

(1) The trench-type vertical power MOSFET of the present invention has a structure in which a gate oxide film is provided on a side surface of a trench and a gate electrode is provided in the trench, and the side surface of the trench is used as a channel. At the same time, since the reach-through layer is provided between the semiconductor substrate between the trenches and the low concentration layer, before the electric field large enough to cause a breakdown at the bottom corner portion of the trench, the reach-through layer portion is formed. Since the breakdown occurs, the effect that the breakdown voltage can be guaranteed is obtained.

(2) The trench type vertical power MOSFET of the present invention has a structure in which a gate oxide film is provided on a side surface of a trench and a gate electrode is provided in the trench, and the side surface of the trench is used as a channel. In addition, the trench has an extremely narrow width of 1 μm, so that the cell size is 10 μm.
The effect that the size can be reduced to μm is obtained.

(3) According to (2), the trench-type vertical power MOSFET of the present invention has an effect that the cell size can be reduced to 10 μm, and the on-resistance can be reduced to 2 to 3 mΩ.

(4) According to the above (2), the trench-type vertical power MOSFET of the present invention has an effect that the size of the vertical power MOSFET chip can be reduced because the cell size can be reduced.

(5) Due to the above (2), the trench-type vertical power MOSFET of the present invention has an effect that the cell size can be reduced, so that the vertical power MOSFET can be highly integrated.

(6) Although the trench type vertical power MOSFET of the present invention has a structure in which a gate oxide film is provided in a trench, the thickness of the gate oxide film at the bottom of the trench, that is, the thickness of the insulating film is effectively equal to that of the FET. Since the thickness of the gate oxide film to be operated is 4 to 6 times the thickness, even if the quality of the insulating film at the bottom corner of the trench is poor, it can be compensated by the thickness.
An effect that a desired intrinsic oxide film breakdown voltage can be obtained can be obtained.

(7) According to the above (6), in the trench type vertical power MOSFET of the present invention, the thickness of the gate oxide film at the bottom of the trench is as large as several thousand Å, and the edge of the insulating film at the bottom is a bird's beak. Due to the structure, the thickness of the insulating film at the corners is large, and as a result, the effect is obtained that the electric field concentration is eased and the breakdown voltage hardly deteriorates.

(8) According to the above (2) and (7), the trench type vertical power MOSFET of the present invention has the effect of improving the breakdown resistance as a whole by improving the breakdown voltage of the gate oxide film and the breakdown voltage by the electric field concentration. .

(9) According to the above (1) to (8), according to the present invention, a synergistic effect that a small-sized vertical power MOSFET having a high electrostatic breakdown strength and a small on-resistance can be provided is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, as a method of increasing the thickness of the gate oxide film (insulating film) at the bottom of the trench, a method of implanting oxygen directly into the bottom of the trench 11 may be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technology of the trench type vertical power MOSFET which is the application field as the background has been described, but the invention is not limited thereto. The present invention can be applied to the manufacture of a semiconductor device using a simple trench, for example, a trench capacitor.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

The trench type vertical power MOSFET of the present invention is provided with a trench reaching the drain at the center of a source region provided on a partial surface of a channel forming layer, and the trench is provided with a gate electrode with a gate oxide film interposed therebetween. , The size of the cell can be reduced, the on-resistance can be reduced, and the chip size can be reduced or the degree of integration can be increased. Further, in the trench type vertical power MOSFET of the present invention, since the reach-through layer is provided, the breakdown is performed in the reach-through layer. As a result, the breakdown voltage can be ensured. Further, in the trench type vertical power MOSFET of the present invention, the thickness of the gate oxide film provided on the inner wall of the trench is 4 to 6 times or more the thickness of the side wall of the trench. Even if the film quality is not necessarily good, the withstand voltage is improved. In addition, the partial thickening of the gate oxide film alleviates the electric field concentration at the corner of the bottom of the trench and improves the withstand voltage.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a part of a vertical power MOSFET according to an embodiment of the present invention, FIG. 2 is a flowchart showing a manufacturing process of the vertical power MOSFET, and FIG. FIG. 4 is a cross-sectional view of a wafer provided with a trench, FIG. 5 is a cross-sectional view of a wafer also provided with an insulating film in two layers, and FIG. FIG. 7 is a cross-sectional view of a wafer showing a state in which an insulating film is etched in a different direction; FIG. 7 is a cross-sectional view of a wafer showing a state in which the insulating film at the bottom of the trench is similarly thickened by the LOCOS method; FIG. 9 is a cross-sectional view of a wafer showing a state in which a gate oxide film has been formed, and FIG. 10 is a cross-sectional view of a wafer showing a state in which a polysilicon film has also been formed. Fig. 11 FIG. 12 is a cross-sectional view of a wafer in which a gate electrode is formed, FIG. 12 is a cross-sectional view of a wafer in which a source electrode is formed, FIG. 13 is a schematic cross-sectional view showing a main part of a conventional lateral power MOSFET, FIG. 14 shows a trench type vertical power MOSFET tried by the present inventor.
FIG. 4 is a schematic diagram illustrating breakdown at the bottom of the trench. 1 ... cell, 2 ... semiconductor substrate, 3 ... low concentration layer, 4 ...
... well region, 5 ... drain surface layer, 6 ... source region, 7 ... gate oxide film, 8 ... gate electrode, 9 ... insulating film, 10 ... source electrode, 11 ... trench, 17 ... pn junction, 18 ... reach-through layer, 19 ... thick insulating film, 20 ...
Channel forming layer, 21 ... insulating film, 22 ... drain electrode,
23 ... wafer, 24 ... insulating film, 25 ... SiO ₂ film, 26 ... Si
₃ N ₄ film, 27 ...... polysilicon film.

Claims (2)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a low concentration layer of the first conductivity type provided on a main surface of the semiconductor substrate, and a channel of a second conductivity type provided on an upper surface of the low concentration layer. A formation layer, a source region of the first conductivity type provided partially on the surface of the channel formation layer, and a source region of the first conductivity type provided at the center of the source region and penetrating the channel formation layer A semiconductor device having a vertical power MOSFET including a groove reaching a low-concentration layer, a gate oxide film covering an inner wall surface of the groove, and a gate electrode provided on the gate oxide film. A semiconductor device, wherein a reach-through layer of the first conductivity type and having a concentration close to the impurity concentration of the semiconductor substrate is provided between the semiconductor substrate and the low concentration layer between the trenches; . 2. The method according to claim 1, wherein said groove is formed by a trench having a groove width of 1 μm or less.
13. The semiconductor device according to claim 1.