JP2644592B2 - Convergence correction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a convergence correction device for a color television receiver.

FIG. 7 is a block diagram of a conventional example.

In FIG. 7, reference numeral 1 denotes a phase locked loop (hereinafter, referred to as "PLL") circuit. A horizontal blanking signal is input to a terminal a and a vertical blanking signal is input to a terminal b from a deflection system of a display device. The PLL circuit 1 is phase-synchronized with the blanking signal, and outputs a reference clock multiplied by x in the horizontal direction and multiplied by y in the vertical direction (x and y are natural numbers). The reference clock is input to the timing generation circuit 2 and outputs a pattern clock signal to the pattern generation circuit 3 and an address clock signal to the address generation circuit 4. The pattern generating circuit 3 normally has nine cross hatch patterns in the horizontal direction and thirteen in the vertical direction in the screen as shown in FIG. 4, and when the static convergence switch 11 is ON, it is shown in FIG. Such a cross pattern is output to the output terminal h.

When the convergence is coincident, it looks like a white cross pattern as shown in FIG. 5, but when there is a static convergence deviation, the R, G and B colors are x or y as shown in FIG.
Seems shifted in the direction. FIG. 4 shows a cross hatch pattern representing the correction position on the screen. In this case, the convergence adjustment point is the intersection of the cross hatch pattern shown in FIG. That is, the adjustment point is equally divided into x in the horizontal direction and y in the vertical direction.
It is the intersection of equally divided crosshatch patterns. The address generating circuit 4 outputs a synchronous address signal to the terminal c of the address switching circuit 5. The synchronous address signal is PLL
It is synchronized with the horizontal and vertical blanking signals input to the circuit 1. The address switching circuit 5 includes three terminals, terminals d and e, in addition to the terminal c. The switching operation is controlled by an address switching signal output from a control circuit 8.

At present, when the terminals c and e are ON as shown in FIG. 7, the synchronous address signal is guided to the frame memory 6. The digital correction data in the frame memory 6 respectively correspond to correction points which are intersections of the cross hatch patterns shown in FIG. 4, and are read out one after another in synchronization with the raster scan. The read digital correction data is input to a D / A conversion circuit 9, converted into an analog signal, and then smoothed by a low-pass filter (hereinafter, referred to as “LPF”) 10. The convergence correction signal smoothed by the LPF 10 has a DC component obtained by the static convergence adjustment volume 12 and a DC superposition circuit 13.
Are amplified by the driver amplifier 14 and guided to the conversion sense correction coil 15.

The control circuit 8 is a circuit using, for example, a microprocessor or the like, and generates a control address signal for the terminal d of the address switching circuit 5 and the nonvolatile memory 7. At the same time, the frame memory 6 and the nonvolatile memory 7 have a bidirectional data bus. That is, the control circuit 8
When the terminals d and e of the address switching circuit 5 are turned ON by an address switching signal output from the address switching circuit 5 to the address switching circuit 5, the frame memory 6 is addressed by the control address signal. The contents can be changed, and appropriate convergence correction digital data is obtained in the frame memory 6 after trial and error.

If the address switching signal is changed at the timing of, for example, a vertical blanking signal, the synchronous address signal and the control address signal are alternately switched to the frame memory 6, and the digital correction data from the frame memory 6 is synchronized with the synchronous signal cycle. Read without interruption. When a series of operations for the convergence correction is completed, the terminals f and g of the write switch 16 connected to the control circuit 8 are turned on.
When the write switch 16 is turned on, the control circuit 8 outputs an address switching signal so that the terminals d and e of the address switching circuit 5 are turned on only during the vertical blanking period, and the contents of the frame memory 6 are transferred to the bidirectional data bus. To the non-volatile memory 7 and write to the non-volatile memory 7.

If the data capacity of the nonvolatile memory 7 is set to n times the data capacity of the frame memory 6, the nonvolatile memory 7 can be selectively written into n blocks by a memory selection signal from the control circuit 8. Also, turn off the power
Then, when it is turned ON again, the address switching signal turns ON the terminals d and e of the address switching circuit 5, and the control circuit 8 transfers the contents of the nonvolatile memory 7 of the block selected by the memory selection signal to the frame memory through the data bus. 6 and the digital correction data is again read out synchronously.

There are two ways to adjust convergence: fixing green and matching red to green, and matching blue to green. In either case, the series of operations described above for each intersection of the cross hatch pattern Is repeatedly performed.

Problems to be Solved by the Invention In the conventional convergence correction device, even after appropriate correction, the state of the correction circuit changes due to temperature change due to changes in circuit and component characteristics due to aging, etc. There was a drawback that the convergence was not adjusted properly due to drift.

Means for Solving the Problems In order to solve the above-described problems, the present invention focuses on the fact that most of the causes of static drift are due to drift of a DC component, and reduces a DC component of a correction current flowing through a convergence correction coil. A DC level detection circuit for detecting
A feedback loop for automatically changing the digital correction amount of convergence from the change amount of the DC component detected by the DC level detection circuit is formed.

When the DC component of the convergence correction coil drifts due to changes in the characteristics of the circuit components due to aging, etc., the DC component of the convergence correction coil is detected by the DC level detection circuit, and this DC component is stored in advance for proper convergence correction. Compared with the reference level corresponding to the subsequent DC component, the DC component change amount detection means detects the DC component change amount, and changes the value of the frame memory for storing the digital correction amount in the direction in which the change amount decreases. Rewrite and correct for static convergence drift.

Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
Parts corresponding to the conventional example shown in the figure are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 1, reference numeral 17 denotes a DC level detection circuit for detecting the DC voltage level of the convergence correction coil 15;
Is an analog / digital (hereinafter referred to as "A / D") conversion circuit for converting the DC voltage detected by the DC level detection circuit into a digital signal, and 19 is digital DC data output from the A / D conversion circuit 18 Is stored when the static convergence switch 11 changes from ON to OFF, and the signal is transferred to the register X20 in the control circuit 8.
It is.

Note that the A / D conversion circuit 18 may use a simple comparator.

FIG. 2 is a flowchart of an automatic correction operation for automatically correcting the drift of the DC voltage of the convergence correction waveform supplied to the convergence correction coil 15. Hereinafter, the operation of the present invention will be described in detail with reference to the flowchart shown in FIG.

First, the convergence correction is performed by turning on the static convergence adjustment switch 11 to generate a cross pattern for static convergence adjustment from the pattern generating circuit 3 as shown in FIG.
Is adjusted to superimpose the DC component on the DC superimposing circuit 13 so as to eliminate the deviation of the green-red or green-blue cross pattern as shown in FIG. 6, and to perform appropriate static convergence adjustment. When the static convergence adjustment is completed, the static convergence switch 11 is switched from ON to OFF. The control circuit 8 knows that the static convergence adjustment has been completed by switching the static convergence adjustment switch 11 to OFF. This state corresponds to step (i) in the flowchart shown in FIG.

On the other hand, the DC voltage of the convergence correction waveform supplied to the convergence correction coil 15 is detected by the DC level detection circuit 17, and is derived as a DC signal corresponding to the DC voltage. This DC signal is guided to the A / D conversion circuit 18 and the third
As shown in the figure, the data is converted into, for example, 8-bit digital DC data. That is, as shown in FIG.
When the dynamic range of the analog DC signal which is the output signal of 17 is set to + BV to -BV, and the dynamic range of the A / D conversion circuit 18 is set to, for example, 8 bits, the DC signal which is the analog signal becomes 0 to 255 digital DC data. When the analog DC signal L at the end of the static convergence adjustment is set to the reference level, this is associated with the M-bit digital DC data.

Then, the digital DC data M is taken into the register Y19 after the static convergence adjustment is completed.
It is not necessary to carry out the fetch operation to the register Y19 frequently, and it may be performed at a convenient time in the processing program of the microprocessor provided in the control circuit 8.
The data taken into the register Y19 is further transmitted to the control circuit 8
And is set as a reference level in the control circuit 8. This state corresponds to step (ii) in FIG.
Is equivalent to

For some reason such as a temperature change, a drift of static convergence occurs, and the DC signal which is a detection signal of the DC level detection circuit 17 is, for example, L ′ (or L ″) with respect to the reference level L as shown in FIG. If the drift of the DC signal is L '(or L "), the digital DC data written to the register Y19 in step (iii) becomes M' (or M"), and Since the digital DC data previously written in the register X20 in the control circuit 8 in the level setting step (ii) is M, the contents of both registers X and Y are compared in the step (iv), and X-
The condition of Y ≦ 0 is satisfied (or not satisfied)
That is, in the next step (vii) (or steps (v) and (vi)), the digital correction data is
Bits (or + N bits), and M′−M (or M ″)
-M) Form a loop to reduce drift.

In this case, the N bits as a unit for changing the digital correction data may be appropriately determined from the input level and gain of the driver amplifier 14, the DC level detected by the DC level detection circuit 17, and the like.

As described above, when the DC level of the convergence correction coil 15 becomes higher or lower than the reference level, step (iii) → (iv) → (vii) → (iii) or step (i)
A loop of ii) → (iv) → (v) → (vi) → (iii) is formed, and the content of the register Y19 is subtracted or added N bits at a time, and the adjustment is automatically made in the direction to eliminate the drift amount. That is, step (iii) → (iv) → (v) → (iii)
The control circuit 8 controls the frame memory 6 so that
, The DC level drift in the convergence correction coil 15 is corrected.

The basic operation of the convergence correction has been described above.
The same operation may be performed for each of red, green, blue, horizontal and vertical.

Effects of the Invention Since the present invention has the above configuration, the drift of static convergence due to a temperature change or the like can be minimized with a simple circuit configuration as compared with a conventional convergence circuit.

In particular, when a circuit configuration in which an amplifier and a coil are DC-coupled from a small signal system is used, the feedback loop for correction is equivalent to a kind of protection circuit, improving the reliability and safety of the circuit and ensuring stable operation. And the like.

Further, in the present invention, since the DC component obtained from the DC level detection circuit is converted into a digital amount, the change amount of the DC component can be obtained by digital addition and subtraction, and the digital correction amount of the frame memory can be obtained. Even when rewriting is performed in a direction in which the change amount decreases, processing can be performed by digital addition and subtraction. Therefore, there is an effect that convergence correction can be performed at low cost and with high accuracy compared to the case where an analog circuit is used.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a flowchart for explaining the operation of the present invention, FIG. 3 is an explanatory diagram of a DC detection signal for explaining the operation of the present invention, FIG. 4 is a view showing a cross hatch pattern, FIG. 5 is a view showing a cross pattern, FIG. 6 is a view showing a state of static convergence shift, and FIG. 7 is a block diagram of a conventional example. 6 ... frame memory, 7 ... non-volatile memory, 15 ... convergence correction coil, 17 ... DC level detection circuit, 19 ... register Y, 20 ... register X.

Claims (1)

(57) [Claims] An intersection of a mesh pattern that divides a horizontal direction into x and a vertical direction into y on a screen of a raster scan type color display device is defined as a digital convergence correction point, and a digital correction amount corresponding to each correction point is calculated. A frame memory for storing one plane and a non-volatile memory for storing several planes are provided. The digital correction amount of the frame memory is read out in synchronization with the deflection timing of the color display device, converted to an analog correction amount, and converted to an analog correction amount for the convergence correction coil. In a convergence correction device that supplies and corrects convergence, a DC level detection circuit that detects a DC component of a correction waveform flowing through the convergence correction coil, and a DC component obtained from the DC level detection circuit is converted into a digital amount. A / to convert
A D conversion circuit, a change amount detection unit that detects a change amount of a digital DC component output from the A / D conversion circuit, and the change amount decreases the digital correction amount of the frame memory according to the change amount. Provide a feedback loop to rewrite in the direction,
A convergence correction device wherein a drift of static convergence is corrected.