JP2646584B2 - Error correction arithmetic unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction operation device, and more particularly to branching of sub data in an intermediate relay station of a communication system in which sub data is multiplexed with main data, error correction encoded and transmitted. The present invention relates to an error correction operation device for insertion.

[Conventional technology]

Such a conventional error correction operation device will be described with reference to the drawings.

FIG. 1 is a block diagram showing an example of a conventional error correction operation device.

11 is an error correction decoding circuit, 12 is a frame synchronization circuit, 13
Is an error correction coding circuit.

Digital service channels (Digita
l Service channel (DSC) signals are multiplexed to obtain framed information data, calculate the redundant bits of the error correction code for each frame, and add the obtained redundant bits to each frame for errors. A sequence of correction codes is obtained.

Error correction code Then, the redundant bits are determined so that A (x) is divisible by the generator polynomial g (x). In other words, if the error correction code is expressed in vector as A = (a _n a _n-1 ... A _i ... A _o ) (2), the check matrix is set to H and A · H = 0. (3)

A signal whose error correction code sequence is received by the intermediate relay station thus obtained is defined as an input signal S1.

The error correction decoding circuit 11 composites the input signal S1 and outputs information data. The output information data is data in which the information data in the input signal S1 has been error-corrected and the speed has been converted to a low speed by an amount corresponding to the removal of the redundant bits.

The frame synchronization circuit 12 detects a time slot of the DSC signal in frame synchronization with the input information data, branches and outputs the DSC signal S2 from the information data, and inserts a new DSC signal S3 to be input.

The error correction encoding circuit 13 re-encodes the branched and inserted information data of the DSC signals S2 and S3 and outputs it as an output signal S4. At this time, time slots for adding redundant bits by converting the speed of the input information data at high speed are created.

[Problems to be solved by the invention]

As described above, the conventional error correction operation device performs the speed conversion of the information data twice, and thus requires two speed conversion circuits, and thus has a disadvantage of increasing the circuit scale.

An object of the present invention is to provide an error correction operation device having a small circuit scale.

[Means for solving the problem]

An error correction operation device according to the present invention is a reading means for reading out the sub data in code synchronization with a column of an error correction code obtained by adding a redundant bit to a block of information data obtained by multiplexing a sub data block with a main data block. Subtracting means for calculating a difference between the sub data read by the reading means and sub data to be newly input; calculating means for calculating a conversion amount of the redundant bit by using a difference output of the calculating means; Insertion conversion means for replacing the sub data in the sequence of the error correction code with the newly input sub data and adding the conversion amount to the redundant bits.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings showing examples.

FIG. 1 is a block diagram showing an embodiment of an error correction operation device according to the present invention.

The input signal S1, the DSC signals S2 and S3, and the output signal S4 in FIG. 1 are the same as those signals in FIG.

In the embodiment shown in FIG. 1, a synchronizing pulse which is word-synchronized with the input signal S1 and synchronized with the error correction code constituting the input signal S1
A word synchronizing circuit 1 for outputting the SP, a timing generating circuit 2 for outputting a timing signal TS representing the position of the time slot of the DSC signal S2 in the input signal S1 on the basis of the synchronizing pulse SP, and a clock terminal for the timing signal TS A flip-flop (hereinafter referred to as F / F) 3 which inputs a signal S1 to a data input terminal D and outputs a DSC signal S2 from a data output terminal Q, and a DSC signal S3 to be newly input to the CL. Subtraction circuit 4 that subtracts S2 and outputs difference signal DF
A conversion circuit 5 for calculating the conversion amount M using the difference signal DF; a redundant bit conversion circuit 6 for inputting the input signal S1 and adding the conversion amount M to the redundant bits in the input signal S1; And a DSC signal insertion circuit 7 that replaces the DSC signal S2 with the DSC signal S3 in the output of the circuit 6 and outputs it as an output signal S4.

The F / F 3 reads the time slot data at the timing of the timing signal TS from the input signal S1, so that the read data is the TSC signal S2 included in the input signal S1.

The error correction code constituting the input signal S1 is expressed by two equations,
The a _i corresponding to the DSC signal S2 to a B · H = 0 ...... an error correction code when replaced by b _i corresponding to the DSC signal S3 as B (4) is the redundant bits (bi- ai) × Hi (5) It is necessary to add a value (conversion amount) corresponding to (where Hi is the element of the i-th row of the check matrix H).

The subtraction circuit 4 outputs the value (bi-ai) as a difference signal DF,
The conversion amount calculation circuit 5 performs the calculation of the equation (5) and outputs a conversion amount M. Therefore, the output signal S4 obtained by adding the conversion amount M to the redundant bits in the input signal S1 and inserting the DSC signal S3 is obtained by branching the DSC signal S2 from the information data in the input signal S1 and inserting the DSC signal S3. It is a sequence of error correction codes obtained by encoding the information data.

As described above, the embodiment shown in FIG. 1 does not require the speed conversion of the information data.

The redundant bit conversion circuit 6 may be arranged after the DSC signal insertion circuit 7.

〔The invention's effect〕

As described in detail above, the error correction operation device of the present invention calculates the conversion amount from the difference between the inserted sub data and the branched sub data, adds the conversion amount to the redundant bits in the input signal, and calculates the conversion amount in the output signal. Since the redundant bits are obtained, the sub-data can be branched and inserted without changing the speed of the information data, and there is an effect that the circuit scale is small because no speed conversion circuit is required.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an error correction operation device according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional error correction operation device. 1... Word synchronization circuit, 2... Timing generation circuit, 3
... flip-flop (F / F), 4 ... subtraction circuit, 5 ...
... Conversion amount operation circuit, 6 ... Redundant bit conversion circuit, 7 ...
DSC signal insertion circuit.

Claims (1)

(57) [Claims] A reading means for reading out the sub-data in synchronism with a sequence of an error correction code obtained by adding a redundant bit to a block of information data obtained by multiplexing a sub-data block with a main data block; Subtracting means for calculating a difference between the sub data read by the means and sub data to be newly input; calculating means for calculating a conversion amount of the redundant bit using a difference output of the subtracting means; and the error correction code And an insertion conversion unit that replaces the column data in the column with the sub data to be newly input and adds the conversion amount.