JP2648003B2 - Timer counter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a timer counter, and more particularly, to a programmable timer counter built in a microcomputer or the like.

[Conventional technology]

Conventionally, there are various types of timer counters built in a one-chip microcomputer or the like, and FIG. 3 shows an example of a type in which the measurement time taken here can be set by software.

Referring to FIG. 3, a conventional timer counter includes a counter 1 having a predetermined bit length operated by a clock pulse CLK and a comparison value setting register having the same bit length as the counter 1 for setting the value of the counter 1 as a comparison value. 2 and a comparison circuit 3 for comparing the values of the comparison value setting register 2 and the counter 1 and outputting a coincidence signal CO when both coincide with each other, and an internal bus 8 for inputting / outputting the above data and commands. Was composed.

Next, the operation of the conventional timer counter shown in FIG. 3 will be described.

First, the value of the measurement time of the counter 1 is stored as the comparison value B in the comparison value setting register 2 via the internal bus 8.

Next, when the counter initialization signal IN is applied to the counter 1, the counter 1 is initialized, that is, reset, and starts counting the clock pulse CLK. Count value output A of counter 1 and comparison value setting register 2
When the comparison value B coincides with the comparison value B, the comparison circuit 3 outputs a coincidence signal CO, which is used as a timer output TO for an interrupt signal or the like of the microcomputer.

[Problems to be solved by the invention]

The conventional timer counter described above has a disadvantage that the maximum value of the measurement time is limited by the bit length of the counter 1.

One-chip microcomputers equipped with this kind of timer counter have been applied to various applications, and the requirements for time measurement in those applications are also various. Therefore, there is a drawback that the application range is restricted by the limitation of the measurement time. Was.

[Means for solving the problem]

The timer counter of the present invention includes: a first counter that counts clock pulses; a storage unit that can operate as a counter that sets a predetermined value as a comparison value; a count value of the first counter and the storage unit A comparator that outputs a match signal when the comparison values are set to match, and sets an external control signal to count the clock pulse using the first storage unit as a counter and set the storage unit to the first storage unit. Operation mode switching means for setting to operate in series with the above counter.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

Referring to FIG. 1, a timer counter according to the present invention includes a counter 1 having a predetermined bit length operated by a clock pulse CLK and a counter 1 for setting a numerical value of the counter 1 as a comparison value, as in the conventional example. Comparison value setting register 2 having the same bit length, comparison value setting register 2 and counter 1
In addition to the portion composed of the comparison circuit 3 for comparing the two values and outputting a coincidence signal CO when the two coincide with each other, and the internal bus 8 for inputting and outputting data and commands, the following: Has been added.

That is, the first switching circuit 4 for turning on / off the clock pulse CLK with respect to the comparison value setting register 2, and the counting pulse input of the counter 1 are connected to the clock pulse CLK and the overflow output signal OF 2 from the comparison value setting register 2. A second switching circuit 5 for switching the output TO of the timer counter, an output CO of the comparison circuit 3 and an overflow output signal from the counter 1, and a program via the internal bus 8. Mode register 7 which is a register for controlling the first to third switching circuits 4 to 6
And

The comparison value setting register 2 is basically a well-known parallel input shift register, which inputs data in parallel when setting a comparison value, but operates as a counter by applying a clock pulse CLK. is there.

 Next, the operation of the present embodiment will be described.

First, a case where “0” is written to the mode register 7 will be described.

In this case, the timer counter enters the program mode, the first switching circuit 4 is turned off, the second switching circuit 5 is switched to the clock pulse CLK, and the third switching circuit 6 is switched to the comparison circuit output CO.

Therefore, this case is the same as the above-mentioned conventional example,
Since the description is duplicated, it is omitted so as not to be redundant.

Next, a case where "1" is written to the mode register 7 will be described.

In this case, the timer counter is set to the extension timekeeping mode, the first switching circuit 4 is turned on, and the second switching circuit 5 outputs the third signal to the overflow output signal OF2 from the comparison value setting register 2.
The switching circuit 6 outputs the overflow output signal OF from the counter 1
Each can be switched to 1.

Therefore, the comparison value setting register 2 operates as a counter, and the counter 1 receives the overflow output signal OF2 when the comparison value setting register 2 operates as a counter instead of the clock pulse. 2 and the counter 1 are connected in series. As described above, since the bit lengths of the counter 1 and the comparison value setting register 2 are the same, a counter having a double bit length is obtained as a result.

The output of the timer counter becomes the overflow output signal OF1 of the counter 1.

 Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

The difference from the first embodiment shown in FIG.
An external input terminal TS is provided instead of the mode register 7 which is a register for controlling the switching circuits 4 to 6, and the above switching circuits are controlled by a mode control signal from the outside.

The other parts are the same as those of the first embodiment, and the description will be duplicated.

The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments, and various modifications can be made.

〔The invention's effect〕

As described above, the present invention operates the storage means as the second counter when the extension timing is required, and operates the storage means in series with the first counter, so that the time length of the counter is longer than that of the conventional counter. This has the effect that it can be significantly extended.

Therefore, the conventional standard timer-counter operation,
There is an effect that the two kinds of operation modes of the above-mentioned extended timing operation can be selected according to the purpose.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing an example of a conventional timer counter. . 1 counter, 2 comparison value setting register, 3 comparison circuit, 4 first switching circuit, 5 second switching circuit, 6
... Third switching circuit, 7... Mode register, 8... Internal bus, TS... External input terminal.

Claims (3)

(57) [Claims] 1. A counter for counting clock pulses, a comparison value setting register that sets a predetermined value as a comparison value and operable as a counter, and sets a count value of the counter and the comparison value setting register. A comparison circuit that compares the comparison values and outputs a coincidence signal when they match, and sets the comparison value setting register so as to count the clock pulse by using the comparison value setting register as a counter by a control signal. The counter is set to operate in series with the counter, and when there is no control signal, the coincidence signal from the comparison circuit is output, and when there is the control signal, the output signal of the counter is output as a timer signal. A timer counter. 2. The timer counter according to claim 1, wherein the comparison value setting register is a parallel shift register having a bit length equal to that of the first counter. 3. The timer counter according to claim 1, wherein said control signal is programmed in advance.