JP2648086B2 - Reference current generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference current generating circuit capable of providing a matched current source and current sink reference current.

[0002]

2. Description of the Related Art Current generating circuits are known in the art and, in the simplest form, consist of a pair of matched current mirror transistors, each current mirror transistor having a controllable path. And a control node for controlling the degree of conduction of the controllable path. In bipolar technology, the control node is the base and the controllable path is the path from the collector to the emitter. On the other hand, MO
In S technology, the control node is the gate and the controllable path is the source / drain channel.

[0003] The present invention particularly, but not exclusively, relates to bipolar technology. One of these transistors has a current setting resistor connected in its controllable path, and its control node connects to the control node of one of the transistors and has its own controllable path. Connected to When a current flows through the current setting resistor, the same current also flows in the controllable path of the other transistor and is related to the current via the area ratio between the output transistor and the current mirror transistor. It can be used to drive an appropriate output transistor to generate a reference current. Another pair of matched current mirror transistors is connected in series with the first pair between the power supply voltage and ground, and drives the output transistor to generate a sink reference current. In practice, a basic current mirror circuit has many limitations. One of those restrictions
First, when connected to another circuit, its impedance is too low for it to act as a complete current sink or sink. In order to increase the impedance, it is common to provide a pair of matched cascode transistors connected to each current mirror transistor for each of the source and sink current generating portions.

FIG. 1 shows a source / sink current generating circuit of this type. This circuit has a first current mirror circuit for generating a source current and a second current mirror circuit for generating a sink current. The first current mirror circuit has a first set of matched PNP bipolar transistors Q1, Q2. These transistors have their emitters connected to the power supply voltage Vdd and their bases connected together.
In a conventional current mirror configuration, the base of the second transistor Q2 is connected to its collector. Similarly, a second set of transistors Q3 and Q4 connected in cascode to the first set.

[0005] The second current mirror circuit has a third set of matched NPN transistors Q5, Q6 connected in the form of a current mirror. The collectors of these transistors Q5 and Q6 are respectively connected to transistors Q3 and Q6.
4 connected to the emitter. The second current mirror circuit also has a fourth set of transistors Q7 and Q8 cascode-connected to the third set of transistors Q5 and Q6.

A set of output transistors Q9 and Q10 connected to the first current mirror circuit and a set of output transistors Q connected to the second current mirror circuit
11, Q12 are provided. As is known, the collector current I flowing through the output transistors Q9 and Q10 is
_source is related to the collector current flowing through transistors Q2 and Q4. Similarly, the current I _sink flowing through output transistors Q11 and Q12 is related to the collector current flowing through transistors Q6 and Q8. This collector current is set by a current setting resistor R connected to the emitter of the transistor Q8. Therefore, the _sink current I _sink and the _source current I _source are
Both are related to the collector current set by the resistor R. Thus, as long as the dimensions of the current mirror transistors in the first and second current mirror circuits are substantially the same, their sink current and source current are substantially matched.

However, the circuit of FIG. 1 is not satisfactory under certain circumstances. In particular, if a particular manufacturing process has significant processing variations affecting the transistor, the currents I _sink and I _source are no longer properly matched. This means
In part, process variations affect PNP transistors differently than for NPN transistors,
Therefore, the current sinking portion of the circuit is affected differently than the current draining portion of the circuit.

A typical use of a current generating circuit of the type shown in FIG. 1 is for providing a plurality of current sinks and / or current sinks. To do so, separate sets of transistors corresponding to transistors Q9, Q10 for current sinking and transistors Q11, Q12 for current sinking are connected in parallel to provide a separate current generating configuration. The current sinking portion of this circuit is taken as an example, and a case is considered in which n sets of transistors are connected in parallel with transistors Q11 and Q12, each of which has the same dimensions as transistors Q11 and Q12. The base current required to drive the output transistor is nIb, where Ib is the transistor Q11, Q11
12 is the base current supplied to each base. This base current is derived from the collector currents of transistors Q5 and Q8, respectively.

In the case of a single set of output transistors,
It is assumed that the base current is very small compared to the collector current, and therefore does not significantly affect the operation of the current mirror circuit. However, when a significant number of extra sets of transistors are connected to provide multiple current sinks, the amount of base current that needs to be supplied increases and the collector in the current mirror circuit increases. This affects the current, and thus the reference current, and also affects the matching state of the sink current and the discharge current. The ability to drive these sets of transistors without adversely affecting the reference current is referred to as the fanout capability of the circuit.

FIG. 1 shows the magnitude of the current flowing in each branch of the circuit, where n is the number of sets of output transistors, Ibp is the base current of the P-type transistor and Ibn. Is the base current of the N-type transistor. Therefore, the following equation is established.

I _source = n [I− (2n + 5) Ibp + nIbn] I _sink = n [I− (2n + 5) Ibp−2Ibn] Therefore, the mismatch current I _mismatch = I _source −I
_sink = n [nIbn + 2Ibn] = n (n + 2) Ibn
And therefore depends on both n and Ibn. Therefore,
In the case of the circuit of FIG. 1, a mismatch current always exists,
It increases as n increases.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a current generating circuit capable of maintaining a state in which a source current and a sink current are substantially matched irrespective of process fluctuations. is there.

Another object of the present invention is to overcome the disadvantages of the prior art as described above, to have a high DC power rejection ratio and to operate at low power supply voltages (at least 1.4V). To provide a possible circuit.

[0014]

According to one aspect of the present invention, a source / sink current generation circuit is provided. A first set of matched transistors of one conductivity type is provided connected as a first current mirror to drive the current source output transistors. A second set of matched transistors of opposite conductivity type is provided connected as a second current mirror to drive the current sink output transistor. The first set and the second set are connected in series between the first reference voltage and the second reference voltage. A current setting load is provided connected to one of the first current mirror and the second current mirror to set the magnitude of the source current and sink current to be output from the current source and current sink output transistors, respectively. I have. A bias comprising a control node connected in a common controllable path with the first and second current mirrors and having a controllable path connected between the first and second current mirrors A transistor is provided.

Preferably, the first current mirror has a third set of matched transistors of one conductivity type cascode-connected to the first set. Further, preferably, the second current mirror has a fourth set of matched transistors of the opposite conductivity type cascoded with the second set of transistors.

In a preferred embodiment, the first current mirror circuit has a first set of bipolar PNP transistors, their emitters are connected to a power supply voltage and their bases are connected together. I have. The base of one of these transistors is connected to its own collector. The collector of the first set of transistors is connected to the emitter of the third set of transistors,
The third set of transistors is also a bipolar PNP transistor. A third set of transistors has their bases connected together. The collector of the third set of transistors is connected to the collector of the fourth set of transistors, the fourth set of transistors being bipolar NPN transistors.

The bases of the fourth set of transistors are connected together, and the base of one of these transistors is connected to its own collector. The second set of transistors is also a bipolar NPN transistor, and their bases are commonly connected. The base of one of the second set of transistors is connected to its own collector. The collectors of the second set of transistors are connected to the emitters of the fourth set of transistors, forming a cascode arrangement. The emitters of the second set of transistors are connected to ground, and one emitter of the second set of transistors is connected to ground via a current setting load. Preferably, the current setting load is a resistor. In this configuration, the biasing transistor comprises a bipolar NPN transistor, the collector of which is connected to the bases of the transistors in the third set, and the emitter of which is connected to the bases of the transistors in the second set. . The base of the biasing transistor is connected to the collector connection between the third and fourth sets of transistors.

In this specification, the term "matched transistor" is used to mean a transistor whose collector current is substantially the same under the same conditions.

[0019]

FIG. 2 shows a circuit constructed according to an embodiment of the present invention. In this circuit and the circuit shown in FIG. 1, the same transistors are denoted by the same reference numerals. The circuit of FIG. 2 has an extra NPN transistor Q13 whose base is connected to the collector of transistor Q5, whose collector is connected to the bases of transistors Q3 and Q4, and whose emitter is transistor Q7. , Q8. The base of transistor Q5 is no longer connected to its collector. Instead, the base of transistor Q6 is connected to the collector of transistor Q6. Otherwise, the circuit is identical to that shown in FIG.

FIG. 2 further shows a suitable start-up circuit, as indicated by dashed line 10. This start-up circuit has a PNP transistor Q16, whose base is connected to the bases of the transistors Q1 and Q2, whose emitter is connected to the power supply voltage Vdd, and whose collector is connected to another NPN transistor Q1.
4 connected to the base. The emitter of transistor Q14 is connected to ground, and its collector is connected to a resistor R2.
To the power supply voltage Vdd. Another diode-connected transistor Q15 is provided,
Its base is the collector of transistor Q14 and resistor R2.
And its emitter is connected to the base of an additional transistor Q13. This start-up circuit is shown only as an example,
Of course, other start-up circuits can be used with the circuit of the present invention.

For frequency stability, the transistor Q
It is possible to connect a capacitor C between the base of the transistor 13 and the base of the transistor Q5.

Transistor Q13 has several important effects. By maintaining the collector voltage of the transistor Q3 at a fixed value (VbeQ7 + VbeQ13) higher than the ground, the so-called "Early effect" that causes the source current and the sink current generated by the present circuit depending on the power supply voltage is removed. I have. This significantly improves the DC power rejection ratio for this circuit. Such Early effects and their elimination are described in more detail in the earlier filed UK Patent Application No. 9223338.6.

The additional transistor Q13 also has a surprising effect. When the source current and the sink current are calculated by analyzing the current flowing through the circuit, the equations for the source current and the source current are as follows.

I _source = n × (I− (2n + 5) × Ib
p + 2 (n + 1) × Ibn) I _sink = n × (I− (2n + 5) × Ibp + 2 (n +
1) × Ibn) Here, I is a reference current. Therefore, I _mismatch = I
_source- I _sink = 0. The current flowing in each branch of the circuit is shown in FIG. These were derived by employing Kirchhoff's law and the usual equations for NPN and PNP transistors at each location. The derivation of the current in each part of the circuit is obvious to a person skilled in the art, so the description in this specification is omitted.

In the above equation, n is the transistor Q
12 is the area ratio between Q12 and Q7 and between transistors Q10 and Q3. Since the same equations apply to I _source and I _sink , the circuit is almost completely immune to process variations that affect PNP and NPN transistors differently. Absent. Ibp and Ibn are the base currents of the PNP transistor and the NPN transistor, respectively.

FIG. 4 shows the relationship between the generated current in μA and the power supply voltage for the circuit of FIG. 2 for n = 1. The following values can be deduced from FIG.

(1) DC PSRR １０ nominal 10 μA (n = 1) = (10.0077 μA-10.09 μA) / (7.0
V-2.3V) = 14.5 nA / V or 1450 ppm / V (2) ＠ Vdd = 2.5 V, I = 10 μA, I _sink =
I _source = nominal 10 μA current mismatch percentage = (I _source −I _sink ) / Inom × 100% = (10.018 μA−10.13 μA) / 10 μA
× 100% = 0.05% FIG. 5 shows a similar graph when n = 10. As described above, n is the area ratio between the transistors Q12 and Q7 and between the transistors Q9 and Q1. n can be obtained by making the transistor Q12 n times the size of the transistor Q7 in order to provide a sink current that is 10 times the current I set by the current setting resistor R. On the other hand, it is possible to connect and provide n sets of output transistors in parallel with the transistors Q11 and Q12 and the transistors Q9 and Q10.
Each transistor has the same dimensions and is equal to that of transistors Q7 and Q3. This is shown in FIG. 3a, where the current generating circuit is schematically illustrated by the blocks "current sink generator" and "current source generator". In this case, the ideal current generator is capable of generating the same current I in each set of transistors, and the current sum nI is the current I set by the current setting resistor. N times. The following values can be derived from the graph of FIG.

(1) DC PSRR １００ Nominal 100μ
A (n = 10) = (100.337 μA−99.322 μA) / (7.
0 V-2.3 V) = 237 nA / V or 2370 ppm (2) ＠ Vdd = 2.5 V, I = 10 μA, I _sink =
I _source = 100 μA nominal Current mismatch percentage = (I _source −I _sink ) /Inom×100%=99.628 μA−99.473 μA) / 100 μA
× 100% = 0.15% (3) Current nI = 99.6 with respect to a nominal value of 100 μA
FIG. 6 is a similar diagram for the circuit of FIG. 3, for n = 1, having a weak NPN transistor and a strong PNP transistor. this is,
May occur as a result of severe processing fluctuations. The following values can be derived from the graph of FIG.

(1) DC PSRR １０ Nominal 10 μA = (11.021 μA−10.980 μA) / (7.0)
V-2.3V) = 8.7 nA / V or 790 ppm / V (2) ＠ Vdd = 2.5 V, I = 10 μA, I _sink =
I _source = nominal 10 μA Current mismatch percentage = (I _source −I _sink ) / Inom × 100% = (10.991 μA-10.895 μA) / 11 μA
× 100% = 0.05% FIG. 7 shows a graph of the Vs voltage and the generated current for the conventional circuit of FIG. 1 for n = 1, which can derive the following values: is there.

(1) DC PSRR １０ Nominal 10 μA (n = 1) = (10.130 μA−9.977 μA) / (7.0 V)
-2.3 V) = 32.6 nA / V or 3260 ppm / V (2) ＠ Vdd = 2.5 V, I = 10 μA, I _sink =
I _source = nominal 10 μA Current mismatch percentage = (I _source −I _sink ) / Inom × 100% = (10.367 μA-10.024 μA) / 10 μA
× 100% = 3.43% Therefore, the characteristics of the circuit of FIG. 3 are more advantageous than those of these figures. FIG. 8 shows a similar graph for the circuit of FIG. 1 for n = 10. The following numbers can be derived:

(1) DC PSRR ＠ Nominal 100 μA = (72.200 μA−70.402 μA) / (7.0)
V-2.3V) = 382.5 nA / V or 5664 ppm / V (2) ＠ Vdd = 2.5 V, I = 10 μA, I _sink =
I _source = 100 μA nominal Current mismatch percentage = (I _source −I _sink ) / Inom × 100% = (80.302 μA−70.760 μA) / 75 μA
× 100% = 12.7% (3) nI = 80 μA compared to the nominal value of 100 μ.

FIG. 8 shows that for n = 10, the conventional circuit cannot generate a current level of 100 μA, but can only generate a current of 70 μA to 80 μA. Is shown. It is further 12.
It has a high mismatch ratio of 7%. However,
In the case of the circuit of the present invention, as shown in FIG. 5, the source current and the sink current are each actually 100 μA. Therefore, it is understood that the present circuit has a high fan-out capability.

Although the specific embodiments of the present invention have been described in detail above, the present invention is not limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. Of course is possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a source / sink current generation circuit based on the prior art.

FIG. 2 is a circuit diagram showing a current source / sink generation circuit configured based on one embodiment of the present invention.

FIG. 3 is a circuit diagram showing currents at various branches in the circuit of FIG. 2;

FIG. 3a is a circuit diagram showing a plurality of output sets.

FIG. 4 is a graph illustrating the relationship between power supply voltage and source / sink current for a circuit according to the present invention.

FIG. 5 is a graph showing the relationship between power supply voltage and source / sink current for a circuit according to the invention having n = 10 sets of output transistors.

FIG. 6 shows a weak NP due to a process variation in a manufacturing stage.
FIG. 4 is a graph showing the relationship between power supply voltage and source / sink current for a circuit according to the present invention when an N transistor and a strong PNP transistor are generated.

FIG. 7 is a graph showing a relationship between a power supply voltage and source / sink current for the conventional circuit of FIG. 1;

8 is a graph showing the relationship between the power supply voltage and the source / sink current for the conventional circuit of FIG. 1 when connected to n = 10 sets of output transistors.

[Explanation of symbols]

 Q13 NPN transistor C capacitor 10 Startup circuit

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Gie Henro, Republic of Singapore, Singapore 1954, Florence Road 66 Sea (56) References JP-A-7-146725 (JP, A) JP-A-63-182723 (JP, A) JP-A-58-31422 (JP, A) JP-B-1-23802 (JP, B2)

Claims (5)

(57) [Claims] 1. A source / sink current generating circuit comprising: a first set of matched transistors of one conductivity type connected as a first current mirror for driving a current source output transistor; A second set of matched transistors of opposite conductivity type is provided that is connected as a second current mirror to drive the current sink output transistor, the first set and the second set being a first reference voltage and a second set. Connected in series between the reference voltage and the two current mirrors, and connected to one of the first and second current mirrors to set the magnitude of the source current and sink current to be output from the current source and current sink output transistors, respectively. And a control node connected to a common controllable path with the first and second current mirrors. And the biasing transistor is provided having a controllable path connected between the second current mirror, the current generating circuit, characterized in that. 2. The current generating circuit according to claim 1, wherein the current setting load is a resistor. 3. The current generator according to claim 1, wherein the first current mirror comprises a third set of matched transistors of the first conductivity type cascode-connected to the first set. circuit. 4. The device of claim 1, 2 or 3, wherein the second current mirror comprises a fourth set of matched transistors of the opposite conductivity type cascoded with the second set of transistors. Current generation circuit. 5. The transistor of claim 4, wherein the biasing transistor comprises a bipolar NPN transistor, the collector of which is connected to the base of the transistor in the third set, and the emitter of which is in the second set. A current generating circuit connected to a base of a transistor.