JP2650107B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a bipolar CMOS random access memory (hereinafter referred to as a bipolar CMOS RAM). It is about effective technology to use.

[Conventional technology]

There is a so-called ECL interface bipolar CMOS RAM compatible with ECL (Emitter Coupled Logic).

In a bipolar CMOS type RAM, the memory array is, for example, a high resistance load type N-channel MOSFET memory cell (nMOS).
Memory cell), and its memory peripheral circuits are bipolar transistors and CMOS (complementary MOSFET)
With this configuration, high integration, low power consumption, and high-speed operation of the circuit can be realized at the same time. In the bipolar CMOS type RAM, the reading operation is further speeded up by using a current sensing type reading circuit and compressing the amplitude of the reading signal.

The bipolar CMOS type RAM is described, for example, in "Nikkei Electronics", March 10, 1986, pp. 199 to 217, published by Nikkei McGraw-Hill.

[Problems to be solved by the invention]

FIG. 4 shows the bipolar CMOS type RA described above.
The circuit diagram of the readout circuit of M is shown. The bipolar CMOS type RAM includes a plurality of memory arrays M-ARY0 to M-ARY.
3 and column switches CSW0 to CSW3 and sense amplifiers SA0 to SA3 provided corresponding to each memory array. The collectors of the differential transistors T11 and T12 constituting these sense amplifiers are connected to complementary common collector lines r and r.
Through the cascade circuit of the data output buffer DOB. The output signal of the cascade circuit is further supplied to the differential transistor T via a corresponding emitter follower circuit.
2, transmitted to the main amplifier having T3 and T4 as the basic configuration.

The sense amplifiers SA0 to SA3 are controlled according to the selection signals s0 to s3.
Alternatively, the operation state is set. The read signal output from the selected memory cell MC is a voltage signal, for example, a complementary data line D0 • ▲ and a complementary common data line CD0 •.
The signal is transmitted to the sense amplifier SA0 via ▲ ▼. This read signal is converted into a current signal by the sense amplifier SA0, and transmitted to the cascade circuit of the data output buffer DOB via the complementary common collector lines rr. The cascade circuit returns the read signal to a voltage signal by the resistors R11 and R10, and sets the level of the complementary common collector line r to the forward voltage of the diode D1 and the transistor T17.
And a predetermined level determined by the base-emitter voltage of T18. The read signal returned to the voltage signal is transmitted to the main amplifier of the data output buffer DOB via the corresponding emitter follower circuit and further amplified. The output signal of the main amplifier is output from the open-emitter output transistor T1 via the data output terminal DO.
Sent out.

That is, in the bipolar CMOS type RAM, the signal amplitude of the complementary common data lines CD00 ▲ to CD3 ・ ▲▲ is compressed by using the current sensing type read circuit. Further, the read signal is transmitted to the cascade circuit as a current signal without fluctuation of the level of the complementary common collector line r. As a result, the transmission delay time of the read signal is reduced, and the bipolar CMOS type
The reading operation of the RAM is further accelerated.

However, the study by the present inventors has revealed that the above-described readout circuit has the following problems. That is, as described above, the read signal output from the selected memory cell is converted into a current signal by the corresponding sense amplifier. Therefore, each complementary common data line still needs a level difference of, for example, about several tens mV at the input terminal of the corresponding sense amplifier, that is, at the base of the differential transistor. This level difference is transmitted to the complementary common collector line r. Via the corresponding differential transistor, and as a result, the charge / discharge operation of a relatively large load capacitance coupled to the complementary common collector line r. . Therefore, a transmission delay occurs every time the read signal is inverted,
This limits the speed of the read operation of the bipolar CMOS type RAM.

An object of the present invention is to provide a current sensing type read circuit in which a signal transmission delay time is reduced. It is another object of the present invention to speed up a read operation of a bipolar CMOS type RAM or the like including a current sense type read circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
In a current sense type read circuit, a cascade circuit coupled to a complementary common collector line is connected to a differential amplifier for inverting and amplifying the potential difference of the complementary common collector line and a complementary output signal of the differential amplifier to a complementary common collector line. It comprises two sets of emitter follower circuits for transmitting a current signal transmitted and transmitted via a complementary common collector line to a voltage signal.

[Action]

According to the above means, the potential difference of the complementary common collector line is amplified and negatively fed back through the differential amplifier, so that the potential difference of the complementary common collector line is significantly reduced. The charge / discharge operation of the collector line can be shortened, the transmission delay time of the read signal by the complementary common collector line can be shortened, and the read operation of a bipolar CMOS RAM or the like can be further accelerated.

〔Example〕

FIG. 2 shows a bipolar CMOS to which the present invention is applied.
A block diagram of one embodiment of a type RAM is shown. The circuit elements constituting each block in FIG.
Although it is not particularly limited by the manufacturing technology of the CMOS integrated circuit, it is formed on one semiconductor substrate such as single crystal silicon.

FIG. 2 shows a bipolar CMOS type RA of this embodiment.
M is not particularly limited, but four memory arrays M-ARY
0 to M-ARY3. Each memory array is arranged at (m + 1) word lines arranged in the horizontal direction, n + 1 pairs of complementary data lines arranged in the vertical direction, and at the intersection of these word lines and the complementary data lines. ) × (n +
1) static memory cells.

The word lines constituting the memory arrays M-ARY0 to M-ARY3 are coupled to the X address decoder XDCR via the corresponding main word line, though not particularly limited, and are alternatively set to a high level selected state. .

The X address decoder XDCR is provided commonly to the four memory arrays M-ARY0 to M-ARY3. The X address decoder XDCR receives complementary internal address signals a x0 to a xi (here, for example, the non-inverted internal address signal ax0 and the inverted internal address signal ▲) from the X address buffer XADB.
Together with ▼, it is represented as a complementary internal address signal a x0.
The same applies hereinafter), and a timing signal φce is supplied from the timing control circuit TC. X address decoder
XDCR is selectively activated according to timing signal φce. In this operating state, the X address decoder XDCR decodes the complementary internal address signals a x0~ a xi, and alternatively selected one word line specified by the X address signal AX0～AXi.

The X address buffer XADB receives the ECL level X address signals AX0 to AXi supplied via the external terminals AX0 to AXi, and receives the complementary internal address signals a x0 to a xi at the CMOS level.
To form

On the other hand, the complementary data lines constituting the memory arrays M-ARY0 to M-ARY3 are connected to the corresponding complementary common data lines CD0, ▲ ▼ to CD3 via the corresponding column switches CSW0 to CSW3.
・ Selectively connected to ▲ ▼.

The column switches CSW0 to CSW3 are n + 1 provided corresponding to the respective complementary data lines of the corresponding memory array.
Includes a set of switch MOSFETs. Each set of switch MOSFETs is supplied with corresponding data line selection signals 0 to Yn from corresponding Y address decoders YDCR0 to YDCR3. These switch MOSFETs are connected to the corresponding data line select signal Y0
When the signals .about.Yn are alternatively set to the high level, the corresponding complementary data line and the complementary common data line are selectively connected.

The Y address decoders YDCR0 to YDCR3 are commonly supplied with j-1 bit complementary internal address signals a y0 to a yj-2 excluding the upper two bits from the Y address buffer YADB, and the timing signal φce from the timing control circuit TC. Is supplied. Y address decoders YDCR0 to YDCR3 are selectively activated according to timing signal φce. In this operating state, the Y address decoders YDCR0 to YDCR3
Decodes the complementary internal address signals a y0 to a yj-2 and selectively sets the data line selection signals Y0 to Yn to a high level.

The Y address buffer YADB receives the ECL level Y address signals AY0 to AYj supplied via the external terminals AY0 to AYj, and receives the complementary internal address signals a y0 to a yj at the CMOS level.
To form Of these, the complementary internal address signals a y0 to a yj-2 of j−1 bits excluding the upper 2 bits are commonly supplied to the Y address decoders YDCR0 to YDCR3, and the complementary internal address signals a yj−1 of 2 bits are used. ~ a yj is supplied to the array selection circuit ASEL.

The array selection circuit ASEL receives the upper 2 bits of the complementary internal address signal a yj- supplied from the Y address buffer YADB.
Decodes. 1 to a yj, is alternatively a selection signal S0 to S3. These selection signals s0 to s3 are supplied to corresponding sense amplifiers SA0 to SA3 and write amplifiers WA0 to WA3, respectively.

Complementary common data lines CD0 ・ ▲ ▼ ~ CD3 ・ ▲ ▼
Are coupled to the input terminals of the corresponding sense amplifiers SA0 to SA3, respectively, and are connected to the corresponding write amplifiers WA0 to WA3.
Output terminals.

The sense amplifiers SA0 to SA3 are connected to the complementary common data lines CD0 and
Includes a pair of differential transistors coupled to ▼ -CD3. One and the other collectors of the respective differential transistors are commonly coupled to a complementary common collector line r. Further, N-channel type driving MOSFETs receiving the selection signals s0 to s3 corresponding to the gates thereof are provided between the commonly coupled emitters of the respective differential transistors and the power supply voltage Vee of the circuit. These drive MOSF
The ET selectively functions as a current source circuit when the corresponding selection signals s0 to s3 are set to a high level.

When the bipolar CMOS type RAM is set to the read operation mode, the complementary common data lines CD0 ・ ▲ to CD3 ・ ▲
▼ indicates the corresponding memory array M-ARY0 to M-ARY3
The read signal output from the designated memory cell is transmitted. The read signal is a voltage signal as described later, and its amplitude is relatively small. The sense amplifiers SA0 to SA3 are alternatively activated by setting the corresponding selection signals s0 to s3 to high level. In this operating state, the sense amplifiers SA0 to SA3 convert the read signals supplied via the corresponding complementary common data lines CD0 ・ ▲ to CD3 ▲▲ into current signals, and transmit them to the complementary common collector lines r I do.

The complementary common collector line r
B is coupled to the cascade circuit. Data output buffer D
OB includes a cascade circuit coupled to the complementary traffic collector line r, a main amplifier receiving the output signal of the cascaded circuit, and an open-emitter output transistor receiving the output signal of the main amplifier, as described later. . The timing signal φoe is supplied from the timing control circuit TC to the main amplifier of the data output buffer DOB.

As will be described later, the cascade circuit of the data output buffer DOB returns the read signal transmitted via the complementary common collector line r to a voltage signal, and clamps the potential of the complementary common collector line r to a predetermined level. Further, it has a function of compressing a potential difference between the non-inverted signal line r and the inverted signal line. The read signal returned to the voltage signal by the cascade circuit is supplied to the main amplifier of the data output buffer DOB via the corresponding emitter follower circuit.

The main amplifier of the data output buffer DOB is selectively activated according to the timing signal φoe in the read operation mode of the bipolar CMOS type RAM. In this operating state, the main amplifier further amplifies the read signal transmitted from the cascade circuit and sends it out through the open-emitter output transistor.

Bipolar CMOS type RAM including sense amplifiers SA0 to SA3, complementary common collector line r, and data output buffer DOB
The specific circuit configuration and operation of the read circuit will be described later in detail.

On the other hand, the input terminals of the write amplifiers WA0 to WA3 are further connected to a data input buffer DI via a complementary write signal line w.
Commonly coupled to B output terminal. Light amplifier WA0-WA3
Are supplied with selection signals s0 to s3 from the array selection circuit ASEL. The data input buffer DIB is supplied with the timing signal φwe from the timing control circuit TC.

The data input buffer DIB is selectively activated according to the timing signal φwe in the write operation mode of the bipolar CMOS type RAM. In this operation state, the data input buffer DIB converts the write data at the ECL level supplied through the data input terminal DI into a complementary write signal at the MOS level, and outputs a complementary write signal line w.
To the write amplifiers WA0 to WA3.

The write amplifiers WA0 to WA3 are alternatively activated by setting the corresponding selection signals s0 to s3 to high level. In this operating state, the write amplifiers WA0 to WA3
From the data input buffer DIB to the complementary write signal line w
Are transmitted to the corresponding complementary common data lines CD0 • ▲ to CD3 • 〜.

The timing control circuit TC forms the above-mentioned various timing signals based on a chip select signal ▼ and a write enable signal ▼ which are supplied as control signals from the outside, and supplies them to each circuit.

FIG. 1 is a circuit diagram showing one embodiment of the reading circuit of the bipolar CMOS type RAM shown in FIG. In the following figures, the MOSFET with an arrow added to its channel (back gate) portion is a P-channel type and is distinguished from an N-channel MOSFET without an arrow. The illustrated bipolar transistors are all NPN transistors.

In FIG. 2, memory arrays M-ARY0 to M-ARY3
Is m + 1 arranged in the horizontal direction in FIG.
These word lines W0 to Wm, n + 1 sets of complementary data lines D0 ・ to Dn ・ ▲ arranged in the vertical direction, and the intersections of these word lines and the complementary data lines are arranged in a grid (m + 1 ) × (n + 1) static memory cells.

Each static memory cell is a memory cell of FIG.
As represented by MC1, an N-channel drive MOSFET Q11 having a gate and a drain cross-coupled to each other
And Q12. The sources of these drive MOSFETs Q11 and Q12 are coupled to the power supply voltage Vee (second power supply voltage) of the circuit. Although not particularly limited, the power supply voltage Vee is, for example, −
Negative power supply voltage such as 5.2V. Drain of drive MOSFETs Q11 and Q12 and circuit ground potential (first power supply voltage)
Are provided with resistors R6 and R7, respectively. resistance
R6 and R7 prevent the gate voltage of the memory cell MC1 from dropping due to leakage current when the storage data of logic “1” or logic “0” is stored and the corresponding drive MOSFET Q12 or Q11 is turned on. It is designed to have the highest possible resistance.

The drains of the drive MOSFETs Q11 and Q12 serve as the non-inverting and inverting input / output nodes of the memory cell MC1, respectively. These input / output nodes are N-channel type transmission gate MOSF
Via ETQ13 and Q14, the corresponding complementary data line D0
It is combined with ▼. The gates of transmission gate MOSFETs Q13 and Q14 are commonly coupled to corresponding word line W0.

When the word line W0 is at a low level, the transmission gate MO
SFETs Q13 and Q14 are both turned off, and memory cell MC
1 is separated from the complementary data line D0. When the word line W0 is alternatively set to the high-level selection state, the transmission gate MOSFETs Q13 and Q14 are both turned on, and the memory is provided between the non-inversion signal line and the inversion signal line of the complementary data lines D0 and ▲ ▼. A predetermined level difference occurs according to the data stored in cell MC1. This level difference is transmitted from the complementary data line D0 ・ to the complementary common data line CD0 ・ ▲ as a read signal of the memory cell MC1. When the bipolar CMOS type RAM is set in the write operation mode, the complementary common data lines CD0,
For ▲, a complementary write signal is supplied from the write amplifier WA0. This complementary write signal is written to the memory cell MC1 as new storage data when the word line W0 is set to the high level and the transmission gate MOSFETs Q13 and Q14 are turned on.

Complementary data lines D0 and ▲ constituting the memory array M-ARY0
▼, on the other hand, is coupled to the ground potential of the circuit via P-channel MOSFETs Q1 and Q2. These MO
SFETs Q1 and Q2 are always on by their gates being coupled to the supply voltage Vee of the circuit, and the load MOSFETs
Function as

Complementary data lines D0 and ▲ constituting the memory array M-ARY0
On the other side, 相 補 is selectively connected to complementary common data lines CD0 ・ ▲ via two corresponding sets of switch MOSFETs Q3 ・ Q15 and Q4 ・ Q16 of column switch CSW0. The gates of the N-channel type switch MOSFETs Q15 and Q16 of the column switch CSW0 are commonly connected, and the corresponding data line selection signal Y0 is supplied from the column address decoder CDCR. Similarly, the gates of the P-channel switch MOSFETs Q3 and Q4 of the column switch CSW0 are commonly coupled, and an inverted signal of the data line selection signal Y0 by the inverter circuit N1 is supplied. These switch MOSFETs are simultaneously turned on when the corresponding data line selection signal Y0 is alternatively set to a high level, and the complementary data lines D0 and ▲
▼ and complementary common data lines CD0 and ▲ ▼ are selectively connected.

The complementary common data lines CD0 and ▲ ▼ are connected to the sense amplifier S
They are respectively coupled to the bases of the differential transistors T11 and T12 (first differential transistors) constituting A0. The complementary common data lines CD0 and ▼ are also coupled to an output terminal of a write amplifier WA0 (not shown). Similarly, complementary common data lines CD1, ▲ ▼ to CD3, ▲ ▼ are respectively coupled to the bases of similar differential transistors constituting corresponding sense amplifiers SA1 to SA3, and are connected to corresponding write amplifiers WA1 to WA3. Each is coupled to an output terminal.

An N-channel drive MOSFET Q17 is provided between the commonly coupled emitters of the differential transistors T11 and T12 and the power supply voltage Vee of the circuit. The gate of the MOSFET Q17 is supplied with a selection signal s0 from the array selection circuit ASEL. Similarly, between the common-coupled emitters of the differential transistors constituting the sense amplifiers SA1 to SA3 and the power supply voltage Vee of the circuit, similar drive MOSFETs receiving the selection signals s1 to s3 corresponding to the gates thereof are provided. Each is provided.

The collectors of the differential transistors T11 and the like constituting one of the sense amplifiers SA0 to SA3 are commonly coupled to a non-inverted signal line r of a complementary common collector line. Similarly, the sense amplifier SA0
To SA3, the collectors of the other differential transistor T12 and the like are commonly coupled to the inverted signal line. The complementary common collector lines r. Are respectively coupled to bases of differential transistors T9 and T8 forming a cascade circuit of the data output buffer DOB.

The differential transistors T11 and T12 of the sense amplifiers SA0 to SA3 are connected to the corresponding MOSFETs when the selection signals s0 to s3 are set to the high level.
When Q17 and the like are turned on, they are alternatively turned on. In this operating state, the differential transistors T11 and T11
12 and the like form a current signal in accordance with a read signal transmitted from a selected memory cell via a corresponding complementary data line and a complementary common data line, and form a complementary common collector line r.
To supply. That is, the read signal output from the selected memory cell as a voltage signal is converted by the corresponding sense amplifiers SA0 to SA3 as a current signal for the complementary common collector lines r and r.

The cascade circuit of the data output buffer DOB includes a differential amplifier having the above-described differential transistors T8 and T9 (second differential transistors) as a basic configuration, and two sets of emitter follower circuits having a basic configuration of the transistors T7 and T10. including.
Load resistors R3 and R4 are provided in the circuit between the collectors of the differential transistors T8 and T9 and the ground potential of the circuit, respectively.
A constant current source IS5 is provided between the commonly coupled emitters of the differential transistors T8 and T9 and the power supply voltage Vee of the circuit. The collectors of the differential transistors T8 and T9 are further coupled to the bases of the transistors T7 and T10, respectively.

A load resistor R2 is provided between the collector of the transistor T7 and the ground potential of the circuit. Further, the emitter of the transistor T7 is coupled to the base of the differential transistor T8, that is, the inverted signal line of the complementary common collector line, and further coupled to the power supply voltage Vee of the circuit via the constant current source IS4. Similarly, a load resistor R5 is provided between the collector of the transistor T10 and the ground potential of the circuit. Also transistors
The emitter of T10 is coupled to the base of the differential transistor T9, ie, the non-inverted signal line r of the complementary common collector line, and further coupled to the circuit power supply voltage Vee via the constant current source IS6. The transistors T7 and T8, together with the corresponding resistors R2 and R5 and the constant current sources IS4 and IS6, form two sets of emitter follower circuits.

The cascade circuit converts a read signal transmitted as a current signal via the complementary common collector line r to a voltage signal. That is, a read signal output from the selected memory cell via the corresponding complementary data line and complementary common data line is converted into a current signal for the complementary common collector line r by the corresponding sense amplifiers SA0 to SA3. . Changes in these current signals increase or decrease the current drawn by the two sets of emitter follower circuits in the cascade circuit. As a result, the voltage drops of the resistors R5 and R2, that is, the collector voltages of the transistors 10 and T7 are changed.

The cascade circuit further comprises a complementary common collector line r.
Has a so-called equalizing function of compressing the potential difference between the non-inverted signal line and the inverted signal line. That is, as described above, the complementary common collector line r. Is respectively coupled to the bases of the differential transistors T9 and T8 constituting the differential amplifier of the cascade circuit. When the potential of the non-inverted signal line of the complementary common collector line r · becomes higher than that of the inverted signal line, the collector current of the transistor T9 increases, and conversely, the collector current of the transistor T8 decreases. Therefore, the collector voltage of the transistor T9 decreases, and the emitter voltage of the transistor T10, that is, the potential of the non-inverting signal line r of the complementary common collector line decreases. Further, as the collector current of the transistor T8 decreases, the collector voltage of the transistor T8 increases, and the emitter voltage of the transistor T7, that is, the potential of the inverted signal line of the complementary common collector line increases. On the other hand, when the potential of the non-inverted signal line of the complementary common collector line r · becomes lower than that of the inverted signal line, the collector current of the transistor T9 decreases, and conversely, the collector current of the transistor T8 increases. Therefore, the collector voltage of the transistor T9 increases, and the emitter voltage of the transistor T10, that is, the potential of the non-inverting signal line r of the complementary common collector line is increased. Also, as the collector current of the transistor T8 increases,
The collector voltage of the transistor T8 decreases and the transistor
The emitter voltage of T7, that is, the potential of the inverted signal line of the complementary common collector line is lowered. That is, the potential difference of the complementary common collector line r is inverted and amplified by the differential amplifier including the differential transistors T9 and T8, and is negatively fed back to the complementary common collector line r via the corresponding emitter follower circuit. As a result, the potential difference between the complementary common collector lines r is equalized, and is always set to substantially the same potential.

Complementary output signal or transistor of cascade circuit
The collector voltages of T10 and T7 are transmitted to the bases of the differential transistors T2 and T4 constituting the main amplifier via an emitter follower circuit including the transistor T6 and the constant current source IS3 or the transistor T5 and the constant current source IS2. You.

The transistor T2 is provided in its base with a transistor T3 that receives an inverted signal of the timing signal φoe by the inverter circuit N2 at its base. Transistor T4
Are coupled to the ground potential of the circuit. Further, a load resistor R1 is provided between the commonly coupled collectors of the transistors T2 and T3 and the ground potential of the circuit. A constant current source IS1 is provided between the commonly coupled emitters of the differential transistors T2 to T4 and the power supply voltage Vee of the circuit. These differential transistors T2 to T4 are connected to the data output buffer DO
Construct B main amplifier.

The commonly coupled collectors of transistors T2 and T3 are:
Coupled to the base of transistor T1. Transistor T1
Is coupled to the ground potential of the circuit, and its emitter is coupled to the data output terminal DI of the bipolar CMOS type RAM. Thus, the transistor T1 functions as an open-emitter output transistor.

When the timing signal φoe is at a low level and the output signal of the inverter circuit N2 is at a high level, the transistor T3 is turned on. Therefore, the potential of the commonly coupled collector of transistors T2 and T3 is constant current source IS1
And is fixed at a predetermined low level determined by the operating current provided by the resistor and the resistor R1. As a result, the output transistor T1 is cut off.

On the other hand, when the timing signal φoe goes high and the output signal of the inverter circuit N2 goes low, the transistor T3 enters the cutoff state. At this time, the differential transistors T2 and T4 function as differential amplifiers, and amplify a read signal transmitted from the cascade circuit through two sets of emitter follower circuits. The output signal of the main amplifier is sent from the output transistor T1 to the outside via the data output terminal DI.

As described above, the bipolar CMOS type RAM of this embodiment
In this case, a current sensing type readout circuit including a plurality of sense amplifiers which are alternatively activated, a complementary common collector line r, and a cascade circuit is used. The cascade circuit includes a differential amplifier for inverting and amplifying the potential difference of the complementary common collector line r, and transmitting the output signal of the differential amplifier to the complementary common collector line r and via the complementary common collector line r And two sets of emitter follower circuits for converting a current signal into a voltage signal. The potential difference of the complementary common collector line r is negatively fed back through the differential amplifier and the two sets of emitter follower circuits, and as a result, the potential difference of the complementary common collector line r is compressed. For this reason, the charge / discharge operation of the complementary common collector lines rr due to the inversion of the read signal is reduced, and the signal transmission delay time of the read circuit is reduced. Thereby, the reading operation of the bipolar CMOS type RAM is further speeded up.

As shown in the present embodiment, when the present invention is applied to a semiconductor integrated circuit device such as a bipolar CMOS RAM, the following effects can be obtained. That is, (1) In a current sense type read circuit, a cascade circuit coupled to a complementary common collector line is connected to a differential amplifier for inverting and amplifying a potential difference of the complementary common collector line and a complementary output signal of the differential amplifier. By using two sets of emitter follower circuits for transmitting a current signal transmitted to the complementary common collector line and transmitted through the complementary common collector line to a voltage signal, the potential difference between the complementary common collector lines can be significantly reduced. The effect is obtained.

(2) According to the above item (1), the effect of shortening the charge / discharge operation of the complementary common collector line due to the inversion of the read signal and shortening the signal transmission delay time of the read circuit can be obtained. .

(3) According to the above items (1) and (2), it is possible to obtain an effect that the operation margin of a bipolar CMOS type RAM or the like including a current sensing type readout circuit can be increased and the degree of design freedom can be increased. .

(4) According to the above items (1) and (2), an effect is obtained that the reading operation of a bipolar CMOS type RAM or the like including a current sensing type reading circuit can be further speeded up.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in the circuit diagram of FIG. 1, a diode or the like for level clamp may be provided between the collectors of the transistors T7 and T10 constituting the emitter follower circuit of the cascade circuit and the ground potential of the circuit. A level shift transistor may be provided between the bases of the differential transistors T11, T12 and the like constituting the sense amplifiers SA0 to SA3 and the corresponding complementary common data lines CD0 ・ ▲ to CD3 ・ ▲. . Further, the selection signals s0 to s3 supplied to the MOSFETs Q17 and the like of the sense amplifiers SA0 to SA3 may include the conditions of the read operation mode. Memory array M-ARY0-M
-The static memory cells that make up ARY3 have high resistance
A P-channel type load MOSFET may be used instead of R6 and R7, or a memory cell may be formed by cross-connecting two sets of CMOS inverter circuits. In the circuit block diagram of FIG. 2, one or eight or more memory arrays may be provided. Also, as shown in FIG. 3, n + corresponding to the complementary data lines D0.
By providing one sense amplifier SA0 to SAn, the operation of selecting a complementary data line may be performed without providing a column switch.

That is, in the embodiment of FIG. 3, the memory array M-AR
Y + 1 + 1 sets of complementary data lines D0 • ▲ ▼ to Dn • ▲
N + 1 sense amplifiers SA0 to SAn are provided corresponding to ▼, and each complementary data line is coupled to the base of the differential transistor T13.T14 to T15.T16 of the corresponding sense amplifier. An N-channel MOSFET Q22 is connected between the commonly coupled emitter of each differential transistor and the power supply voltage Vee of the circuit.
To Q23. The gates of these MOSFETs are supplied with corresponding data line selection signals Y0 to Yn from a Y address decoder YDCR. The sense amplifiers SA0 to SAn are
When the corresponding data line selection signals Y0 to Yn are set to the high level, the operation is alternatively performed.

In FIG. 3, a level shift transistor is connected between the bases of the differential transistors T13, T14 to T15, T16 of the sense amplifiers SA0 to SAn and the corresponding complementary data lines D0, ▲ to Dn, ▲ ▼. It may be provided.

Further, the specific circuit configuration of the data output buffer DOB shown in FIG. 1 and the bipolar CM shown in FIG.
Various embodiments such as a combination of a block configuration of the OS-type RAM and control signals / address signals can be adopted.

In the above description, the invention made by the present inventor has been mainly applied to the bipolar / CMOS
Although the case where the present invention is applied to a type RAM has been described, the present invention is not limited to this, and may be applied to various semiconductor memory devices such as a bipolar type RAM. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor integrated circuit device provided with a current sensing type readout circuit including at least a cascade circuit.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, the cascade circuit of the readout circuit transmits the complementary output signal of the differential amplifier and the differential amplifier for inverting and amplifying the potential difference of the complementary common collector line to the complementary common collector line and is transmitted through the complementary common collector line. Of the current signal into a voltage signal, the potential difference between the complementary common collector lines is compressed, and the reading operation of a bipolar CMOS type RAM including a current sensing type reading circuit is further performed. It can speed up.

[Brief description of the drawings]

FIG. 1 shows a bipolar CMOS type RA to which the present invention is applied.
FIG. 2 is a circuit diagram showing an embodiment of a readout circuit of M. FIG. 2 is a bipolar CM including the readout circuit of FIG.
FIG. 3 is a circuit block diagram showing an embodiment of an OS type RAM, and FIG. 3 is a bipolar CMOS type RA to which the present invention is applied.
FIG. 4 is a circuit diagram showing another example of a read circuit of a conventional bipolar CMOS type RAM. M-ARY0 to M-ARY3 ... memory array, CSW0 to CSW3 ...
Column switch, SA0 to SA3, SAn ...... Sense amplifier, DOB
…… Data output buffer, MC, MC1, MC2 …… Static memory cell, Q1-Q6 …… P-channel MOSFET, Q11-Q
23 N channel MOSFET, T1 to T18 NPN type bipolar transistor, D1 diode, R1 to R11 resistor, IS1 to IS9 constant current source, N1, N2 inverter circuit. XDCR: X address decoder, YDCR0 to YDCR3: Y address decoder, XADB: X address buffer, YADB:
Y address buffer, WA0-WA3 …… Write amplifier, DIB
…… Data input buffer, ASEL …… Array selection circuit, TC
... Timing control circuit.

Continuing on the front page (72) Inventor Kazuhiro Tsuruoka 1448, Kamizuhoncho, Kodaira-shi, Tokyo Hitachi Ultra S.I.E. Engineering Co., Ltd. (72) Inventor Hiromichi Yamauchi 1448, Josuihonmachi, Kodaira-shi, Tokyo Hitachi-Ull・ S.I.Engineering Co., Ltd. (72) Inventor Hitoshi Endo 1448, Kamizuhoncho, Kodaira-shi, Tokyo Hitachi S.L.S.E.Engineering Co., Ltd. (72) Inventor Masanori Odaka 2326, Imai, Ome-shi, Tokyo (56) References JP-A-62-24493 (JP, A) JP-A-61-246993 (JP, A)

Claims (5)

(57) [Claims] A plurality of sense amplifiers including a first differential transistor for receiving a complementary input signal corresponding to each base and selectively operating according to a predetermined selection signal; A complementary common collector line in which one and the other collectors of the transistors are commonly coupled, a differential amplifier for inverting and amplifying the potential difference between the complementary common collector lines, and a complementary output signal of the differential amplifier for the complementary common collector line And a cascade circuit including two sets of emitter follower circuits for converting a current signal transmitted from the sense amplifier via the complementary common collector line to a voltage signal, and receiving a complementary output signal of the cascade circuit. And a second amplifier, wherein each base is coupled to the complementary common collector line. An active transistor, first load means respectively provided between a collector of the second differential transistor and a first power supply voltage, a commonly coupled emitter of the second differential transistor, and a second power supply A first current source circuit provided between the collector and the base of the second differential transistor, each of which has a base and an emitter respectively corresponding to a collector and a base of the second differential transistor. Transistors commonly connected, second load means respectively provided between the collector of the transistor and the first power supply voltage, and second load means provided between the emitter of the transistor and the second power supply voltage, respectively. 2. A semiconductor integrated circuit device, comprising: 2. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device is a semiconductor memory device. 3. The semiconductor memory device includes a plurality of memory arrays, a plurality of column switches provided corresponding to the memory arrays, and a complementary common data line, and the sense amplifier corresponds to the complementary common data line. 3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is provided. 4. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a bipolar CMOS.
4. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is a type RAM. 5. The semiconductor memory device includes a memory array having a plurality of complementary data lines, and the sense amplifier comprises:
5. The semiconductor integrated circuit device according to claim 2, wherein said semiconductor integrated circuit device is provided corresponding to said complementary data line.