JP2656745B2 - Wafer processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

This application is a continuation-in-part of an application entitled "Plasma Etching Tool" filed on August 20, 1993 (the corresponding Japanese patent application is Japanese Patent Application No. 6-132499). .

The present invention relates to plasma etching or reactive ion etching (RIE Reactive) of a semiconductor wafer.
Ion Etching).

[0003]

2. Description of the Related Art RIE and plasma etching techniques are widely used to etch products such as semiconductor wafers. These techniques basically involve exposing the wafer with a plasma to remove selected surface materials in selected areas, such as silicon dioxide on the semiconductor wafer surface. A polymeric material such as a photoresist is used as an etching mask to prevent unnecessary etching. If the etching is performed in a chemical or physical manner, the etching of the selected material can be very finely controlled because the etching process is limited.

[0004] Although the etching tools currently in use have been greatly improved, and allow for more precise control of gas flow, pressure, temperature, overall electric field, and plasma formation, they are still being developed. Asymmetric etching may occur during processing.

[0005] RIE or plasma etching occurs when ions are separated from the plasma and etched by the electric field present between the wafer, the pedestal and the plasma sheath, ie, the edge of the plasma cloud. Ions separated from the plasma travel along the electric field lines and collide with and react to selected exposed areas of the wafer surface. Ideally, these field lines should be perpendicular to the entire surface of the wafer. However, the edges of the wafers and pedestals in industrially used equipment, and the wafer retaining clips used in some equipment, can be distorted or changed in the direction of the electric field lines between the plasma sheath, wafer, pedestal and clip. Trigger. Wafer and pedestal distortion exacerbates electric field and plasma sheath distortion. Thus, the pedestal design may further bend the electric field near the edge of the wafer.
Such changes in the electric field affect the ions that are separated from the plasma and that are being etched, acting at an acute or obtuse angle to the surface of the wafer. The non-perpendicular ion projection angle results in asymmetrical etching of the wafer. Such asymmetric etching is particularly severe around the wafer due to the high level plasma sheath and field line distortion caused by the edge of the wafer and pedestal.

[0006] To date, many attempts have been made to solve the non-uniformity problem. Some of these attempts include using quartz spacers to separate the wafer from the cathode, curving the surface of the wafer, changing the flow of plasma gas, and using flat anodes with large areas. The wafer pedestal may change in various directions with respect to the physical position of the wafer on the cathode when it is operated. The device itself has also been modified by removing the use of large flat power distribution boards of the prior art and replacing it with a centrally located hexagonal post on which the wafer is mounted essentially vertically.

While the above solution has improved the uniformity of the overall etch, it has not achieved a symmetrical etch over the entire surface of the wafer.

As the demand for higher density semiconductor devices increases, if the surface etched holes are not at all symmetric, the surface will render the device imperfect. As disclosed in the related application above, the symmetry of the hole etched by the addition of the ring was greatly improved, but the presence of the ring caused the amount of etching gas in the area adjacent to the ring, It was found that the mixing or distribution changed. This region is referred to herein as a “gas depletion region”. In this gas-depleted region, the removal of the material being etched is reduced, so that the slope of the sidewall of the etched hole at the periphery of the wafer is much steeper than the sidewall of the etched hole at the center of the wafer.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to guarantee the following items (1) and (2) to reduce the number of wafers etched in a plasma etching apparatus.
It is to improve the uniformity and symmetry of the etching. (1) The electric field lines between the plasma sheath and the wafer are essentially perpendicular to the entire wafer surface, providing symmetric etching across the entire surface of the wafer. (2) The gas required for etching is not depleted in the ring member, that is, in the region adjacent to the ring.

Another object of the present invention is to provide a design that controls and uniformizes the distribution of process gas over the entire surface of the wafer,
All features on all areas of the wafer surface
Is to be etched symmetrically and uniformly.

[0011]

SUMMARY OF THE INVENTION In a batch etching tool, the present inventors provide a wafer support pedestal with an annulus, ie, a ring or a collar, and an additional gas flow around the periphery adjacent the annulus of the wafer. It has been found that by doing so, the slope of the sidewall of the etched opening at the periphery of the wafer can be made equal to the slope of the sidewall of the etched opening at the center of the wafer. Thus, a more uniform and symmetrically etched opening can be achieved over the entire surface of each wafer in the etching tool.

This significant improvement provides the support pedestal of each wafer with an insulating ring surrounding each pedestal, driving one or more process gases to the gas depleted region and being etched regardless of location on the wafer surface. This is achieved by providing a means to prevent the inclined sidewalls from being angled differently.

The above and other objects and features of the present invention will be more clearly described below with reference to the drawings.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS By providing each pedestal on which a wafer rides with a ring or ring or collar, the electric field distortion that occurs in non-ringed devices is essentially eliminated. The hoop essentially eliminates such distortion by creating an essentially uniform plasma sheath over the entire surface of the wafer being etched. The result is a favorable orientation of the ions that separate from the plasma and impinge on the wafer surface, providing an etch that is as symmetrical as possible. Unfortunately, under certain circumstances, the annulus causes a change or depletion of process gas in the area adjacent the annulus. The change or depletion of gas adjacent to this ring
The etching rate of the surface structure at the periphery of the wafer is also changed. The change in etch rate causes the sidewall slope of the structure etched at the periphery of the wafer to be greater than that etched at the center of the wafer.

[0015] Today, wafer products are typically etched in batches. FIG. 1 is a schematic diagram of the inside of a batch type plasma etching apparatus commonly used in the semiconductor industry. Commercially available such devices include Applied Materials' Model 8310. The apparatus is a low pressure, batch type wafer reactive ion etching tool. As shown here, the device has a pressure chamber 10, typically made of stainless steel or other suitable metal. Inside the pressure chamber 10 is a cylindrical anode electrode 12, and in the center is a hexagonal cathode 14 having a plurality of tapered pedestals 18 that are vertically aligned on each side. The wafer 16 to be etched is placed on a tapered pedestal 18. The anode and cathode are
Connected to a suitable radio frequency (RF) power supply 17. A suitable etching gas is delivered to the pressure chamber 10 through a tube 15 from a suitable source (not shown). When the pressure chamber is filled with such a gas at a suitable pressure and power is applied from the RF source 17, a plasma is formed. If necessary, gas is withdrawn from the pressure chamber 10 through a discharge tube 19 connected to a vacuum pump (not shown). As noted above, such devices are widely used and commercially available in the semiconductor industry and will not be described in detail herein with respect to their general features and methods of use.

FIGS. 2 and 3 are enlarged views of the pedestal 18 and the wafer 16 mounted thereon. FIG. 2 is a plan view of the pedestal 18 to which the wafer 16 is fixed. In current Applied Materials equipment, the wafer is secured by a plurality of S-shaped retaining clips 20. Other plasma etchers may use different retention methods. FIG. 3 is a side sectional view of the pedestal 18, the wafer 16, the plasma sheath 22, and the electric field line 24 between the sheath and the pedestal and the wafer in the Applied Materials apparatus. From FIG. 3, the pedestal 18
It can be seen that the lower portion 18a is thicker than the upper portion 18b, and the surface of the pedestal is at an angle to the central cathode 14. Pedestal 18
This sloped surface 18c is required for the handling methods currently used to place and remove wafers from the pedestal. cathode
The slope of the pedestal surface 18c relative to the 14 perpendicular surfaces further exacerbates the plasma sheath distortion and electric field refraction. The effect occurs around the entire pedestal and varies with the material of the pedestal. When the clip 20 is used to hold the wafer on the pedestal, the electric field lines may distort slightly around it. However, the strain around the clip is so small that it does not affect the symmetry of adjacent structures etched at the surface of the wafer.

As shown in FIG. 3, the edge of the pedestal causes distortion of the plasma sheath near the wafer and the edge of the pedestal, deflecting the angle of the electric field lines 24 with respect to the surface of the wafer 16 so as to be non-perpendicular. The effect of this distortion extends far from the wafer. As shown here, the angle of the electric field lines 24 becomes less and more vertical as they approach the edge of the wafer and the edge of the pedestal. These non-perpendicular field lines are shown at 24a. As the ions separated from the plasma as described above travel along the electric field lines, the electric field lines that are not perpendicular to the surface of the wafer make the etched structures, such as holes or openings, on the surface of the wafer asymmetric. On a 125 mm diameter wafer, it can affect 40% of the chips manufactured on this wafer.

This asymmetry is more clearly illustrated by FIGS. FIGS. 4 and 5 are scanning electron microscope (SEM) photographs of holes 21 etched into the surface of a semiconductor wafer using prior art equipment. Figure 4 shows hole 21
5 is a plan view of the same hole 21. FIG. This hole 21 was made in the surface of the semiconductor wafer 16 by a series of photoresist and oxidation etching processes. Hole 21
The effect of the asymmetry on the axis 23 (FIG. 4) extending perpendicularly from the center of the bottom surface is particularly pronounced on the left side 21a of the hole 21 in FIG. 5 after the second etching process. From these figures, it can be seen that the wall on the left side of the hole forms an angle greater than the wall on the right side with respect to a line drawn perpendicular to the surface of the wafer, thereby making the hole asymmetric. This asymmetry becomes more severe as the etching process is repeated.

FIG. 6 is a cross-sectional side view of the pedestal 28 with the wafer 26 mounted thereon. This pedestal 28 has a unique wheel 30. Ring 30 shown in more detail in FIG.
Is formed of an insulating or dielectric material such as ceramic or plastic.

The annulus 30 has a thicker lower edge 32 and a thinner cylindrical upper wall 34. The lower edge 32 is shown in FIG.
9 is tapered along its diameter as shown in FIG. 9 to accommodate the taper of the pedestal that the rim surrounds as shown in FIG. When the retaining clip is used, the ring 30
Further comprises a plurality of grooves 33 spaced around the periphery of the lip adjacent to the clip 20.

In designing the annulus, the height of the walls is selected so that the plasma sheath is uniform over the entire surface of the wafer. If the wall is too high, for example, about 6 cm, the plasma sheath will be similarly distorted and lose the ring effect. The wall thickness should be as small as possible, while maintaining the properties of the material used. Thus, some molding materials, such as ceramics, may require thicker walls than machined plastic due to the properties of the material. Finally, the internal diameter of the wall is
It is preferable that the distance from the edge of the wafer is not more than 20 mm and not more than 2.5 mm.

The wheels used to achieve the results described in the preferred embodiment of the present invention were formed from LEXAN ™ polycarbonate plastic sold by General Electric. The wheel 30 used in Applied Materials Model 8310 is
32 has an internal diameter of 14.70 cm, the wall 34 extending upward has an internal diameter of 14.45 cm, and a height above the pedestal surface 18 b.
It is 1.78cm and 0.508cm thick. It should be noted that the inner diameter of the wall 34 is smaller than the inner diameter of the lower rim and covers the inner surface of the lower rim 32 and covers the edge of the pedestal 28. Groove 33 is 1.70 cm high and 2.54 cm wide, with the top of the groove ending at the border of the rim and the wall. These grooves 33 allow the retaining clips 20 that are opened to insert, place and remove wafers from the surface of the pedestal to move freely. Note that when using other devices that do not use retaining clips, these openings are not required. When used with a 125 mm wafer, the annulus 30 changes the electric field such that all electric field lines 36 on the entire wafer surface are essentially perpendicular to the wafer surface as shown in FIG.

Referring again to FIGS. 6 and 7, the plasma sheath 38 modified by the presence of the annulus 30 will be further described. FIG. 7 shows, in particular, how the electric field lines 36 between the part of the plasma sheath 38 in contact with the ring 30 and the pedestal 28 are modified by the ring 30 in the region of the edge of the wafer. In FIG. 7, the plasma sheath 38 is essentially flattened over the entire wafer surface by the annulus 30, especially its upper wall 34, altering the plasma sheath 38, ie, preventing the sheath from bending downward at the end of the pedestal. You can see that Thus, the annulus 30 essentially eliminates the effects exerted on the plasma sheath 38 and the electric field lines 36 by the end of the pedestal. This modification of the effect of the edge of the pedestal causes the electric field lines 36 at the edge of the wafer to take a direction essentially perpendicular to the surface of the wafer. This occurs because the annulus 30 effectively eliminates the effects of the pedestal edge and forces the plasma sheath to remain essentially flat over the entire wafer surface. Since the diameter of the wafer is smaller than the diameter of the pedestal, there is a slight difference in height between the sheath and the surface of the pedestal, and the plasma sheath is
Slightly descend before starting to rise along. However, this drop does not significantly affect the symmetry of the structure formed on the surface of the wafer. Because, as described above, ions separated from the plasma travel along the electric field lines, any ions following the non-perpendicular electric field lines 36 are kept away from the edge of the wafer, reducing the asymmetry of the structure etched at the wafer surface. Because it does not wake up.

The holes formed in the surface of the semiconductor wafer using the symmetrical structure, ie, ring 30, are shown in FIGS. 10 and 11, which are photographs of holes 40 etched in the surface of semiconductor wafer 26. FIG. 10 is a sectional view of the hole, and FIG. 11 is a plan view of the same hole. This hole has been etched into the same region of the semiconductor wafer with exactly the same processing and steps that were performed to form the asymmetric hole 21 shown in FIGS. Compared to the axis 23 extending perpendicularly to the surface of the wafer from the center of the hole in FIGS.
The effect of the ring 30 in eliminating asymmetry is clear. Thus, it is clear that all walls are at the same angle with respect to a line drawn perpendicular to the surface of the wafer.

Although the preferred embodiment has been described with reference to etching holes in the surface of the wafer, it is also possible to etch the surface of a suitable component to leave other structures protruding or sinking from the surface of the component. It is necessary to keep in mind. The structure thus formed has walls that are at the same angle to an axis drawn perpendicular to the surface of the part.

Thus, by using an annulus 30 in a plasma or RIE etcher, the symmetrical etching of the surface of the component or the structure within the component, regardless of the location in the etcher or the location of the structure on the component surface, is achieved. can get.

This symmetry is achieved by eliminating the distortion of the plasma sheath within the annulus, whereby the annulus 30 makes the plasma sheath uniform with respect to the component surface.

Although described above with reference to a batch etcher, it will be appreciated that the wheel can also be used in a single wafer etcher or an etcher with a pedestal of a different mechanical configuration. In such other circumstances, it is preferred that the lower edge 32 of the wheel 30 be adapted to the mechanical configuration of the pedestal and the wall 34 overlap the edge of the pedestal.

FIG. 12 shows in detail how the annulus may change the process gas at various locations across the surface of the wafer 26. Because of the annulus 30, the process gas, represented by the isobar 50, moves away from the interior surface of the annulus. As a result, the process gas appears to rise above the upper edge of the loop, creating a ring region 51 on the wafer periphery 26a, where the process gas is depleted or gas depleted as described above. The processing gas at the center of the wafer is close to the wafer surface and the strength is unchanged. As a result, the central surface of the wafer 26 is etched at a rate different from the etching rate at the periphery of the wafer under the gas depleted area. This etching difference is particularly shown in FIG. In FIG. 13, line 52
Shows the etch rate across the wafer surface when the annulus 30 surrounds the pedestal 28 and the wafer 26 and the present invention is not used. From FIG. 13, the film at the center of the wafer is uniformly etched to a depth of 15,600 angstroms, but the amount of etching at the periphery of the wafer is 15,3
It can be seen that it has been reduced to 00 angstroms. This reduction in the amount of wafer edge etching causes a difference in the slope of the wall of the etched opening, as can be seen by comparing FIGS.

FIG. 14 is an actual photograph of a structure etched in the center of the wafer, for example, a hole 61, and FIG. 15 is the same type etched in a gas-depleted region 51 adjacent to the annulus 30 at the periphery of the wafer. It is a photograph of a structure, for example, a hole 62. A quick comparison of FIGS. 14 and 15 reveals the difference between the etched wall 61A of hole 61 and the slope of wall 62A of hole 62. Thus, as described above, the presence of the annulus 30 essentially eliminates the effects on the plasma sheath 38 and the electric field lines 36 induced by the edge of the pedestal, making the holes symmetrical, but at the same time, the peripheral surface of the wafer. , Thereby causing a difference in the slope of the walls of the holes 61 and 62.

The inventor has been able to overcome the effects of the gas depletion region 51 by introducing a controlled amount of the selected gas into the gas depletion region 51 at a selected rate;
It has been discovered that the ring 30 can increase the etching at the periphery of the wafer. This increase in etching
As shown by the dotted line 53 in FIG. 13, the end of the line 52 is directed upward.

In particular, the inventor has shown a central orifice (hole) 54 along the central axis of pedestal 28 and a high pressure gas supply 55 as shown in FIGS.
Modified pedestal 16 by connecting to 54.
This orifice 54 extends over the surface of the pedestal at the upper surface 28a of the pedestal and almost
Combines with a plurality of radial grooves 56, extending to a.

The gas selected must be a process gas, ideally with small molecules to maximize flow between the wafer and the pedestal. The flow rate is selected by changing the flow to optimize the configuration of the structure being etched, and is characterized by analyzing the removal of the target film at the center and edge of the wafer.

When the etching process requires a mixed gas of CHF ₃ and O ₂ to etch holes in the surface of the wafer,
The inventor has noted that when oxygen is injected through the orifice 54 and the groove 56 at a rate of 10-75 percent of the total oxygen flow used in the pressure chamber, oxygen can overcome the gas depletion in the gas depletion region 51. It has been found that it is introduced into the gas depletion zone 51 at a sufficient rate. As a result, removal at the edge of the wafer increases to the level indicated by dashed line 53 in FIG. In the specific example actually performed, the amount of etching at the periphery of the wafer was between 15,300 and 15,700
Angstrom increased. With this increase in the etching of the opening at the periphery of the wafer, the slope of the hole wall at the periphery will match the slope of the hole wall etched at the center of the wafer. This match is shown in FIG.
It can be seen by comparing 15 and 18. FIG.
Shows the same type of structure, eg, hole 63, etched at the periphery of the wafer formed when an additional gas is supplied to the depleted area as taught in the present invention. 14 and 18, it can be seen that the walls of holes 61 and 63 have the same slope.

Thus, the present invention provides an aperture having a uniform wall slope over the entire surface of the wafer, even though a loop is used to correct the symmetry of the aperture by controlling the amount of gas at the periphery of the wafer. It teaches that it can be formed.

FIG. 19 illustrates a different technique for introducing gas to the periphery of the wafer. In this figure, the pedestal 28 has a plurality of orifices 65 on the circumference inside the annulus 30 and outside the wafer 26, which orifices 65 are connected to a high pressure gas supply 66.

Although the preferred embodiment has been described with reference to the process of etching holes in the wafer surface, the present invention also etches the surface of suitable components, leaving other structures protruding or sinking from the component surfaces. Can be used for By using the present invention, the structure formed has essentially the same sloped walls.

Therefore, the present invention relates to plasma or RI
In the E etching apparatus, a symmetrical etching of the structure can be obtained by using the ring 30 and supplying an additional gas to the periphery of the wafer and a region adjacent to the ring, and each structure can be obtained by arranging the position of the component in the etcher or the like. It teaches that the same amount is etched regardless of the position of the structure on the component surface.

Although the invention has been described using oxygen as the inlet gas, it will be appreciated that the same gas mixture as the process gas or its components may be used.

It will further be appreciated that other means than the central orifices and grooves described above can be used to introduce gas into the gas depletion region 51. For example, the gas may be introduced through the wheel itself, or it may be showered over the surface of the wafer from above. Both of these other means may, of course, require different gas pressures or gas flows.

Although the present invention has been described in terms of a particularly preferred embodiment, those skilled in the art will readily appreciate from the foregoing description that changes in form and detail can be readily made without departing from the spirit and scope of the invention. It will be understood that it is possible.

In summary, the following items are disclosed regarding the configuration of the present invention. (1) On an electrode for holding a product to be etched, the electrode having a surface having a selected diameter and an edge for holding the wafer to be etched at a preselected location. An annular pedestal attached to the pedestal, a ring made of an insulating material attached to the pedestal, and a unit for introducing a component gas of the plasma to a periphery of the wafer; Has a height and width selected such that all lines of electric force are substantially perpendicular to the surface of the wafer, and the direction of ions separated from the plasma is directed by the ions to all regions of the wafer. The structure formed is controlled to be substantially symmetrical about an axis perpendicular to the surface of the wafer at the center of the structure. Etch tool. (2) The tool according to (1), wherein the means for introducing a gas to the periphery of the wafer includes an orifice connecting a source for the gas and a plurality of grooves under the wafer. (3) The ratio of the processing gas introduced into the orifice is
The tool of (2), wherein the tool is between 10 percent and 75 percent of the total flow of process gas introduced into the tool. (4) A method of altering lines of electric force impinging on a component in a plasma etching tool, the method comprising: attaching an annular pedestal having a selected diameter and an end surface to an electrode of the tool; Supporting a perimeter wafer to be etched at a preselected location on the surface of the pedestal; attaching a loop of insulating material to the pedestal; all lines of electric force between the plasma and the wafer are The structure formed in all regions of the wafer by controlling the direction of ions separated from the plasma so as to be substantially perpendicular to the surface of the wafer from the center of the structure to the surface of the wafer Substantially symmetrical with respect to an axis extending perpendicular to the tool; introducing the selected gas into the tool; Forming a Luo plasma,
Introducing a component gas of the selected gas to a periphery of the wafer adjacent the annulus. (5) The method according to (4), wherein the gas at the periphery of the wafer is introduced from one orifice between a source for the gas and a plurality of grooves under the wafer.

[0043]

As described above, according to the present invention, the uniformity and symmetry of etching of a wafer to be etched in a plasma etching apparatus can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic view of an entire batch etching apparatus.

FIG. 2 is a plan view of a wafer holding pedestal used in the apparatus of FIG. 1 with the wafer secured by clips.

FIG. 3 is a cross-sectional view of the wafer support pedestal used in the apparatus of FIG. 1 with a plasma sheath surrounding the pedestal and electric field lines extending between the sheath and the wafer.

FIG. 4 shows the structure etched on the surface of the wafer when the wafer is placed on the pedestal shown in FIGS. 2 and 3;
That is, it is an electron microscope (SEM) photograph of the cross section of the hole.

FIG. 5 is an electron microscope (SEM) photograph of a plane of the etched hole of FIG. 4;

FIG. 6 is a cross-sectional view of a wafer holding pedestal with an additional wheel used in the apparatus of FIG. 1;

FIG. 7 is a partial enlarged view of FIG. 6, showing how attaching the hoop to the pedestal changes the electric field lines and the plasma sheath.

FIG. 8 is an isometric view of a loop.

FIG. 9 is a sectional view of a hoop according to the invention showing how the hoop tapers to accommodate the pedestal of the device used.

FIG. 10 shows a structure etched on the surface of a wafer when a ring is attached to a pedestal used in the etching apparatus of FIG. 1 as shown in FIGS. It is a microscope (SEM) photograph.

FIG. 11 is an electron microscope (SEM) photograph of the plane of the etched hole of FIG.

FIG. 12 is a cross-sectional view of the wafer support pedestal used in the apparatus of FIG. 1 modified by the addition of a hoop, showing a change in process gas distribution and the creation of a hue-induced gas depletion zone.

FIG. 13 is a graph showing how the etching of the surface material varies with the ring and the resulting gas depleted region.

FIG. 14 is an electron microscope (SEM) of a cross-section of the etched structure or hole in the center of the wafer surface when the wafer is placed on the looped pedestal shown in FIG.
It is a photograph.

FIG. 15 is an electron microscope (SEM) of the cross-section of the etched structure or hole at the periphery of the wafer surface when the wafer is placed on the looped pedestal shown in FIG.
It is a photograph.

16 is a plan view of a pedestal modified to introduce gas into a gas depleted region at the edge of the wafer shown in FIG.

FIG. 17 is a sectional view of the pedestal of FIG. 16;

FIG. 18 shows a structure or hole etched at the periphery of the wafer surface when the wafer is placed on the looped pedestal shown in FIG. 12 and provided with an additional gas as taught by the present invention. It is an electron microscope (SEM) photograph of a cross section.

FIG. 19 is a view showing another method of introducing gas into the gas depletion region shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Pressure chamber 12 Anode 14 Cathode 16, 26 Wafer 17 High-frequency power supply 18, 28 Pedestal 20 Holding clip 22, 38 Plasma sheath 24, 36 Electric field line 30 Wheel 32 Edge 33 Groove 34 Wall 50 Isobar 51 Gas depleted area 54 Orifice 55, 66 High pressure gas supply source 56, 65 Groove 61, 62, 63 hole

Continued on the front page (72) Inventor Din Dunn United States 05452 Aspen Drive, Essex Junction, Vermont 26 (72) Inventor James George Michael United States 05401 Pine Street 500 Burlington, Vermont 500 Apartment 3 Eff (72) Inventor Timothy Edward Neari, Margaret Street 34, Essex Junction, Vermont, United States 05452 United States 05452 Inventor Paul William Pastel, Essex Junction, Essex Junction, Vermont United States 05452, United States 18 (72) Inventor Sylvia Rose Labelle Tolley United States 05403 Spare Street, South Burlington, Vermont 112 (72) Inventor Arthur Clifford Winslow Amelie Clover Drive, Essex Junction, Vert., United States of America, 05452 48 (56) references A) JP-A-1-115122 (JP, A) JP-A-59-89534 (JP, U) JP-A-3-13733 (JP, U) JP-A-58-77043 (JP, U)

Claims (3)

(57) [Claims] 1. A wafer processing method for processing a wafer with a plasma etching tool, comprising: mounting a circular pedestal on an electrode; mounting the wafer on the pedestal; and controlling an electric field from plasma to the wafer. The direction is perpendicular to the surface of the wafer, and each of the openings formed across the surface of the wafer by ions from the plasma is symmetrically about a central axis perpendicular to the surface of the wafer. A ring member of an electrically insulating material is mounted on the pedestal so as to surround the wafer to be formed, and a processing gas for forming the opening is introduced into the plasma etching tool to generate the plasma. In order to compensate for the depletion of the processing gas in a peripheral portion of the surface of the wafer adjacent to the ring member, an upper portion is formed from a gas supply source. Wafer processing method comprising supplying the processing gas into the periphery through the supply passage provided in the pedestal. 2. The pedestal is provided with an orifice provided at the center of the pedestal and a groove extending radially in communication with the orifice, and the gas supply source is connected to the orifice. The wafer processing method according to claim 1, wherein: 3. The pedestal, wherein a plurality of through orifices are provided at locations adjacent to a peripheral portion of the wafer, and the processing gas is supplied from the gas supply source to the through orifices. 2. The wafer processing method according to 1.