JP2656765B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus capable of processing instructions at high speed.

[0002]

2. Description of the Related Art As shown in FIG. 1, a conventional data processing apparatus includes an interface circuit 7 for exchanging data with a storage device 5, an instruction execution unit 3 for controlling an instruction to be executed, and an instruction execution unit. And an instruction execution unit 4. When the instruction read from the storage device 5 is transferred to the instruction control unit 3 via the line 73, the interface circuit 7, and the line 11, the instruction control unit 3 analyzes the transferred instruction and outputs the result to the instruction control unit 3. Line 1 to execution unit 4
5 via The instruction execution unit 4 generates various control signals as a result of the analysis, and opens and closes each gate in the instruction execution unit 4 with the control signals to perform processing such as calculation, storage, and shift. Line 1 depending on the command
4. An address is designated via the line 74, and data is read from the main memory 5 via the lines 13 and 74, and the operation result is written into the main memory 5. The instruction control unit 3 sends the read address of the next instruction to the line 12, the interface circuit 7,
Instruct storage device 5 via line 74. The data processing device 1 executes the program stored in the storage device 5 by repeating these series of operations.

[0003] The data processing apparatus comprises an instruction control unit 3
And the instruction execution unit 4 can operate in parallel, and pipeline control is performed.

The conventional device has a cache memory 71 for reading data from the main memory 5 at a high speed. The cache memory 71 is searched by the address on the line 73, and when a hit is found, the data of the corresponding entry is read, and the access to the main memory 5 is not performed. Therefore, in the case of a hit, the access time to the main memory can be omitted, and high-speed data reading can be performed.

[0005] As an example of such a device, for example, Iwanami Koza Microelectronics "Hardware of Microcomputer", November 144, 1984, Nos. 144-14.
There is a data processing device stored on page 8.

However, in such a data processing device having a cache memory, it is necessary to invalidate the cache, that is, to prohibit access to the contents of the cache in various cases. For example, when the content of the instruction or operand data stored in the main memory is updated to a new content, or the correspondence between the logical address stored in the instruction cache memory or the operand cache memory and the physical address of the main memory is not guaranteed. Such as when the contents of the instruction or operand data stored in the instruction cache memory or operand cache memory do not match the contents of the instruction or operand data stored in the main memory, Is required.

The invalidation of the cache is described in Japanese Patent Application Laid-Open No. 60-500187 and Japanese Patent Application No. 60-68210.
It is also disclosed in (JP-A-60-225262).

In the current system, the address created in the chip may be different from the address actually assigned to an external device, and the address created in the data processing device may be referred to as a logical address or an external address . The address actually given to the device may be called a physical address.
In general, conversion between a logical address and a physical address is performed by providing special hardware called an address conversion mechanism in an output unit in a chip of a data processing device or outside. For example, it is shown on page 145 of the above-mentioned book.

However, when a system is provided in which an address conversion mechanism is provided outside the data processing device which refers to the logical address in the chip, the address of the main memory referred to by the physical address and the chip referred to by the logical address are used. The address of the cache memory inside may be different.

In particular, when the address space on the main memory is switched to another address space, the correspondence between the address of the information held in the cache memory in the data processor 1 and the actual address of the main memory is changed. Cannot be guaranteed.

Therefore, when the address translation mechanism is provided in the system, it is necessary to assert the purge signal to inform the data processing device that the address space of the address translation mechanism has been switched.

As regards the invalidation of the cache, Japanese Patent Application Laid-Open No. S60-500187 does not consider the above-mentioned problems, and therefore uses only an instruction for invalidating a cache line which is a part of the cache. In Japanese Patent Application No. 60-68210 (JP-A-60-225262),
It only discloses that it is invalidated when a direct memory access (DMA) write operation is performed (note: there is no description of the invalidation instruction).

[0013]

Therefore, an instruction address generator (32) for generating an instruction address (l31) and a plurality of entries for storing a plurality of instruction addresses and a plurality of instructions corresponding to the plurality of instruction addresses are provided. Instruction cache memory
(31) and the instruction generated from the instruction address generator (32).
Instruction cache memory (31) according to the instruction address
Or the instruction read from another memory and the decoding result
And the output of the instruction decoder
An operand address generator (45) for generating an operand address according to the above , an operand cache memory (21) having a plurality of entries for storing a plurality of operand addresses and a plurality of operand data corresponding to the plurality of operand addresses, Generated by the instruction address generator
A data processing apparatus comprising an address conversion circuit for converting a logical address into a physical address, the instruction de
According to the output of the coder, invalidation is performed by designating any of a plurality of entries of the instruction cache memory or a plurality of entries of the operand cache memory.

In other words, the data processor issues a purge command in advance to invalidate the internal cache memory (associative memory).

[0015]

The instruction cache memory can be invalidated in response to the switching of the address space of the address translation mechanism, so that the address of the information held in the cache memory in the data processing device and the actual main memory can be saved. Correspondence with addresses can be guaranteed.

[0016] Other objects and features of the present invention will be apparent from the following examples.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the drawings.

In the following description, first, instructions used in the data processing device of the present embodiment will be described, then the device configuration will be described, and finally the operation will be described.

1) Instruction Basic instruction format FIG. 2 shows an instruction format of this embodiment.

An instruction is an operation type (bits 15 to 1).
2) An operation word (bits 11 to 0) for designating an addressing mode and the like, and an extension for giving data for address calculation, and are 32 bits in length.

Depending on the type of addressing mode to be specified, there may be no extension.

Bits 11 to 9 of the operation word indicate the number of a data register that holds data used as one operand of an operation. The other operand is specified by bits 5-0 of the operation word. That is, bits 2 to 0 indicate the number of the register to be referred to for acquiring this operand, and bits 5 and 3 indicate the addressing mode.

This embodiment has eight data registers and eight address registers as described later.

FIG. 2B shows the correspondence between the bit patterns of bits 5 and 3 and the addressing mode. In the figure, a “data register” mode and an “address register” mode are modes in which the contents of a designated data register and address register are used as operands as they are. "Address register indirect"
The mode is a mode in which the content of the specified address register is used as a memory address of an operand.
The “post-increment” mode and the “pre-decrement” mode are basically the same as the address register indirect mode, except that the contents of the address register are respectively +1 and −1 immediately before and immediately before the store or fetch of the operand, respectively. Is different. Therefore, in this mode, operand data stored in a series of addresses is read out one after another and operated.

The "address register with displacement indirect" mode is a mode in which the value obtained by adding the contents of the extension to the contents of the designated address register is used as the memory address of the operand. The mode is a mode in which a value obtained by adding the content of the extension to the address of the instruction (contents of the program counter) is used as the memory address of the operand. The “absolute address” mode is a mode in which the content of the extension is used as it is as the memory address of the operand.

Stack Instructions Among Basic Instructions Since a current program is written in a high-level language, it has a stack as its data structure. In particular, when using a subroutine, the variables used in the main routine,
The variables used in the subroutine need to be stored on the stack as separate groups. This group is called a frame.

The stack includes a part of the main memory and a stack pointer. The stack pointer is a register for storing addresses for storing variables in the main memory one after another from lower addresses.

When calling a subroutine, the value of the stack pointer is moved to the frame pointer. The frame pointer is a register for storing the highest address of one frame. In this embodiment, one of the eight address registers is used as a stack pointer, and the other is used as a frame pointer.

To access the stack, a frame pointer or a stack pointer is designated by bits 2 to 0 of the instruction, and the addressing mode of the instruction 5 to 3 bits is "address register indirect", "post increment", "pre-decrement". Or "indirect address register with displacement". These access modes to the stack are collectively called a stack access mode, and these instructions are called stack instructions.

As described above, in the present apparatus, the stack pointer is determined in advance for one register, so that a program that does not designate the register as the stack pointer may have a reduced performance.

Control Instruction The data processing apparatus of the present embodiment further has a control instruction having a format different from that of the general instruction.

This embodiment is called a purge (PURGE) instruction, which is issued exclusively by the data processing apparatus itself. However, it may be read from the main memory together with the basic instruction described above. The function of this instruction is to invalidate the associative memories 21, 31 or 36, 37, 38 incorporated in the data processing device.

The reason why this instruction exists is as follows.

The data processing device 1 is contained in one chip. This is to access the outside with the address created in this chip. However, in the current system, the address created in the chip may differ from the address actually assigned to an external device, and the address created in the data processing device is logically added to the address.
Less, sometimes an address actually given to the external device physically A <br/> that address. In general, conversion between a logical address and a physical address is performed by providing special hardware called an address conversion mechanism in an output unit in a chip of a data processing device or outside. For example, op.
It is shown on the page.

Since the data processing apparatus of this embodiment refers only to the logical address in the chip as described later, when a system having an external address conversion mechanism is configured, the data is referred to by the physical address. The address of the memory and the address of the associative memory in the chip referenced by the logical address may be different.

In particular, when the address space on the main memory is switched to another address space, the correspondence between the address of the information held in the associative memory in the data processing device 1 and the actual address of the main memory is changed. Cannot be guaranteed.

This inconsistency can be solved by the data processor issuing a purge command in advance to invalidate the internal associative memory.

Therefore, when the address translation mechanism is provided in the system, it is necessary to assert the purge signal to inform the data processing device that the address space of the address translation mechanism has been switched.

The present data processing apparatus is configured to issue a purge command based on a purge signal and a purge command from an address conversion mechanism, as described later in the section of the purge control circuit.

The above is the reason why the purge command is provided.

Next, the format of the purge command will be described with reference to FIG.

In the purge instruction, the memory whose contents are to be invalidated is specified by a purge code (PURGE COD).
According to E). The correspondence is shown in FIG. When bits 7 and 6 of the purge code are "00", they are not invalidated.
When the purge code is "01000000", the associative memory of the data system is invalidated. The data-based associative memory corresponds to the associative memory 21 described later.

When the purge code is "10000000", the instruction-based associative memory is invalidated. Instruction-type associative memories include associative memories 31, 36, and 37 described later.
And 38 apply.

When the purge code is "11111111", all internal associative memories are invalidated.

2) Next, the configuration of the present apparatus will be described in detail.

In FIG. 4, reference numeral 1 denotes a data processing device, an interface unit 2 for exchanging data with the main memory 5, an instruction control unit 3 for analyzing data from the interface unit, and an analysis from the instruction control unit. It comprises an instruction execution unit for executing an instruction.

From the main memory 5, data of 4 bytes (32 bits) can be read by one access. Instruction execution unit 4
Reads out data necessary for instruction execution from the main memory via the interface unit 2.

Instruction control unit 3 and instruction execution unit 4
Can be operated in parallel and pipeline control is performed.

Hereinafter, each circuit will be described.

The instruction control unit 3 receives the prefetch address update signal via the line 134 and inputs the branch destination address to the line l3.
3, a prefetch address and a fetch request are output to a line l31, and an address of an instruction being executed by the instruction execution unit 4 is output to a line l32.

FIG. 5 shows the details of the address generation circuit 32.

Reference numeral 323 denotes a selection circuit, which is normally a register 32.
1 is selected, and when a branch address is provided via line l332, the branch address is selected.

An adder 325 adds the number given from the constant generation circuit 324 to the instruction address from the selection circuit 323. The number generated by the constant generation circuit 324 corresponds to the length of the instruction to be read.

The register 321 latches the output of the adder 325 according to the signal from the line l342. Therefore, each time a signal is received from the line l34, the register 321 is updated, and the prefetch address is output to the line l312 in the line l31. The update signal of the line l34 is output as a fetch request from the line l311 of the line l31.

326 is a selection circuit, which is usually an adder 329.
Is selected, and when a branch address is given via line l332, the branch address is selected. Register 327 latches the instruction address from selection circuit 323, and outputs the instruction address to line l32.

The adder 329 adds the number given from the constant generation circuit 328 to the instruction address on the line l32.
The number generated by the constant generation circuit 328 corresponds to the length of the instruction to be executed.

The associative memory 31 is a memory for storing an instruction address and an instruction corresponding to the instruction address in the same entry.

FIG. 6 shows the structure of the associative memory 31. A total of 64 entries are formed, each entry being a search field 311, a valid bit 312 and a data field 3.
13.

The search field is a field for storing an instruction address given via the line 1312. The valid bit is a bit indicating whether the data stored in the data field 313 is valid. Data field 31
Reference numeral 3 denotes a field for storing an instruction given via a line 135 and has a length of 4 bytes (32 bits).

The search to the associative memory 31 is performed by the instruction address given via the line l31. If the instruction address is present and the valid bit is set, the instruction stored in the data field of the entry is
52. Also, a fetch end signal is output to a line l351. When a hit occurs, the signal on the line 126 is turned on, and the access to the main memory 5 is prohibited by the selection circuit 22.

The associative memory 31 is updated when there is no entry storing the instruction address from the line l31 and the valid bit is reset. Main memory 5
The instruction read out when the fetch end signal of line l351 is turned on is input via line l35 and written into the oldest rewritten entry along with the instruction address from line l31. The valid bit 312 of the newly rewritten entry is set.

The associative memory 31 is invalidated by executing the purge command. When the purge command is executed, the valid bit 312 is reset for all entries by a signal line (not shown) from the command execution unit 4.

The first-in / first-out memory 34 is a memory for storing a plurality of instructions given via the line l352 when the fetch end signal of the line l351 is turned on, and is the oldest written instruction. Is the memory that reads out the fastest.

When the memory 34 has a vacancy and the fetch end signal of the line l351 is turned off, the control circuit 33 sends the address generation circuit 32 via the line l34 to read the next instruction. This is a circuit for sending a prefetch address update signal.

The decoder 35 analyzes the instruction from the memory 34, converts it into the instruction address of the microprogram, and outputs it to the line 136.

The associative memories 36, 37 and 38 are buffers for suppressing disturbances in the pipeline, and store a branch source address, a branch destination instruction and a decoding result in the same entry.

The structure of the associative memories 36, 37 and 38 is shown in FIG.
Shown in The whole is composed of four entries, and each entry is composed of a search field 361, a valid bit 362 and data fields 363, 37, 38.

The search field 361 is a field for storing a branch source address given via the line l32. The valid bit field 362 is the data field 3
This bit indicates whether the data stored in 63, 37, and 38 is valid. A part 363 of the data field is a field for storing a branch destination next instruction given via the line l38. Another part 38 of the data field is a field for storing the branch target instruction itself given via the line l38. The other part 37 of the data field is
This is a field for storing a microinstruction address given via a line l36. Incidentally, in the overall configuration diagram of FIG.
The associative memory 36 includes an address generation circuit 32 and a decoder 35.
The associative memory 37 is provided between the decoder 35 and the instruction execution unit 4. The reason is that the positions of the sources of various information stored in the associative memory 36 and the positions of the sources of information stored in the associative memory 37 are different. Thus, the associative memories 36, 37
, The distance between the information source and the associative memory can be shortened, and the area occupied by the chips between them can be reduced. The associative memories 36 and 37 are connected via a line 137, and the address of the entry selected in the associative memory 36 is stored in the associative memories 37 and 38.
Via the line l37, and the same entry is selected.

The search to the associative memories 36, 37, 38
This is performed at the branch source address given via the line l32.
If the branch source address exists and the valid bit 362 is set, the data field 36
The information stored in the lines 3, 37, and 38 is a line 135 and a line l, respectively.
39 and line 140.

The associative memories 36, 37 and 38 are updated when there is no entry storing the branch source address from the line l32 and the valid bit 362 is reset. At this time, the oldest rewritten entry is written together with the branch source address, the branch destination address, and the branch destination next instruction. The valid bit 362 of the newly rewritten entry is set.

The associative memories 36, 37 and 37 are invalidated when the barge instruction is executed. When the barge instruction is executed, the valid bit 362 is reset for all entries by a signal line (not shown) from the instruction execution unit 4.

When receiving the branch success signal provided via the line l45, the selection circuit 47 selects the line l39. When the branch failure signal is received, the line 136 is selected.

The selection circuit 46 selects the line l38 when receiving the branch success signal given via the line l45. When the branch failure signal is received, the line 140 is selected.

Register 38 latches the microinstruction address from decoder 37 in response to a next instruction request signal provided via line 141. Then, the latched microinstruction address is sent to the instruction execution unit. However, the barge command signal and the line l41 are transmitted via the line l62.
When the next instruction request signal is given, the purge instruction is latched via the line 163 instead of the micro instruction address from the decoder 37.

Register 40 latches the signal from selection circuit 46 when receiving the next command request signal via line 141.

The instruction execution unit 4 ROM 41 sequentially fetches, as an address, each microinstruction of a microinstruction sequence arranged on a time axis given via a line 140 and sequentially reads out control information stored at a corresponding address. , Line 142.

The processing circuit 45 performs an operation based on the control information on the line 142. An address for obtaining operand data from main memory is output via line 133, and the read operand data is input via line 134. The command itself is input via a line 144. Upon completion of the instruction execution, a next instruction request signal is output to line l41.
If the branch was successful when the branch instruction was executed, the line l
A branch success signal is output to 45, and a branch failure signal is output if the branch has failed.

FIG. 8 is a diagram showing the structure of the processing circuit 45. Lines l46, l47 and l48 are internal data buses. The register group 452 includes eight data registers, eight
It consists of a book address register. One or two registers of the register group 452 are designated by a line l422, and data is read from the buses l46 and l47 or data is read from the bus l48.

The address pointer includes a stack pointer and a frame pointer among eight address registers. The contents of the stack pointer are decremented each time it is used for storing data in the main memory, and incremented by one each time it is used for reading.

An arithmetic circuit 453 includes buses 146 and l46.
The signal on the line 47 is subjected to addition, division and the like based on the instruction from the line l423, and outputs the operation result to the internal data bus l48. Further, the arithmetic circuit 453 outputs the next instruction request signal to 141 after all the control information for one instruction is input from the line 142 and after the operation is completed.

When the branch instruction is executed, the condition code C. With reference to C, a branch success signal is output to a line l45 if the condition defined by the branch instruction is satisfied, and if not, a branch failure signal is output to a line l45.

When the purge command is executed, first, a purge clear signal is output to a line 149, and the effective bit of the associative memory indicated by the purge code is reset via a signal line (not shown).

A data designating circuit 454 designates an operand size (1 byte, 2 bytes, 4 bytes specified by the instruction) received via the line l424 when the post-increment mode or the pre-decrement mode is executed. ), The lower 2 bits of the address on line l33 are decoded, and among the 32-bit data on line l43, data required as an operand and having a length of the operand size is interfaced via line l50. 451.

The interface 451 transmits data from the line l432 to the internal data bus l4 when the fetch end signal of the line l431 is turned on based on the control information on the line l421.
7, 148 to turn off the fetch request signal on line l431. The data from the internal data buses l47 and l48 are output to the line l432, and the fetch request signal is output to the line l43.
Output to 1. When the bit position and length of the data to be read are designated by the line 150, the data is cut out based on the designated bit position and length.

The associative memory 21 includes an operand buffer 24 for storing operand data and a line buffer 25 for storing byte data.

FIG. 9 shows the configuration of the operand buffer 24. Each entry is composed of a search field 241, a valid bit 242, and a data field 243.

The search field is a field for storing the address of the operand data given via the line 133. The valid bit 242 is a bit indicating whether the operand data stored in the data field is valid. The data field 243 is a field for storing the operand data given via the line l21.

The update / search of the operand buffer 24
The following two types of control are performed based on the instruction to be executed by the instruction execution unit 4.

(A) In the stack access mode, when the contents of the address register specified by the instruction are output to the line l332 as the address of the operand data, the operand buffer 24 is searched by the operand data address. When the operand data address exists and the valid bit 242 is set, the operand data stored in the data field of the entry is output to the line l432. At this time, line l43
1 is turned on. When a hit occurs, access to the main memory 5 is prohibited by the selection circuit 22 via the line 125. When a miss occurs as a result of the search, the operand data read from the main memory 5 is input via the line l21, and is written into the oldest rewritten entry along with the operand address from the line l33. The valid bit 242 of the newly rewritten entry is set.

(B) When an instruction execution result is obtained, the execution result is output on a line l43, and an address in the main memory 5 where the execution result is to be stored is output on a line l332, the operand buffer 24 Search by address. If the address exists and the valid bit 242 is set, the data of the data field of the entry is rewritten to the execution result on the line l332. Valid bit 242 is set. Even if you hit at this time,
Nothing is output on line 125. Therefore, the selection circuit 2
2 is not prohibited from accessing the main memory 5. If the search results in a miss, the data in the operand buffer is not rewritten.

In cases other than the above (a) and (b), the search and rewrite of the operand buffer are not performed.

The case (a) relates to updating of the stack and reading of data from the stack. In case (a), the operand buffer is updated and rewritten, so that the operand buffer can be said to be an internal memory for storing stack data.

In the case of (b), the data may be rewritten by directly specifying the address of the stack depending on the instruction. This is a measure to cope with this.

The operand buffer 24 is invalidated by a purge signal. When the purge signal is input,
All the valid bits 242 are reset.

In the post-increment mode and the pre-decrement mode, the line buffer 25 holds 4 bytes of a continuous address read from the main memory 5 at a time when reading byte data of a length specified by the operand size. This is a memory for accelerating access to successive operand addresses in subsequent instructions.

FIG. 10 shows the configuration of the line buffer 25. The line buffer 25 has 6 address registers, excluding the stack pointer and the frame pointer, out of the 8 address registers.
It has an entry corresponding to a book registry on a one-to-one basis. Therefore, it consists of a total of six entries.

Each entry has search fields 251 and 4
It consists of two valid bits 252 to 255 and four data fields 256 to 259. Valid bit 25
2 to 255 correspond to the data fields 256 to 259, respectively, and indicate whether the data of the corresponding data field is valid or not. In the four data fields of one entry, 4-byte data of a continuous address read from the main memory 5 at a time is stored, respectively.

[0098] of the line buffer 25 search of the address indirect mode, carried out at the time of the post-increment and pre-decrement mode.

The post-increment and pre-decrement modes are modes in which the value of the address register is incremented or decremented by one, and data stored at consecutive addresses are read out one after another.

In this mode, when the first data is read out, it is normal that the corresponding entry does not exist even if the line buffer is searched. Therefore, the line l
The address is sent out via 33. At this time, the main memory 5
Is read out at a time, and written to the entry corresponding to the address register specified by the instruction in this mode via the line l21. At the same time, the data is output from the selection circuit 22 to the line 143.

At this time, although 32-bit data is sent to the line 143, the data required as an operand is data of the number of bytes specified by the operand size. The extraction of the data is performed by the data designating circuit 454 and the interface 451 described above.

When the processing of the first data is completed, the contents of the address register designated by the instruction in this mode increases or decreases by 1, and the next data is read. At this time, the address output to the line l33 is an address that is consecutive to the previously output address. Therefore, there is an extremely high probability that the corresponding address exists in the data previously stored in the line buffer. If the search results in a hit, the data is not read out to the main memory 5 but the 4-byte data of the corresponding entry is output to the line l43. Also, output is output to line 125,
The access to the main memory 5 of the selection circuit 22 is prohibited.

In the instruction execution unit 4, when an instruction execution result is obtained, the execution result is output on a line l43, and an address on the main memory 5 where the execution result is to be stored is output on a line l33, The line buffer 25 is searched by the address. If the address exists and the valid bit is set, the data in the data field of the entry is rewritten to the execution result on line l33. The valid bit is set. Even if a hit occurs at this time, nothing is output to the line 125. Therefore, access to the main memory 5 of the selection circuit 22 is not prohibited. If the search results in a mishit, the line buffer 2
5 is not rewritten. This operation is also a process for keeping the contents of the line buffer coincident with the contents of the main memory 5 as in the case of the operand buffer.

As described above, by using the line buffer 25, in the post-increment / pre-decrement mode, it is sufficient to access the main memory once every four bytes on average, and high-speed reading is possible. Becomes In particular, when the operand size is designated as 1 byte, the main memory needs to be accessed only once during the processing of four operand data.

The interface unit 2 selection circuit 22 sends one of the instruction address given via the line l31 and the operand data address given via the line l33 to the main memory 5 via the line l23. It is.

FIG. 11 shows a configuration diagram of the selection circuit. Line l3
11 is a read request signal, and line l312 is an address signal, constituting line l31. A line l331 is a fetch request signal, and a line l332 is a line l33 with an address signal. AND
The circuit 222 obtains the logical product of the signals on the lines l311 and l26, and outputs a signal for inhibiting the access from the instruction control circuit 3 to the main memory 5 when the associative memory 31 hits. The AND circuit 226 calculates the logical product of the signals on the lines l331 and l125, and outputs a signal for inhibiting the instruction execution unit 4 from accessing the main memory 5 when the associative memory 21 hits.

The AND circuits 223 and 227 are circuits for giving priority to an access request from the instruction execution unit 4. One of flip-flops 224 and 228 is set by AND circuits 223 and 227. The selector 221 has a flip-flop 224
Alternatively, it is a circuit that outputs one address signal selected by 228 to a line l232.

The OR circuit 230 is connected to the flip-flop 22
This circuit calculates the logical sum of the outputs of 4,228 and outputs a fetch request signal to a line l231. Lines l231 and l
232 constitutes a line 123.

Data from main memory 5 is obtained via line 124. A line l241 is a fetch end (readout end) signal, which indicates that data is ready. Line l
The data itself is input on 242.

AND circuits 225 and 229 are connected to line l2
It is determined whether the instruction control unit 3 or the instruction execution unit 4 has issued the fetch request to the line 31, and the data is ready by the fetch end signal to the line (l351 or l211) that issued the request. Let them know. The instruction control unit 3 and the instruction execution unit 4 each have a line l3.
By looking at l351 in line 5 or l211 in line l21, it is determined whether or not there is a response to the fetch request, and the fetch request is turned off.

Purge control circuit 6 The purge control circuit 6 outputs a purge command signal to a line 162 when a purge signal is input from a line 161, and outputs a purge command signal to a line 162.
3 to output a purge command.

FIG. 12 shows a configuration diagram of the purge control circuit 6. The inputs of the purge control circuit 6, lines l61 and l64 are
As is clear from FIG.
The purge signal is input to l61.
The purge command stored in the register 66 is input to l64.
Is forced. Further, the input of the purge control circuit 6, the line
And 149 are processes in the instruction execution unit 4 shown in FIG.
Signal line input from the logic circuit 45,
A command request signal is input, and a purge clear signal is provided at l49.
Is entered.

When a purge signal is input from line l61, A
The D terminal of the flip-flop 65 is set high through the ND circuit 64. When the next command request signal is input via the line l41, the input of the D terminal is latched at that timing, and the purge command signal on the line l62 is turned on. Therefore, the contents of the register 66 in which the purge command is stored in advance via the line l64 are stored in the register 38 via the line l63.
1 (FIG. 4) . At this time, the flip-flop 62 is also set. When a purge command is executed by the command execution unit 4, first, a purge clear signal is output from a line l4.
9 is output. Thereby, the flip-flop 62 is reset. The D input of the flip-flop 65 is set to Low via the delay circuit 63 and the AND circuit 64. When the execution of the purge command is completed, the next command request signal on line l41 turns on. As a result, the flip-flop 62 is set and the flip-flop 65 is reset. The output of the flip-flop 62 is input to the delay circuit 63. During this time, the register 381 latches the instruction decode result from the selection circuit 47. Thereafter, the output from the delay circuit 63 becomes high. At this time, if the line l61 is still outputting the purge signal, the flip-flop 6
The D input of 5 is high. Therefore, when the next command request signal is input, a purge command signal is output again on line l62.

An address conversion circuit (not shown) can be connected to lines l61 and l63.

As described above, the address conversion circuit is used for a system in which an address used in the data processing device is different from an address given to a device outside the data processing device.

In the present embodiment, the purge instruction can be alternately latched in the register 381. This is because the data processor executes the normal instruction one step at a time and checks the program. In order to carry out.

3) Description of Operation Next, the operation of the data processing apparatus will be described.

FIG. 13 shows an example of an instruction sequence executed in the data processing apparatus.

The instructions are stored at consecutive addresses in the main memory from No. 1 to No. 11.

Instructions No. 1 and No. 2 are instructions for storing the data at the address indicated by the stack pointer in the data register specified by each instruction.

The instruction No. 3 is an instruction for adding the contents of the registers storing the data in the instructions No. 1 and No. 2, respectively, and storing the result in one of the data registers.

Instruction No. 4 is an instruction for storing the contents of the data register specified by the instruction at the address specified by the address register specified by the instruction.

The instruction No. 5 is an instruction for jumping to the instruction at the address specified by the address register specified by the instruction. In the case of this example, it is assumed that the processing jumps to the instruction No. 10.

The instruction No. 10 is an instruction for adding the contents of two data registers specified by the instruction.

FIG. 14A shows a time chart when the above-described instruction sequence is executed.

The cycle T ₁ address generation circuit 32 outputs the address of the instruction No. 1 to the line l31. The associative memory 31 is searched at the address. If no hit is found, the data is read to the main memory 5. Data read from the main memory 5 is stored in the associative memory 31.
Is also stored in the memory 34.

Since there is free space in the cycle T ₂ memory 34, the address generation circuit 32 outputs the address of the instruction No. 2. The associative memory 31
Similar to the instruction No. 1, the address is searched for, and if no hit is found, the data from the main memory 5 is written. The read data is stored in the memory 34.

The decoder 35 receives the instruction N from the memory 34
o.1 is analyzed, and the analysis result is stored in the register 38.

The micro instruction sequence of the instruction No. 1 stored in the register 38 is started to be executed in the instruction execution unit 4.

At the time of execution, the address of the operand data to be stored in the data register is output to line 133. Since this instruction is a stack instruction, there is a high possibility that the corresponding entry exists in associative memory 24. . Therefore, the conflict between the read request of the instruction No. 2 from the instruction control unit 3 and the read request of the operand data from the instruction execution unit 4 is reduced.

On the other hand, when the instruction No. 2 exists in the associative memory 31, regardless of whether the associative memory 24 has operand data or not, the instruction control unit 3 and the instruction execution unit 4 Read requests to the main memory 5 do not conflict.

The cycle T ₃ instruction No. 3 is read from the main memory 5 in the same manner as the instructions No. 1 and No. 2 and stored in the memory 34.

In the decoder 35, the instruction No. 2 is analyzed.

In the instruction execution unit 4, the execution of the instruction No. 1 is completed, and the execution of the instruction No. 2 is started.

The instruction No. 2 is a stack instruction similar to the instruction No. 1, and the associative memory 24 is searched. When there is a mishit, the operand data is read to the main memory 5. The conflict between the instruction control unit 3 and the instruction execution unit 4 in this case is the same as that of the instruction No. 1.

Cycle T ₄ Instruction No. 4 is read from the main memory 5 and stored in the memory 34 in the same manner as the instruction No. 1 and the like.

In the decoder 35, the instruction No. 3 is analyzed.

In the instruction execution unit 4, the execution of the instruction No. 2 is completed, and the execution of the instruction No. 3 is started.

The instruction No. 3 is an instruction which performs an operation using the data register in the instruction execution unit 4, and therefore does not go to read the operand data to the main memory 5.

Cycle T ₅ Instruction No. 5 is read from main memory 5 and stored in memory 34 in the same manner as Instruction No. 1.

At the decoder 35, the instruction No. 4 is analyzed.

In the instruction execution unit 4, the execution of the instruction No. 3 is completed, and the execution of the instruction No. 4 is started.

Instruction No. 4 is an instruction for writing the data of the data register to the main memory. The address to which data is to be written is output to the line l33. Operand buffer 24
Checks whether or not this address is for rewriting the contents of the stack, and if so, rewrites the contents of the operand buffer to the data on line l43. Line l
The data on 43 is sent to the main memory 5.

Cycle T ₆ Instruction No. 6 is read from main memory 5 and stored in memory 34 in the same manner as Instruction No. 1.

In the decoder 35, the instruction No. 5 is analyzed.

On the other hand, the address generating circuit 36
To the address of the instruction No. 5 being executed by the instruction execution unit. The associative memory 36 is searched by the address. If there is no corresponding entry, there is no output from the associative memories 37 and 38. If the corresponding entry exists, the time chart after (10) will be described later.

In the instruction execution unit 4, the execution of the instruction No. 4 is completed, and the execution of the instruction No. 5 is started.

Cycle T ₇ Instruction No. 7 is read from main memory 5 and stored in memory 34 in the same manner as Instruction No. 1.

In the decoder 35, the instruction No. 6 is analyzed.

The instruction execution unit 4 outputs the address of the instruction No. 10 to the line 133.

The instruction execution unit 4 clears the contents of the memory 34 because the branch was successful.

The cycle T ₈ address generation circuit 32 takes in the address of the instruction No. 10 on the line l33 and outputs the address of the instruction No. 10 to the line l31. The instruction No. 10 is equivalent to the instruction No. 1 is stored in the memory 34.

[0153] In the decoder 35, the contents of the memory 34 is not nothing since had been cleared in cycle T _7.

In the instruction execution unit 4, nothing is performed because the instruction to be executed has not been decoded.

The instruction No. 10 itself is stored in the associative memory 38.

Cycle T _{9 The} instruction No. 11 is read from the main memory 5 and stored in the memory 34 in the same manner as the instruction No. 1.

In the decoder 35, the instruction No. 10 is analyzed. The analysis result is stored in the associative memory 37. The instruction No. 11 itself is also stored in the associative memory 36. At this time, the address of the instruction No. 5 executed last by the instruction execution unit 4 is stored in the associative memory 36. Therefore, the same entry contains the branch source address,
The branch destination instruction and the branch destination instruction analysis result store the branch destination next instruction.

In the instruction execution unit 4, the instruction No.
At the end of the analysis at 10, execution is performed.

(10) Cycle T _{7 In} cycle T ₆ , if the corresponding entry exists in the associative memory 36, the analysis results of the instruction No. 10 and the instruction itself are immediately transmitted from the associative memories 37 and 38 as shown in FIG. Is read. The instruction No. is output from the associative memory 36.
11 is also read and stored in the memory 34.

In cycle T ₇ , the address generation circuit 32 adds the address of the instruction No. 10 given via the line 133 to the address of the instruction No. 10 and adds the length of the instruction No. An address is created and output to line l31. The read instruction No. 12 is stored in the memory 34.

In the decoder 35, the instruction No. 11 is analyzed.

The instruction execution unit 4 executes the instruction No. 10 read from the associative memories 37 and 38 immediately after the execution of the instruction No. 5 is completed.

[0163]

As described above, according to the present invention, even if the instruction control unit and the instruction execution unit operate in parallel, competition for reading data from the main memory hardly occurs, and the speed of instruction processing can be increased. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a conventional data processing device.

FIG. 2 is a diagram showing an instruction format used in an embodiment of the present invention.

FIG. 3 is a diagram showing a format of a special instruction used in the embodiment.

FIG. 4 is a configuration diagram of an embodiment.

FIG. 5 is a configuration diagram of an address generation circuit 32 used in the embodiment.

FIG. 6 is a configuration diagram of an associative memory 31 used in the embodiment.

FIG. 7 is a configuration diagram of associative memories 36, 37, and 38 used in the embodiment.

FIG. 8 is a configuration diagram of a processing circuit 35 used in the embodiment.

FIG. 9 is a configuration diagram of an operand buffer 24 used in the embodiment.

FIG. 10 is a configuration diagram of a line buffer used in the embodiment.

FIG. 11 is a configuration diagram of a selection circuit 21 used in the embodiment.

FIG. 12 is a configuration diagram of a purge control circuit 6 used in the embodiment.

FIG. 13 is a view showing an instruction sequence executed by the apparatus according to the embodiment.

FIG. 14 is a time chart when the instruction sequence shown in FIG. 13 is executed by the apparatus of the embodiment.

[Explanation of symbols]

1. Data processing device 2. Interface unit
3. Command control unit, 4 command execution unit, 5 main memory, 6 purge control circuit.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Kunio Uchiyama, Inventor 1-280, Higashi Koikebo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Ikuya Kawasaki 1450, Josuihoncho, Kodaira-shi, Tokyo Inside the Musashi Factory (72) Inventor Makoto Hanawa 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-50-138728 (JP, A) JP, U)

Claims (3)

(57) [Claims] An instruction address generator for generating an instruction address; an instruction cache memory having a plurality of entries for storing a plurality of instruction addresses and a plurality of instructions corresponding to the plurality of instruction addresses; To the instruction address generated by the
Therefore, the instruction cache memory or other memory
Decode instructions that decode instructions read from
And an operand address generator for generating an operand address in accordance with the output of the instruction decoder, and an operand cache memory having a plurality of entries for storing a plurality of operand addresses and a plurality of operand data corresponding to the plurality of operand addresses When, in the data processing apparatus comprising an address conversion circuit for converting a logical address in which the instruction address generating unit has generated a physical address in accordance with the output of the instruction decoder, a plurality of entries of the instruction cache memory or the operand cache memory A data processing apparatus for designating any one of the plurality of entries to invalidate the data. 2. The data processing device according to claim 1, wherein said data processing device is a microprocessor formed on an LSI chip, and said instruction cache memory is formed in said chip. 3. The data processing apparatus according to claim 1, wherein said instruction cache memory is an associative memory.