JP2656945B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
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- JP2656945B2 JP2656945B2 JP63109957A JP10995788A JP2656945B2 JP 2656945 B2 JP2656945 B2 JP 2656945B2 JP 63109957 A JP63109957 A JP 63109957A JP 10995788 A JP10995788 A JP 10995788A JP 2656945 B2 JP2656945 B2 JP 2656945B2
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- Prior art keywords
- film
- silicon
- nitride
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- sio
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Description
【発明の詳細な説明】 〔発明の概要〕 半導体装置の製造方法に関し、 ピンホールがなくかつ窒化膜の特徴は可及的に失なわ
ないシリコン窒化薄膜をもつ半導体装置の製造方法を提
供することを目的とし、 多結晶シリコン膜の表面、CVD法によりシリコン窒化
膜を堆積する工程、 該シリコン窒化膜の少なくとも表面の一部を酸化する
工程、 該酸化によって形成されたシリコン酸化膜の少なくと
も表面の一部を窒化処理してシリコン窒化酸化膜に変換
する工程、 を有する構成とする。The present invention relates to a method of manufacturing a semiconductor device, and to provide a method of manufacturing a semiconductor device having a silicon nitride thin film that has no pinholes and retains characteristics of a nitride film as little as possible. A step of depositing a silicon nitride film by a CVD method on a surface of a polycrystalline silicon film, a step of oxidizing at least a part of the surface of the silicon nitride film, and a step of oxidizing at least a surface of the silicon oxide film formed by the oxidation. Converting a part into a silicon oxynitride film by nitriding.
本発明は、集積回路のキャパシタなどに用いる絶縁薄
膜の形成に特徴を有する半導体装置の製造方法に関す
る。The present invention relates to a method for manufacturing a semiconductor device characterized by forming an insulating thin film used for a capacitor or the like of an integrated circuit.
LSIの高集積化、高速化に伴ない、絶縁膜の薄膜化が
図られている。特にMOS FETのゲート酸化膜とダイナミ
ックRAMの電荷蓄積容量用の絶縁膜の薄膜化が重要であ
る。As the integration and speed of LSIs increase, the thickness of insulating films has been reduced. In particular, it is important to reduce the thickness of the gate oxide film of the MOS FET and the insulating film for the charge storage capacity of the dynamic RAM.
例えば上記の電荷蓄積容量つまりキャパシタは誘電体
膜とその両側の電極で形成され、容量値は電流面積、誘
電体膜の誘電率と厚さで決まる。集積化が進めば面積は
小になり、しかし容量値は情報記憶上それ程小にするこ
とはできないから、誘電率を大にするか、厚さを小にし
て容量値を確保する必要に迫られる。For example, the above-mentioned charge storage capacitance, that is, a capacitor is formed by a dielectric film and electrodes on both sides thereof, and the capacitance value is determined by a current area, a dielectric constant and a thickness of the dielectric film. As the integration progresses, the area becomes smaller, but the capacitance value cannot be so small for information storage, so it is necessary to increase the dielectric constant or reduce the thickness to secure the capacitance value. .
集積回路の絶縁膜としては二酸化シリコン(SiO2)が
広く用いられているが、最近1Mビット以上のDRAMのキャ
パシタ誘電体膜などには窒化シリコン(Si3N4)膜が使
われている。Si3N4はSiO2より誘電率が50%程高く、高
集積化に有利である。誘電率の更に高いものとしてはタ
ンタル酸化膜などがあるが、これは集積回路ではまだ実
用化されていない。Silicon dioxide (SiO 2 ) is widely used as an insulating film in integrated circuits, but recently silicon nitride (Si 3 N 4 ) has been used as a dielectric film for capacitors of 1 Mbit or more DRAM. Si 3 N 4 has a dielectric constant about 50% higher than that of SiO 2 and is advantageous for high integration. A tantalum oxide film or the like having a higher dielectric constant has not been put to practical use in an integrated circuit yet.
誘電率を大にするには材料を選定する必要があるが、
この点、従来使われていた実績ある誘電体膜の厚さを薄
くすることはそのような必要もなく、簡便な方法ではあ
る勿論、薄くするとピンホールなどの問題がでてくる。
本発明はこの極薄絶縁薄膜の形成に係るものである。To increase the dielectric constant, it is necessary to select a material,
In this regard, it is not necessary to reduce the thickness of a dielectric film that has been used in the past, and it is a simple method. Of course, if the thickness is reduced, problems such as pinholes appear.
The present invention relates to the formation of this ultra-thin insulating thin film.
集積回路の絶縁膜の材料としてはSiO2が中心的に使わ
れてきたが、高集積化に伴なって種々の要求が表われ、
SiO2に係る材料の出現が望まれている。SiO 2 has been mainly used as the material for the insulating film of integrated circuits, but various requirements have emerged with the increase in integration.
The emergence of materials related to SiO 2 is desired.
窒化シリコンは二酸化シリコンに比べて、誘電率が50
%大きい上、構造が緻密であり、強力な不純物拡散バリ
ア効果、高温耐酸化性、耐放射線性がある。Si3N4を薄
膜としてLSI製造工程に導入する方法としてはシリコン
の直接窒化法と、CVDやスパッタによる堆積法がある。
前者は非常に薄い膜を均一に形成できが、反応温度が高
いこと、下地基板がシリコンに限定される欠点がある。
後者はこれらの欠点はないが、薄膜の場合、偶発的な欠
陥を含み易い。Silicon nitride has a dielectric constant of 50 compared to silicon dioxide.
%, It has a dense structure, and has a strong impurity diffusion barrier effect, high-temperature oxidation resistance, and radiation resistance. Methods for introducing Si 3 N 4 as a thin film into an LSI manufacturing process include a direct nitridation method of silicon and a deposition method by CVD or sputtering.
The former can form a very thin film uniformly, but has the disadvantage that the reaction temperature is high and the underlying substrate is limited to silicon.
The latter do not have these drawbacks, but in the case of thin films they tend to contain accidental defects.
CVD法によるシリコ窒化膜の形成ではシリコン源とし
てSiH4,SiClH3,SiCl2H2,SiCl4,SiCl3Hなどを用い、例え
ば次の反応によるSi3N4を生成させる。In the formation of a silicon nitride film by a CVD method, SiH 4 , SiClH 3 , SiCl 2 H 2 , SiCl 4 , SiCl 3 H, or the like is used as a silicon source, and for example, Si 3 N 4 is generated by the following reaction.
SiCl2H2+NH3→Si3N4+HCl Hの多い程低温で成長させることができるが、使い易
さなどから上式の反応を利用することが多い。ところで
このような反応で堆積した膜は、10nm以下の薄い膜では
ピンホールが発生し易く(厚い膜なら後からの堆積でピ
ンホールは埋められてしまう)、ピンホールがあるとリ
ーク電流などがあって不具合である。The more SiCl 2 H 2 + NH 3 → Si 3 N 4 + HCl H can be grown at a lower temperature, but the reaction of the above formula is often used for ease of use. By the way, in a film deposited by such a reaction, a pinhole is easily generated in a thin film having a thickness of 10 nm or less (a pinhole is filled by a later deposition in a thick film). There is a problem.
CVD Si3N4膜のこのような欠点を補うにはSi3N4膜を高
温で酸化処理するのが有効であり、この方法は1Mビット
以上のメモリで実用されている。シリコン基板上にSi3N
4膜はSiO2膜を介して成長させられ、上記酸化処理で表
面がSiO2化されるので、SiO2,Si3N4,SiO2の3層構造の
膜になる。そしてSi3N4膜にピンホールがあっても、酸
化処理で入ってきた酸素がピンホールを埋め、ピンホー
ル無しになることが期待できる。In order to compensate for such a disadvantage of the CVD Si 3 N 4 film, it is effective to oxidize the Si 3 N 4 film at a high temperature, and this method has been practically used for a memory of 1 Mbit or more. Si 3 N on silicon substrate
The four films are grown via the SiO 2 film, and the surface is turned into SiO 2 by the above oxidation treatment, so that the film has a three-layer structure of SiO 2 , Si 3 N 4 , and SiO 2 . And even if the Si 3 N 4 film has a pinhole, it can be expected that oxygen introduced by the oxidation process fills the pinhole and the pinhole is eliminated.
しかしこの3層構造では膜厚低減に難がある。シリコ
ン基板上の熱酸化SiO2膜は基板表面をきれいにするとい
う意味を持っており、基板表面がきれいなら無くてもよ
い。そこで16Mなどの高集積度メモリではこれを除い
て、Si3N4膜を直接シリコン基板上に形成し、その表面
を酸化して、Si3N4,SiO2の2層構造にすることが考えら
れている。However, this three-layer structure has difficulty in reducing the film thickness. The thermally oxidized SiO 2 film on the silicon substrate has a meaning of cleaning the substrate surface, and the substrate surface need not be clean. In high-density memory such as 16M, except for this, the Si 3 N 4 film can be formed directly on the silicon substrate and the surface can be oxidized to form a two-layer structure of Si 3 N 4 and SiO 2 It is considered.
窒化膜の表面酸化はピンホール除去には有効である
が、窒化膜の表面が酸化膜に変るから、前記窒化膜の特
徴は、酸化膜に変る量が多い程失なわれて行く。Oxidation of the surface of the nitride film is effective for removing pinholes, but the surface of the nitride film changes to an oxide film, and the characteristics of the nitride film are lost as the amount of change to the oxide film increases.
本発明はかゝる点を改善し、ピンホールがなくかつ窒
化膜の特徴は可及的に失なわないシリコン窒化薄膜の形
成を可能にすることを目的とするものである。It is an object of the present invention to improve such a point and to enable formation of a silicon nitride thin film having no pinholes and without losing characteristics of the nitride film as much as possible.
第1図に示すように本発明では、基板上に堆積法に
より、実質的にシリコン窒化物よりなる薄膜を形成し、
該薄膜を酸化性雰囲気中で酸化処理して、該薄膜の表
面に二酸化シリコンを主成分とする薄膜を形成し、然る
後、窒化性雰囲気で窒化処理して、該薄層の少なくと
も一部を窒化物を含む層に変換する。As shown in FIG. 1, in the present invention, a thin film substantially composed of silicon nitride is formed on a substrate by a deposition method,
The thin film is oxidized in an oxidizing atmosphere to form a thin film containing silicon dioxide as a main component on the surface of the thin film. To a layer containing nitride.
この方法によればSi3N4層、SiO2層、窒化されたSiO2
層の3層構造の絶縁薄膜が得られ、下記層のSi3N4層は
酸化処理されるのでピンホールがあっても埋められ、ま
た酸化層表面は窒化されるから、酸化層部分は可及的に
薄く、残り全部が窒化層であるから、窒化膜としての特
徴を可及的に保持することができる。According to this method, Si 3 N 4 layer, SiO 2 layer, nitrided SiO 2
An insulating thin film having a three-layer structure is obtained, and the following layer of Si 3 N 4 is oxidized to fill even if there is a pinhole, and the oxide layer surface is nitrided. Since it is as thin as possible and the rest is a nitride layer, the characteristics as a nitride film can be maintained as much as possible.
第2図に本発明の半導体装置の製造方法の工程を示
す。(a)ではシリコン基板11の上に、高濃度にリン
(P)を含む低抵抗の多結晶シリコン膜12を堆積し、こ
の多結晶シリコン膜上にCVD法により窒化膜13を堆積す
る。多結晶シリコン膜12は、構成しようとするキャパシ
タの一方の電極となるもので、通常、シラン(SiH4)の
熱分解で成長させ、厚みは0.2〜1μmである。窒化膜1
3は、SiH4+NH3あるいはSiO2Cl2+NH3等の反応で、約85
0℃の基板温度で多結晶シリコン膜12上に堆積する。1M
ビットのDRAMの場合窒化膜13の厚みは約15nmであるが、
本発明ではこれより薄くてよい。FIG. 2 shows the steps of the method for manufacturing a semiconductor device according to the present invention. 2A, a low-resistance polycrystalline silicon film 12 containing phosphorus (P) at a high concentration is deposited on a silicon substrate 11, and a nitride film 13 is deposited on the polycrystalline silicon film by a CVD method. The polycrystalline silicon film 12 is to be one electrode of a capacitor to be formed, and is usually grown by thermal decomposition of silane (SiH 4 ) and has a thickness of 0.2 to 1 μm. Nitride film 1
3 is the reaction of SiH 4 + NH 3 or SiO 2 Cl 2 + NH 3
It is deposited on the polycrystalline silicon film 12 at a substrate temperature of 0 ° C. 1M
In the case of a bit DRAM, the thickness of the nitride film 13 is about 15 nm,
In the present invention, it may be thinner.
次に(b)では、(a)の状態のものを湿った酸素雰
囲気中で、900℃で、30分処理し、約2nmの、SiO2を主成
分とする超薄膜14を形成する。この酸化工程で窒化膜13
の欠陥(ピンホール)は消滅し、膜の絶縁性が向上す
る。酸化反応は下式で表わせる。Next, in (b), the state shown in (a) is treated in a humid oxygen atmosphere at 900 ° C. for 30 minutes to form an ultra-thin film 14 of about 2 nm mainly composed of SiO 2 . In this oxidation step, the nitride film 13 is formed.
Defects (pinholes) disappear and the insulating properties of the film are improved. The oxidation reaction can be represented by the following equation.
Si3N4+2O2→SiO2+2NO+N2↑ 生成したN2つまり窒素ガスは窒化膜13から雰囲気中へ
出て行くが、NOが残るので、薄膜14は完全な(シリコン
基板を直接熱酸化したときのような)二酸化シリコン層
ではないが、ほゞSiO2層と言ってよい。Si 3 N 4 + 2O 2 → SiO 2 + 2NO + N 2 N The generated N 2, that is, the nitrogen gas, goes out of the nitride film 13 into the atmosphere, but since the NO remains, the thin film 14 is completely (thermally oxidized the silicon substrate directly). It is not a silicon dioxide layer (as it is sometimes), but it can be almost a SiO 2 layer.
次に(c)では、(b)の状態のものを900℃のNH3中
で処理して薄膜14の表面を窒化して窒化酸化膜15にす
る。この反応は次式で表わせる。Next, in (c), the state of (b) is treated in NH 3 at 900 ° C. to nitride the surface of the thin film 14 to form a nitrided oxide film 15. This reaction can be represented by the following equation.
SiO2+NH3→SiOxNy+OH↑ 生成物SiOxNyの酸素量xは処理温度が高い程小になる
が、IC製造工程ではそれ程高い温度は高い利用できない
ので組成はSiONに近い。しかし緻密性、放射線耐性、電
流/電圧ストレス耐性はSi3N4に似ている。また誘電率
は、(b)のもの(従来のもの)より数10%増加する。
(b)(c)の工程は直接反応によるため均一性は良好
である。膜厚の均一性は工程(a)において決定され
る。SiO 2 + NH 3 → SiOxNy + OH ↑ The oxygen amount x of the product SiOxNy becomes smaller as the processing temperature is higher, but the composition is close to SiON because such a high temperature cannot be used high in the IC manufacturing process. However, its denseness, radiation resistance and current / voltage stress resistance are similar to Si 3 N 4 . Also, the dielectric constant is increased by several tens of percent from that of (b) (conventional one).
Since the steps (b) and (c) are based on a direct reaction, the uniformity is good. The uniformity of the film thickness is determined in the step (a).
前記(b)の工程の窒化膜の酸化は、窒化膜の耐酸化
性により容易に進行せず、そこで酸化では20〜30Å程度
の深さまでとする。前記(c)の工程の酸化膜の窒化
も、表面にできた窒化膜が窒化の進行を阻止するので酸
化膜の全部を窒化するのは容易でない。全部窒化しない
場合は窒化層、酸化層、窒化層の3層構造になるが、酸
化層は窒化層でサンドウイッチされているので、絶縁性
などについては全部窒化層の場合と殆んど差がない。Oxidation of the nitride film in the step (b) does not easily proceed due to the oxidation resistance of the nitride film. Therefore, the oxidation is performed to a depth of about 20 to 30 °. Also in the nitridation of the oxide film in the step (c), it is not easy to nitride the entire oxide film because the nitride film formed on the surface prevents the progress of nitridation. When not fully nitrided, it has a three-layer structure of a nitrided layer, an oxide layer, and a nitrided layer. However, since the oxide layer is sandwiched by the nitrided layer, there is almost no difference in insulation and the like from the case of the fully nitrided layer. Absent.
次に(d)では窒化酸化膜15上に金属あるいは半導体
の電極16を形成し、電極12,16、誘電体膜13〜15の構成
のキャパシタを完成する。このキャパシタの最大電界強
度は、Si3N4の真性値に近い10MV/cmが得られる。Next, in (d), a metal or semiconductor electrode 16 is formed on the nitrided oxide film 15, and a capacitor having the electrodes 12, 16 and the dielectric films 13 to 15 is completed. The maximum electric field strength of this capacitor is 10 MV / cm, which is close to the intrinsic value of Si 3 N 4 .
第3図は本発明をDRAMのメモリセルに応用した例を示
す。11a,11bはソース・ドレイン拡散領域、17は多絶縁
シリコンのゲート電極で、これは1トランジスタ1キャ
パシタ型メモリセルの該トランジスタを構成する。キャ
パシタは多結晶シリコン電極12、絶縁膜13〜15、金属ま
たは多結晶シリコンの電極16で構成される。18はゲート
絶縁膜、19はフィールド酸化膜である。FIG. 3 shows an example in which the present invention is applied to a DRAM memory cell. Reference numerals 11a and 11b denote source / drain diffusion regions, and reference numeral 17 denotes a gate electrode made of poly-insulating silicon, which constitutes the transistor of a one-transistor one-capacitor type memory cell. The capacitor includes a polycrystalline silicon electrode 12, insulating films 13 to 15, and a metal or polycrystalline silicon electrode 16. 18 is a gate insulating film, and 19 is a field oxide film.
DRAMメモリセルのキャパシタはMOSキャパシタを使用
するのが普通であるが、集積度向上につれて2電極1誘
電体型の通常のキャパシタが使用され、この場合拡散層
11b上に絶縁膜を介して電極を配設して該キャパシタを
形成するのが普通である。しかしこれでは集積度が上ら
ず、そこで第3図に示すように、トランジスタ部および
フィールド絶縁層上に跨ってキャパシタを構成すること
が考えられている。本発明ではこの第3図の構成のメモ
リセルのキャパシタの誘電膜を一層薄くかつ高誘電率に
することができ、小面積で所要容量のキャパシタを形成
することができる。またキャパシタの信頼性が高く、メ
モリセルの寿命が従来のものより遥かに長く、デバイス
の歩留りも向上する。In general, a MOS capacitor is used as a capacitor of a DRAM memory cell. However, as the degree of integration increases, a normal two-electrode, one-dielectric capacitor is used.
It is usual that the capacitor is formed by disposing an electrode on 11b via an insulating film. However, this does not increase the degree of integration. Therefore, as shown in FIG. 3, it is considered to form a capacitor over the transistor portion and the field insulating layer. In the present invention, the dielectric film of the capacitor of the memory cell having the structure shown in FIG. 3 can be made thinner and have a higher dielectric constant, and a capacitor having a small area and a required capacity can be formed. In addition, the reliability of the capacitor is high, the life of the memory cell is much longer than the conventional one, and the yield of the device is improved.
実施例では窒化シリコン13は多結晶シリコン上に成長
させたが、シリコン基板上に直接または二酸化シリコン
層上などに成長させることもある。In the embodiment, the silicon nitride 13 is grown on polycrystalline silicon, but may be grown directly on a silicon substrate or on a silicon dioxide layer.
以上説明したように本発明では、窒化膜の表面を酸化
し、生成された酸化膜を窒化処理するので、薄い窒化膜
でもピンホールがなく、かつ全体がほゞ窒化膜なので高
い誘電率、絶縁膜としての高信頼性、耐放射線性などが
得られ、甚だ有効である。As described above, in the present invention, since the surface of the nitride film is oxidized and the generated oxide film is subjected to nitriding treatment, even a thin nitride film has no pinholes, and has a high dielectric constant and insulation because it is almost a nitride film. High reliability and radiation resistance as a film are obtained, which is extremely effective.
第1図は本発明の原理説明図、 第2図は本発明の実施例を示す製造工程図、 第3図は本発明の実施例のメモリセルの断面図である。 第2図で11はシリコン基板、12は多結晶シリコン層、13
は窒化膜、14はその酸化層、15は窒化層、16は電極であ
る。FIG. 1 is a view for explaining the principle of the present invention, FIG. 2 is a manufacturing process diagram showing an embodiment of the present invention, and FIG. 3 is a sectional view of a memory cell of the embodiment of the present invention. In FIG. 2, 11 is a silicon substrate, 12 is a polycrystalline silicon layer, 13
Is a nitride film, 14 is its oxide layer, 15 is a nitride layer, and 16 is an electrode.
Claims (1)
シリコン窒化膜を堆積する工程、 該シリコン窒化膜の少なくとも表面の一部を酸化する工
程、 該酸化によって形成されたシリコン酸化膜の少なくとも
表面の一部を窒化処理してシリコン窒化酸化膜に変換す
る工程、 を有することを特徴とする半導体装置の製造方法。1. A step of depositing a silicon nitride film on a surface of a polycrystalline silicon film by a CVD method, a step of oxidizing at least a part of the surface of the silicon nitride film, and a step of oxidizing at least a part of the silicon oxide film formed by the oxidation. Converting a part of the surface to a silicon oxynitride film by nitridation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63109957A JP2656945B2 (en) | 1988-05-06 | 1988-05-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63109957A JP2656945B2 (en) | 1988-05-06 | 1988-05-06 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01280321A JPH01280321A (en) | 1989-11-10 |
| JP2656945B2 true JP2656945B2 (en) | 1997-09-24 |
Family
ID=14523423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63109957A Expired - Lifetime JP2656945B2 (en) | 1988-05-06 | 1988-05-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2656945B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100769135B1 (en) * | 2005-08-12 | 2007-10-22 | 동부일렉트로닉스 주식회사 | Gate dielectric film formation method of semiconductor device |
| JP2007220888A (en) * | 2006-02-16 | 2007-08-30 | Central Res Inst Of Electric Power Ind | Radiation-resistant silicon carbide semiconductor device having a superlattice structure and its operating method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54162967A (en) * | 1978-06-14 | 1979-12-25 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5884462A (en) * | 1981-11-13 | 1983-05-20 | Toshiba Corp | Metal oxide semiconductor type semiconductor device and its manufacture |
-
1988
- 1988-05-06 JP JP63109957A patent/JP2656945B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01280321A (en) | 1989-11-10 |
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