JP2661382B2 - LSI chip connection method - Google Patents
LSI chip connection methodInfo
- Publication number
- JP2661382B2 JP2661382B2 JP2789191A JP2789191A JP2661382B2 JP 2661382 B2 JP2661382 B2 JP 2661382B2 JP 2789191 A JP2789191 A JP 2789191A JP 2789191 A JP2789191 A JP 2789191A JP 2661382 B2 JP2661382 B2 JP 2661382B2
- Authority
- JP
- Japan
- Prior art keywords
- lsi chip
- substrate
- resin
- conductive particles
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Wire Bonding (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、LSIチップ等の微細
な電極と実装基板上に設けた電極との接続実装に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to connection and mounting of fine electrodes such as LSI chips and electrodes provided on a mounting substrate.
【0002】[0002]
【従来の技術】従来、この種の電気接続用異方性導電材
料としては、高分子材料の表面に導電性を有する金属薄
層を形成した導電粒子を含んだ接着剤組成物が用いられ
ており、接続としては、180〜200℃で20〜30
kg/cm2程度の熱圧着方法が用いられていた。2. Description of the Related Art Conventionally, as this type of anisotropic conductive material for electrical connection, an adhesive composition containing conductive particles having a conductive metal thin layer formed on the surface of a polymer material has been used. And the connection is 180 to 200 ° C and 20 to 30
A thermocompression bonding method of about kg / cm 2 has been used.
【0003】以下に従来の実装方法を説明する。図3
は、従来のLSIチップの接続方法を工程順に示す基板
の断面図である。このLSIチップの接続は、次のとお
りである。すなわち、図3(a)に示すように、電極パ
ッド2が形成されたLSIチップ1と、電極パッド2に
対応して形成された電極端子4を有する基板3とを導電
性粒子9を分散させて含有している熱接着樹脂11を介
して向き合わせる。次に、図3(b)に示すように、L
SIチップ1を基板3とに押し付け、加熱することによ
り、熱接着樹脂11を軟化させ、電極パッド2と電極端
子4とを導電性粒子9により、接続することによって行
われる。[0003] A conventional mounting method will be described below. FIG.
FIG. 2 is a cross-sectional view of a substrate showing a conventional LSI chip connection method in the order of steps. The connection of this LSI chip is as follows. That is, as shown in FIG. 3A, the LSI chip 1 on which the electrode pads 2 are formed and the substrate 3 having the electrode terminals 4 formed corresponding to the electrode pads 2 are formed by dispersing the conductive particles 9. Face each other via the thermal adhesive resin 11 contained therein. Next, as shown in FIG.
This is performed by pressing the SI chip 1 against the substrate 3 and heating it to soften the thermal adhesive resin 11 and connect the electrode pads 2 and the electrode terminals 4 with the conductive particles 9.
【0004】[0004]
【発明が解決しようとする課題】上述した従来の接続実
装方法によれば、電極パッドと電極端子間を電気的に接
続している導電性粒子の数量が多くなると隣合う電極パ
ッド、あるいは電極端子間でショートあるいは電流リー
クが発生する。これを避けるために導電性粒子の数量を
少なくすると、接続抵抗が増大すると共にばらつくとい
う問題が発生していた。また甚だしい場合には電気的に
オープンになる接続箇所が発生していた。さらに、最近
の接続寸法の高精細化に伴って、この傾向はますます著
しくなっている。また、LSIチップと基板が厳密に平
行なまま押し付けることは極めて難しく、各々の電極端
子間のギャップにばらつきが発生し、各電極端子間の導
電粒子の数量にばらつきが生じ、結果として接続が不安
定になるという問題があった。これらの現象は、デバイ
スの動作不良を引き起こす重大な欠点となっている。According to the above-described conventional connection mounting method, when the number of conductive particles electrically connecting the electrode pad and the electrode terminal increases, the adjacent electrode pad or electrode terminal becomes larger. Short circuit or current leak occurs between them. If the number of conductive particles is reduced in order to avoid this, there has been a problem that the connection resistance increases and varies. In severe cases, there were connection points that became electrically open. In addition, this trend is becoming more and more remarkable with recent increase in connection dimension. In addition, it is extremely difficult to press the LSI chip and the substrate while they are strictly parallel, and the gap between the respective electrode terminals varies, and the number of conductive particles between the respective electrode terminals varies, resulting in poor connection. There was a problem of becoming stable. These phenomena are serious drawbacks that cause device malfunction.
【0005】本発明の目的は、再現性が良く、安定で、
しかも高精細化が可能なLSIチップの接続方法を提供
することにある。It is an object of the present invention to provide a reproducible, stable,
In addition, it is an object of the present invention to provide a method for connecting an LSI chip capable of high definition.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するた
め、本発明による接続実装方法においては、LSIチッ
プに形成された電極パッドと、該電極パッドに対応して
基板に形成された電極端子とを接続するLSIチップの
接続方法であって、前記LSIチップあるいは、基板表
面の一方に活性エネルギー線による硬化及び熱硬化性を
有する樹脂中に導電性粒子を分散させた溶液を塗布後、
乾燥する工程と、前記導電性粒子を分散させた溶液を塗
布していない基板表面あるいは、LSIチップの一方に
活性エネルギー線による硬化及び熱硬化性を有する樹脂
を塗布後、乾燥する工程と、前記LSIチップ及び、基
板表面の接着剤樹脂をリソグラフィー及び現像により除
去する工程と、前記電極パッドと電極端子とを向き合わ
せ、半導体回路素子と基板間を密着後、熱圧着して硬化
させる工程とを含むものである。In order to achieve the above object, in a connection mounting method according to the present invention, an electrode pad formed on an LSI chip and an electrode terminal formed on a substrate corresponding to the electrode pad are provided. A method of connecting an LSI chip, wherein the LSI chip or one of the surfaces of the substrate is coated with a solution obtained by dispersing conductive particles in a resin having curing and thermosetting properties by active energy rays,
A step of drying, and a step of applying a resin having curability by active energy rays and thermosetting to one of the substrate surface or the LSI chip to which the solution in which the conductive particles are dispersed is not applied, and drying. A step of removing the adhesive resin on the surface of the LSI chip and the substrate by lithography and development, a step of facing the electrode pads and the electrode terminals, and bringing the semiconductor circuit element and the substrate into close contact with each other; Including.
【0007】[0007]
【作用】再現性が良く、安定で、接続信頼性が高く、し
かも高精細化が可能となる。The reproducibility is good, stable, the connection reliability is high, and high definition can be achieved.
【0008】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。図1A,図1Bは、本発明の一実施例としてLSI
チップの接続方法を工程順に示す断面図である。図2
は、本発明方法によって接続されたLSIチップの断面
図である。まず図1Aの(a)に示すように、LSIチ
ップ1の表面には、電極パッド2が形成され、一方基板
3には、電極パッド2に対応して電極端子4が形成され
ている。Next, the present invention will be described with reference to the drawings. FIGS. 1A and 1B show an LSI according to an embodiment of the present invention.
It is sectional drawing which shows the connection method of a chip | tip in a process order. FIG.
FIG. 3 is a sectional view of an LSI chip connected by the method of the present invention. First, as shown in FIG. 1A, an electrode pad 2 is formed on a surface of an LSI chip 1, while an electrode terminal 4 is formed on a substrate 3 corresponding to the electrode pad 2.
【0009】本発明においては、図1Aの(b)に示す
ように、LSIチップ1上に、光硬化性と同時に熱硬化
性を有する樹脂をスピンナー等で均一に塗布後、乾燥す
る。次に、フォトリソグラフィーにより紫外線7露光を
行う。このとき、電極パッド2上の樹脂層を遮光して露
光を行う。図1Aの(c)に示すように、基板3上に、
光硬化性と同時に熱硬化性を有する樹脂中に導電性粒子
を分散させた溶液をスピンナー等で均一に塗布後、乾燥
する。次に、フォトリソグラフィーにより紫外線7露光
を行う。このとき、電極端子4の樹脂層の露光を行う。
実施例では、感光性基(ネガ型)を有したポリイミド前
駆体である旭化成工業株式会社製「パイメル」(商品
名)を用い、導電性粒子としては、積水ファインケミカ
ル株式会社製「ミクロパール」(商品名)を用いた。次
に、図1Bの(d)に示すように、現像液10にて現像
を行い、LSIチップ及び基板3上の樹脂層を除去しマ
スクパターンを作成する。次に図1Bの(e)に示すよ
うに、電極パッド2と電極端子4とを向き合わせる。In the present invention, as shown in FIG. 1A (b), a resin having both photo-curing and thermo-curing properties is uniformly applied onto the LSI chip 1 using a spinner or the like, and then dried. Next, ultraviolet light 7 exposure is performed by photolithography. At this time, the exposure is performed while shielding the resin layer on the electrode pads 2 from light. As shown in FIG. 1A (c), on the substrate 3,
A solution in which conductive particles are dispersed in a resin having both photocurability and thermosetting properties is uniformly applied by a spinner or the like, and then dried. Next, ultraviolet light 7 exposure is performed by photolithography. At this time, the resin layer of the electrode terminal 4 is exposed.
In Examples, "Pimel" (trade name) manufactured by Asahi Kasei Kogyo Co., Ltd., which is a polyimide precursor having a photosensitive group (negative type), was used. As conductive particles, "Micropearl" (manufactured by Sekisui Fine Chemical Co., Ltd.) (Product name). Next, as shown in (d) of FIG. 1B, development is performed with a developer 10 to remove the LSI chip and the resin layer on the substrate 3 to form a mask pattern. Next, as shown in FIG. 1B (e), the electrode pad 2 and the electrode terminal 4 are opposed to each other.
【0010】次に、電極パッド2と電極端子4とを向き
合わせLSIチップ1を基板3上に乗せ、電極パッド2
と電極端子4とをよく密着させる。さらに、10kg/
cm2程度荷重を加えてLSIチップ1を圧下し、同時
に250℃程度に加熱することによって、LSIチップ
と基板3間に配した樹脂を硬化させ、図2のようにLS
Iチップ1と基板3を接着固定する。Next, the LSI chip 1 is placed on the substrate 3 with the electrode pads 2 and the electrode terminals 4 facing each other.
And the electrode terminal 4 are closely adhered. In addition, 10kg /
By applying a load of about 2 cm 2 and lowering the LSI chip 1 and simultaneously heating it to about 250 ° C., the resin disposed between the LSI chip and the substrate 3 is hardened, and the LSI chip 1 as shown in FIG.
The I chip 1 and the substrate 3 are bonded and fixed.
【0011】なお、感光性と熱硬化性を有する樹脂を基
板3に、感光性と熱硬化性を有する樹脂中に導電性粒子
を分散させた溶液をLSIチップ1に塗布し、以下、工
程順に従って接続を行ってもよい。A photosensitive resin and a thermosetting resin are applied to the substrate 3, and a solution in which conductive particles are dispersed in the photosensitive and thermosetting resin is applied to the LSI chip 1. The connection may be made according to the following.
【0012】[0012]
【発明の効果】以上説明したように、本発明のLSIチ
ップの接続方法は、リソグラフィー技術により電極パッ
ドと電極端子間のみに導電性粒子を分散させた接着剤層
を配し、さらに絶縁部分はリソグラフィー技術により、
導電性粒子を含まない接着剤層を配して熱圧着接続され
ているので高精細化接続が確実に、容易に信頼性よく実
施できるという極めて顕著な効果が得られる。As described above, according to the method for connecting an LSI chip of the present invention, an adhesive layer in which conductive particles are dispersed only between an electrode pad and an electrode terminal is provided by lithography technology, and furthermore, an insulating portion is provided. By lithography technology
Since an adhesive layer containing no conductive particles is provided and connected by thermo-compression bonding, an extremely remarkable effect that high-definition connection can be carried out reliably, easily and reliably is obtained.
【図1A】本発明に係わるLSIチップの接続方法の工
程の前段を工程順に示す断面図である。FIG. 1A is a sectional view showing a step preceding a step of a method of connecting an LSI chip according to the present invention in the order of steps;
【図1B】本発明に係わるLSIチップの接続方法の工
程の後段を工程順に示す断面図である。FIG. 1B is a cross-sectional view showing a stage subsequent to the process of the LSI chip connection method according to the present invention in the order of processes.
【図2】本発明方法により接続されたLSIチップの断
面図である。FIG. 2 is a sectional view of an LSI chip connected by the method of the present invention.
【図3】従来のLSIチップの接続方法を工程順に示す
断面図である。FIG. 3 is a cross-sectional view showing a conventional LSI chip connection method in the order of steps.
1 LSIチップ 2 電極パッド 3 基板 4 電極端子 5 感光性と熱硬化性を有する樹脂 6 フォトマスク 7 紫外線 8 導電性粒子を分散させた光と熱硬化性を有する樹脂 9 導電性粒子 10 現像液 11 熱接着樹脂 DESCRIPTION OF SYMBOLS 1 LSI chip 2 Electrode pad 3 Substrate 4 Electrode terminal 5 Photosensitive and thermosetting resin 6 Photomask 7 Ultraviolet 8 Light and thermosetting resin in which conductive particles were dispersed 9 Conductive particles 10 Developer 11 Thermal bonding resin
Claims (1)
と、該電極パッドに対応して基板に形成された電極端子
とを接続するLSIチップの接続方法であって、前記L
SIチップあるいは、基板表面の一方に活性エネルギー
線による硬化及び熱硬化性を有する樹脂中に導電性粒子
を分散させた溶液を塗布後、乾燥する工程と、前記導電
性粒子を分散させた溶液を塗布していない基板表面ある
いは、LSIチップの一方に活性エネルギー線による硬
化及び熱硬化性を有する樹脂を塗布後、乾燥する工程
と、前記LSIチップ及び、基板表面の接着剤樹脂をリ
ソグラフィー及び現像により除去する工程と、前記電極
パッドと電極端子とを向き合わせ、半導体回路素子と基
板間を密着後、熱圧着して硬化させる工程とを含むこと
を特徴とするLSIチップの接続方法。An LSI chip connection method for connecting an electrode pad formed on an LSI chip and an electrode terminal formed on a substrate corresponding to the electrode pad, wherein
After applying a solution obtained by dispersing conductive particles in a resin having curing and thermosetting by active energy rays on one of the SI chip or the substrate surface, a step of drying, and drying the solution in which the conductive particles are dispersed. A step of applying a resin having curing and thermosetting properties by active energy rays to one of the substrate surface or the LSI chip which has not been applied, followed by drying, and lithography and development of the LSI chip and the adhesive resin on the substrate surface. A method of connecting an LSI chip, comprising: a removing step; a step of facing the electrode pad and an electrode terminal; and closely contacting a semiconductor circuit element with a substrate;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2789191A JP2661382B2 (en) | 1991-01-29 | 1991-01-29 | LSI chip connection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2789191A JP2661382B2 (en) | 1991-01-29 | 1991-01-29 | LSI chip connection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04253348A JPH04253348A (en) | 1992-09-09 |
| JP2661382B2 true JP2661382B2 (en) | 1997-10-08 |
Family
ID=12233517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2789191A Expired - Lifetime JP2661382B2 (en) | 1991-01-29 | 1991-01-29 | LSI chip connection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2661382B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3451987B2 (en) | 1998-07-01 | 2003-09-29 | 日本電気株式会社 | Functional element, substrate for mounting functional element, and method of connecting them |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0621260U (en) * | 1992-05-27 | 1994-03-18 | 和正 菅野 | Semiconductor integrated circuit |
| KR100206893B1 (en) * | 1996-03-11 | 1999-07-01 | 구본준 | Semiconductor package and manufacturing method |
| JP7185252B2 (en) | 2018-01-31 | 2022-12-07 | 三国電子有限会社 | Method for producing connection structure |
| JP7160302B2 (en) * | 2018-01-31 | 2022-10-25 | 三国電子有限会社 | CONNECTED STRUCTURE AND METHOD OF MAKING CONNECTED STRUCTURE |
-
1991
- 1991-01-29 JP JP2789191A patent/JP2661382B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3451987B2 (en) | 1998-07-01 | 2003-09-29 | 日本電気株式会社 | Functional element, substrate for mounting functional element, and method of connecting them |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04253348A (en) | 1992-09-09 |
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