JP2663566B2 - Graphic display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic display device effective for use in a man-machine interface device for process control, and more particularly, to a graphic display device provided to a host processor via a common bus. Each graphic display device receives drawing commands and display commands sent from the host processor, and parallelly displays graphics and patterns according to the characteristics of information on display means such as a CRT. The present invention relates to a graphic display device for displaying information.

<Prior Art> A graphic display device used as a man-machine interface device for process control is capable of displaying various kinds of information for managing and controlling the entire plant on a display means effectively and at high speed. Required.

FIG. 7 is a conceptual diagram showing an example of a conventional graphic display device of this type. In the figure, reference numeral 1 denotes a host processor connected to a common bus BS, and reference numerals 21 to 2n denote graphic displays / functions as a man-machine interface connected to the common bus BS.
A keyboard controller having a dedicated sub-processor 3 inside. In addition to the controller, an interface 5 of the disk device, a communication interface 6, and the like are connected to the common bus BS.

In such a conventional device, when the host processor 1 controls the controllers 21 to 2n, the controller, in accordance with an instruction from the host processor 1, executes a command written in a command block of the main storage device 11 of the host processor 1. The host processor 1 is configured to read a command as a bus master, or to transmit a command sequence by directly obtaining a bus right inside the controller and writing a command directly to its internal memory 20. ing.

<Problems to be Solved by the Invention> However, in the apparatus configured as described above, since the controller must be a bus master, the configuration is complicated and the overhead due to transfer of the bus right increases. However, there is a problem that performance degradation cannot be ignored.

Further, the above-described configuration has a problem in that the processing speed of the sub-processor in the controller is greatly reduced by obtaining the bus right.

The present invention has been made in view of these problems, and a purpose thereof is to allow a host processor to efficiently transmit a command to a plurality of display controllers,
An object of the present invention is to realize a graphic display device capable of increasing the efficiency of parallel processing.

<Means for Solving the Problems> FIG. 1 is a block diagram showing a basic configuration of the present invention. In the figure, reference numeral 1 denotes a host processor, and reference numerals 21 to 2n denote a plurality of graphic display devices connected to the host processor 1 via a common bus BS. Reference numerals 5 and 6 denote interface devices such as a disk device and a local area network (LAN) connected to the common bus BS.

In each graphic display device 21-2n, 2a
Is a two-port shared memory, one of which is connected to the common bus BS and the other is connected to the internal bus, 2b is a FIFO buffer provided in a part of this shared memory 2a, 2c is the host processor 1, and Connected to the shared memory 2a.

Here, an empty area for one command is provided in advance in the FIFO buffer formed in the shared memory 2a.

The host processor 1 writes the command sequence into the FIFO buffer. If the FIFO buffer becomes full during the writing, the host processor 1 writes a command to notify the host processor of an interrupt in a free area, and then writes the command sequence. Is configured to be stopped.

Further, the graphic display device is configured to, when reading a command for notifying the host processor of the interrupt from the free space, interrupt the host processor 1 based on the command.

When the host processor 1 receives the interrupt from the graphic display device side, the host processor 1
Writing to the FIFO buffer is restarted.

<Operation> When the host processor 1 issues a drawing request, data indicating a drawing command or a drawing parameter is sent to the shared memory of each graphic display device, and these data are written to the FIFO buffer of the shared memory. Each graphic display device controls transmission of contents by operating a push / pop pointer of the FIFO buffer.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention. Here, only the internal configuration of one graphic display device is shown, but the internal configuration of another graphic display device is the same.

In the shared memory 2a, a FIFO buffer 2b is formed by software, and a push (PUSH) pointer P1 indicating a data write position from the host processor 1 and a pop (PUS) indicating a data read end position of the processor 2c. PO
P) Writing and reading of commands and data can be controlled by the pointer P2.

The other part of the shared memory 2a is an ordinary shared memory in which program codes are written and used for transmitting other information.

2d is a frame buffer, 2e is a drawing controller, 2f is a keyboard interface, and 2g is a color lookup table. Drawing controller 2e is FIFO buffer 2b
And decodes the commands and data read out from the memory, draws necessary patterns and characters on the frame buffer 2d according to the commands and data, reads them out, and displays them on the display means 3 via the color look-up table 2g. It is supposed to do.

 The operation of the device having the above-described configuration will be described below.

FIG. 3 is a time chart showing the processing allocation of each device. As shown in (a), the host processor 1 sequentially issues a high-level command executable by the drawing controller 2e in each of the graphic display devices 21, 22,.
The I command is written into the FIFO buffer 2b of the shared memory 2a asynchronously with the processor 2c and the drawing controller 2e, and the push pointer P1 of the FIFO buffer is raised.

Here, the capacity of the FIFO buffer 2b is large enough to write commands and data groups necessary to display an average graphic panel, and the host processor 1 executes the drawing of the corresponding graphic display device. The drawing process is ended without waiting for the end of the process, and the process sequentially proceeds to the next graphic display device.

In each of the graphic display devices 21 to 2n, the processor 2c compares the positions of the push pointer P1 and the pop pointer P2 of the FIFO buffer 2b in the shared memory, and knows the arrival of the command from the host processor 1.

The processor 2c reads a high-level command written in the FIFO buffer 2b and executes processing such as keyboard communication. In addition, the host processor 1 performs part of the processing that the host processor 1 should originally execute, such as interpretation of high-level commands, processing for converting the command to a command that can be executed by the drawing controller 2e, and control of the drawing controller 2e. The burden is reduced.

The drawing controller 2e draws a command sequence on the frame buffer 2d or reads it out according to a command given from the processor 2c.

(B)-(e) each graphic display device
In 21 to 24, the processor 2c receives the command processing,
The timing at which drawing is performed is shown, and overheads for sending and receiving commands, interpreting commands, and controlling execution are added. However, each graphic display device executes command processing and a drawing task in parallel.

(F) shows a case of a conventional device in which the host processor 1 performs command processing and drawing execution of each graphic display device for reference.

In the comparison between (a) and (f), the load on the host processor 1 is reduced by the shortened amount, and the spare capacity is increased.

FIG. 4 is a flowchart showing the outline of the operation performed by the driver of the host processor 1 via the shared memory 2a and the drawing task performed by the graphic display device 2 described above.

The driver of the host processor 1 first outputs the command sequence to the FIFO buffer 2b of the shared memory 2a, and performs writing while updating the push pointer P1 by one command from the location indicated by the push pointer P1 until the writing to the FIFO buffer 2b is completed. Do (step,). When the writing is completed, a notification interrupt is issued to the drawing controller 2e (step). In the step, when the end address is reached at the time of writing one command, the process returns to the start and continues writing. The writing here is performed such that the push pointer P1 does not catch up with the pop pointer P2. In addition, in the step, the update of the push pointer P1 has been completed in the FIFO buffer 2b.
The pointer P1 indicates the next position of the command.

The processor 2c and the drawing controller 2e of the graphic display device 2 include a push / pop pointer P1,
It is determined whether the position indicated by P2 is the same, and if not the same, one command is read from the position of the FIFO buffer indicated by the pop pointer P2, interpreted, and the drawing process is executed.

Subsequently, the position indicated by the pop pointer P2 is updated so as to point to the head of the command following the command just read. When the positions pointed to by the push / pop pointers P1 and P2 become the same, the command reading ends.

In such a series of operations, writing to and reading from the FIFO buffer 2b are both performed asynchronously.
Commands may be stored until the FO buffer is full.

In this case, the following control is performed. That is, FIFO
The buffer has a free area for one command in advance, and when the FIFO buffer becomes full, the driver writes “notify the host processor of an interrupt” in this area.
Then, the output of the command sequence is temporarily terminated.

The graphic display device sequentially reads the contents of the FIFO buffer, performs drawing processing, and finally interrupts the host processor to notify the driver that the FIFO buffer is empty. The driver receiving this notification restarts the interrupted writing of the command sequence.

FIG. 5 is a conceptual view showing the structure of a main part of another embodiment of the present invention. In this embodiment, a plurality of FIFO buffers (two buffers in this embodiment) 2b each storing a command sequence corresponding to a processing priority level in a shared memory 2a
It is configured to provide 1, 2b2.

In such a configuration, the driver in the host processor 1 issues a priority FIFO buffer 2b1 to a command sequence CA having a high priority level, such as displaying alarm information.
The normal graphic display command sequence CB is written in the normal FIFO buffer 2b2.

The graphic display device 2 first determines whether a command string is stored in the priority FIFO buffer 2b1, and if it is stored therein, first reads this command string, executes a drawing process, and executes the priority FIFO buffer. When the space becomes free, the command sequence stored in the normal FIFO buffer 2b2 is read, and the drawing process is executed.

FIG. 6 is a flowchart showing an example of the operation performed by the graphic display device in the embodiment of FIG. The determination as to whether or not a command string has been written to the priority FIFO buffer 2b1 is made every time one command is executed during the processing of the normal FIFO buffer 2b2.

With such a configuration, a display with a high priority level, such as alarm information, can be subjected to a drawing process prior to other graphic displays.

<Effects of the Invention> As described in detail above, according to the present invention, each of the graphic display devices performs a parallel distributed processing of a part of the processing that should be originally performed by the host processor. The processing capacity is reduced, and the processing capacity as a whole can be improved.

In addition, by using a configuration in which the host processor and the graphic display device are coupled via a FIFO buffer formed in the shared memory, the graphic display device does not need to be a bus master,
Since the configuration is simplified and the bus right is not taken up by the host processor, there is no problem that the processing speed of the graphic display device is reduced.

In addition, since the FIFO buffer is formed in software in the shared memory, it can be used freely as a memory.In addition, if necessary, multiple FIFO buffers can be formed, and a command sequence with a high priority level can be used for other commands. Processing can be performed prior to the command sequence.

Also, in the present invention, a free space for one command is provided in advance in a FIFO buffer formed in the shared memory 2a, and when the FIFO buffer becomes full while a command string is being written to the FIFO buffer, In this configuration, a command for notifying an interrupt to the host processor is written.

Therefore, the host processor can confirm that the FIFO buffer is empty by receiving the interrupt from the graphic display device side, and can resume the output of the interrupted command sequence. Therefore, it is not necessary for the host processor to constantly monitor the progress of processing on each graphic display device side, and there is an effect that parallel operations on a plurality of graphic display devices can be performed more effectively.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention, and FIG.
FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 3 is a time chart showing the processing allotment of each device. FIG. 4 shows the operation performed by the driver of the host processor via the shared memory and the graphic display device. FIG. 5 is a flowchart showing an outline of a drawing task to be performed, FIG. 5 is a conceptual diagram showing the configuration of a main part showing another embodiment of the present invention, and FIG. 6 is an example of an operation performed by the graphic display device in the embodiment of FIG. FIG. 7 is a conceptual diagram showing an example of a conventional graphic display device of this type. 1 ... host processor 2 ... graphic display device 3 ... display means 4 ... keyboard 2a ... shared memory 2b ... FIFO buffer 2c ... processor 2d ... frame buffer 2e ... Drawing controller, 2f: Keyboard interface, 2g: Color lookup table, P1: Push pointer, P2: Pop pointer,

Claims (1)

(57) [Claims] 1. A system in which a plurality of graphic display devices are connected to a host processor via a common bus, wherein each of the graphic display devices has one connected to a common bus and the other connected to an internal bus. A shared memory of the port; and a FIFO buffer formed in the shared memory and having a free area for one command in advance. The host processor stores a command string in the FIFO buffer from a position indicated by a push pointer of the FIFO buffer. Writing while updating the position of the push pointer, when the FIFO buffer becomes full in the middle of the writing, stops writing the command sequence to notify the host processor of the interrupt in the empty area, and stops the graphic display device from writing. FIFO buffer pop pointer finger When a command string is read from the location to be indicated, the command sequence is interpreted and the drawing process is executed, and when a command for notifying the host processor of an interrupt is read from the empty area, an interrupt is issued to the host processor based on the command, The graphic display device, wherein the host processor restarts writing a command string to the FIFO buffer when receiving the interrupt from the graphic display device side.