JP2663638B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2663638B2 JP2663638B2 JP16462789A JP16462789A JP2663638B2 JP 2663638 B2 JP2663638 B2 JP 2663638B2 JP 16462789 A JP16462789 A JP 16462789A JP 16462789 A JP16462789 A JP 16462789A JP 2663638 B2 JP2663638 B2 JP 2663638B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- semiconductor chip
- lead piece
- lead
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔概要〕 内端部が半導体チップに接続された複数本のリード片
の各外端部と、半導体チップ搭載基板に形成された導体
パターンとを接続せしめる半導体装置の製造方法に関
し、 該導体パターンとリード片との接続を容易かつ確実な
らしめることを目的とし、 半導体チップを搭載し該半導体チップに内端部が接続
された複数本のリード片の各外端部に接続される複数本
の導体パターンが形成された基板には、少なくとも該半
導体チップの同一側に配設された該導体パターンの各内
端部を連結させた連結導体パターンを形成し、 該連結導体パターンに該リード片の外端部を接続させ
たのち、 対応する該導体パターンと該リード片との位置ずれを
位置ずれ認識手段で認識し、 認識手段で得た位置ずれ情報を基に対応する該導体パ
ターンと該リード片の外端部とが含まれるように該連結
導体パターンを切断することを特徴とし構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] Manufacture of a semiconductor device for connecting each outer end of a plurality of lead pieces whose inner ends are connected to a semiconductor chip to a conductor pattern formed on a semiconductor chip mounting substrate A method for easily and securely connecting the conductor pattern and the lead piece, and mounting a semiconductor chip on each outer end of a plurality of lead pieces having inner ends connected to the semiconductor chip. On a substrate on which a plurality of conductor patterns to be connected are formed, a connection conductor pattern is formed by connecting at least the respective inner ends of the conductor patterns provided on the same side of the semiconductor chip. After connecting the outer end portion of the lead piece to the pattern, the displacement between the corresponding conductor pattern and the lead piece is recognized by the displacement recognition means, and the corresponding displacement is obtained based on the displacement information obtained by the recognition means. The The connecting conductor pattern is cut so as to include the conductor pattern and the outer end of the lead piece.
本発明は半導体チップの搭載方法、特に内端部が半導
体チップに接続されたリード片の外端部と、半導体チッ
プ搭載基板に形成された導体パターンとを、容易かつ確
実に接続せしめるようにした新規方法に関する。The present invention provides a method for mounting a semiconductor chip, particularly, an outer end of a lead piece having an inner end connected to a semiconductor chip, and a conductor pattern formed on a semiconductor chip mounting substrate, which is easily and reliably connected. Regarding the new method.
従来、TAB(Tape Automated Bonding)用半導体チッ
プをセラミック基板またはプリント配線板に搭載する方
法は、フィルムキャリアに形成されたリード片の内端部
を該チップに接続(インナーボンディング)したのち、
該キャリアから切り離した各リード片の外端部を、チッ
プ搭載基板に形成された導体パターンの内端部と接続
(アウターボンディング)する方法であった。Conventionally, a method of mounting a semiconductor chip for TAB (Tape Automated Bonding) on a ceramic substrate or a printed wiring board is to connect an inner end of a lead piece formed on a film carrier to the chip (inner bonding).
In this method, the outer end of each lead piece separated from the carrier is connected to the inner end of the conductor pattern formed on the chip mounting board (outer bonding).
第5図は従来方法でセラミック基板にTAB用ICチップ
を搭載した模式平面図(イ)とその模式断面図(ロ)で
ある。FIG. 5 is a schematic plan view (a) in which a TAB IC chip is mounted on a ceramic substrate by a conventional method, and a schematic cross-sectional view thereof (b).
第5図において、1はセラミック基板,2は基板1の上
面にパターン形成された導体パターン,3はICチップ,4は
内端部をICチップ3にボンディングし外端部を導体パタ
ーン2の内端部にボンディングしたリード片(テー
プ),5は基板1にICチップ2を接着させた接着層であ
り、導体パターン2は、搭載されたICチップ3の四方に
それぞれ複数本ずつ放射状に形成される。In FIG. 5, 1 is a ceramic substrate, 2 is a conductor pattern formed on the upper surface of the substrate 1, 3 is an IC chip, 4 is an inner end bonded to the IC chip 3 and an outer end is formed in the conductor pattern 2. Lead pieces (tapes) 5 bonded to the ends are an adhesive layer in which the IC chip 2 is bonded to the substrate 1, and a plurality of conductive patterns 2 are formed radially on each side of the mounted IC chip 3. You.
一般に、導体膜をエッチングして形成される導体パタ
ーン2は、幅が100μm〜200μm,その幅方向に整列する
間隔が100μm程度である。Generally, the conductor pattern 2 formed by etching the conductor film has a width of 100 μm to 200 μm, and the interval of alignment in the width direction is about 100 μm.
ICチップ3と導体パターン2との接続媒体であるリー
ド片4は、幅が50〜100μm程度であり、外端部が導体
パターン2と同一ピッチに形成されるリード片4の内端
部の間隔は、多数のリード片4をICチップ3と接続可能
にするため外端部ピッチより小さく、一般に70μm程度
である。そのため、一部のリード片4は直状に,他の一
部は中間部を鉤形に曲げた形状に形成される。The lead piece 4 serving as a connection medium between the IC chip 3 and the conductor pattern 2 has a width of about 50 to 100 μm, and the outer end is formed at the same pitch as the conductor pattern 2. Is smaller than the pitch of the outer end portion so that many lead pieces 4 can be connected to the IC chip 3, and is generally about 70 μm. Therefore, some of the lead pieces 4 are formed in a straight shape, and others are formed in a shape in which an intermediate portion is bent into a hook shape.
しかしながら、リード片4の外端部を導体パターン2
に接続させるに先立ってICチップ3の位置決め、即ち、
フィルムキャリアに被着させた導体膜から形成したのち
切り出されたリード片4の外端部が、チップ搭載基板に
形成した導体パターン2の幅に収まるようにする位置決
めが困難であり、また、機械的強度の弱いリード片4が
変形し易いこともあって、導体パターン2に対しその幅
方向にリード片4が外れて接続され易いという問題点が
あった。However, the outer end of the lead piece 4 is
Positioning of the IC chip 3 prior to connection to
It is difficult to position the lead piece 4 cut out after being formed from the conductive film adhered to the film carrier so that the outer end of the lead piece 4 fits into the width of the conductive pattern 2 formed on the chip mounting board. There is a problem that the lead piece 4 having a low mechanical strength is easily deformed, and the lead piece 4 is easily detached from the conductor pattern 2 in the width direction and is connected.
特に、リード片4がICチップ3の四辺にそれぞれ100
本以上接続されているようなとき、前記問題点は一層顕
著に現れる。In particular, the lead pieces 4 are 100
When more than one connection is made, the above problem becomes more pronounced.
上記課題の解決を目的とした本発明による半導体チッ
プの搭載方法は、その実施例を示す第1図によれば、半
導体チップ3を搭載し該半導体チップ3に内端部が接続
された複数本のリード片4の各外端部に接続される複数
本の導体パターン2が形成された基板1には、少なくと
も半導体チップ3の同一側に配設された複数本の導体パ
ターン2の各内端部を連結させる連結導体パターン11を
形成し、 連結導体パターン11にリード片4の外端部を接続させ
たのち、 対応する該導体パターン2と該リード片4との位置ず
れを位置ずれ認識手段13で認識し、 認識手段13で得た位置ずれ情報を基に対応する導体パ
ターン2とリード片4の外端部とが含まれるように連結
導体パターン11を切断することを特徴とする。According to FIG. 1 showing an embodiment of the method for mounting a semiconductor chip according to the present invention for solving the above-mentioned problem, a plurality of semiconductor chips having a semiconductor chip 3 mounted and an inner end connected to the semiconductor chip 3 are connected. The substrate 1 on which the plurality of conductor patterns 2 connected to the respective outer ends of the lead pieces 4 are formed, at least the inner ends of the plurality of conductor patterns 2 disposed on the same side of the semiconductor chip 3. After forming the connecting conductor pattern 11 for connecting the parts and connecting the outer end of the lead piece 4 to the connecting conductor pattern 11, a displacement between the corresponding conductor pattern 2 and the lead piece 4 is detected by a displacement detecting means. The connection conductor pattern 11 is cut so as to include the corresponding conductor pattern 2 and the outer end of the lead piece 4 based on the positional displacement information obtained by the recognition means 13 and the recognition means 13.
上記手段によれば、半導体チップ搭載基板には導体パ
ターンと該導体パターンの内端部を連結させる連結導体
パターンとを形成し、半導体チップに接続されたリード
の外端部を該連結導体パターンに接続したのち、それぞ
れが導体パターンとリード片の外端部とを含むように連
結導体パターンを切断するため、基板に半導体チップを
搭載(接着)させたとき、導体パターンとリード片との
位置決めは大まかでよいことになる。According to the above means, a conductor pattern and a connection conductor pattern for connecting an inner end of the conductor pattern are formed on the semiconductor chip mounting board, and an outer end of a lead connected to the semiconductor chip is formed on the connection conductor pattern. After the connection, the connection conductor pattern is cut so that each includes the conductor pattern and the outer end of the lead piece. When the semiconductor chip is mounted (adhered) to the substrate, the positioning of the conductor pattern and the lead piece is performed. That's a good thing.
従って、本発明方法は半導体チップの搭載が容易化さ
れると共に、全リード片の外端部はその幅全体で外部接
続されるようになる。Therefore, according to the method of the present invention, the mounting of the semiconductor chip is facilitated, and the outer ends of all the lead pieces are externally connected over the entire width.
以下に、図面を用いて本発明の実施例によるTABで形
成した半導体装置の製造方法を説明する。Hereinafter, a method for manufacturing a semiconductor device formed by TAB according to an embodiment of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例によりTABチップをその搭
載基板に搭載する主要工程の説明図、第2図は該基板に
形成した接続導体パターンの切断溝の形成例を示す拡大
平面図、第3図は該切断に使用したレーザ照射装置のシ
ステム主要構成図であり、各図において前出図と共通部
分には同一符号を使用する。FIG. 1 is an explanatory view of main steps of mounting a TAB chip on a mounting board according to an embodiment of the present invention, FIG. 2 is an enlarged plan view showing an example of forming a cutting groove of a connection conductor pattern formed on the board, FIG. 3 is a system configuration diagram of a laser irradiation apparatus used for the cutting. In each of the drawings, the same reference numerals are used for the same parts as those in the preceding drawings.
TABチップ搭載基板の模式平面図である第1図(イ)
において、セラミック基板1の上面には、搭載されるIC
チップのリード片が接続される複数本の導体パターン2
と、放射状に形成された各導体パターン2の内端部を連
結させる角形枠状の連結導体パターン11とを形成させ
る。Fig. 1 (a) which is a schematic plan view of a TAB chip mounting substrate.
The IC mounted on the upper surface of the ceramic substrate 1
A plurality of conductor patterns 2 to which lead pieces of a chip are connected
Then, a square frame-shaped connection conductor pattern 11 for connecting the inner ends of the respective conductor patterns 2 formed radially is formed.
ICチップのリード片の外端部が重なるように形成され
た連結導体パターン11と導体パターン2とは、基板1に
被着させた導体膜から同時形成したものであり、セラミ
ックにてなる基板1に形成されるそれらは、例えばタン
グステン,ニッケル,金よりなる3層構成であり、基板
1にプラスチック等からなるプリント配線板を使用した
ときは、例えば銅,ニッケル,金の3層構成である。The connecting conductor pattern 11 and the conductor pattern 2 which are formed so that the outer ends of the lead pieces of the IC chip overlap each other are formed simultaneously from the conductor film adhered to the substrate 1, and the substrate 1 made of ceramic Are formed, for example, in a three-layer structure made of tungsten, nickel, and gold. When a printed wiring board made of plastic or the like is used for the substrate 1, the three-layer structure is made of, for example, copper, nickel, and gold.
基板1にICチップ3を搭載した模式平面図である第1
図(ロ)において、接着層例えば銀ペーストを用いて基
板1の上面にICチップ3を搭載し、ICチップ3の四方に
延在する各リード片4の外端部は、熱圧着等にて連結導
体パターン11に接続させる。その際、ICチップ3は連結
導体パターン11のほぼ中央に位置決めする。FIG. 1 is a schematic plan view in which an IC chip 3 is mounted on a substrate 1.
In FIG. 2B, the IC chip 3 is mounted on the upper surface of the substrate 1 using an adhesive layer, for example, silver paste, and the outer ends of the respective lead pieces 4 extending in all directions of the IC chip 3 are heat-pressed or the like. The connecting conductor pattern 11 is connected. At that time, the IC chip 3 is positioned substantially at the center of the connection conductor pattern 11.
しかるのち、模式平面図である第1図(ハ]に示す如
く、それぞれが1本ずつの導体パターン2とリード片4
を含むように、レーザやイオンビームまたは機械加工手
段で連結導体パターン11に切断溝12を形成せしめ、ICチ
ップ3の搭載に係わる作業が完了する。Thereafter, as shown in FIG. 1 (c) which is a schematic plan view, one conductor pattern 2 and one lead piece 4 are respectively provided.
Then, a cutting groove 12 is formed in the connecting conductor pattern 11 by a laser, an ion beam, or a mechanical processing means so that the operation relating to the mounting of the IC chip 3 is completed.
第2図において、12aは連結導体パターン11をその直
角方向の直状に切断した溝,12bは連結導体パターン11を
斜めの直状に切断した溝,12cは連結導体パターン11を中
間部で鉤形に切断した溝であり、導体パターン2の延長
領域にリード片4aがほぼ収まるとき、連結導体パターン
11はリード片4aの両側を切断溝12aで切断する。そし
て、導体パターン2の延長領域から横方向に少しずれた
リード片4bは、ずれた方向の連結導体パターン11を切断
溝12bにて切断し、リード片4bよりもさらに大きく横方
向にずれたリード片4cは、ずれた方向の連結導体パター
ン11を切断溝12cで切断する。In FIG. 2, reference numeral 12a denotes a groove obtained by cutting the connecting conductor pattern 11 in a right angle direction, 12b denotes a groove obtained by cutting the connecting conductor pattern 11 into an oblique straight shape, and 12c denotes a hook formed by connecting the connecting conductor pattern 11 at an intermediate portion. When the lead piece 4a is almost fitted in the extended area of the conductor pattern 2, the connecting conductor pattern
11 cuts both sides of the lead piece 4a with the cutting groove 12a. Then, the lead piece 4b slightly shifted in the lateral direction from the extended area of the conductor pattern 2 cuts the connecting conductor pattern 11 in the shifted direction by the cutting groove 12b, and the lead shifted further in the horizontal direction than the lead piece 4b. The piece 4c cuts the connecting conductor pattern 11 in the shifted direction by the cutting groove 12c.
このように、連結導体パターン11の切断溝12の形状
は、リード片4のずれに応じて変化させなければなら
ず、その方法を用いて説明する。As described above, the shape of the cut groove 12 of the connection conductor pattern 11 must be changed in accordance with the displacement of the lead piece 4, and the method will be described.
第3図において、位置ずれ認識手段(テレビカメラ
等)13は、対向すべき導体パターン2とリード片4との
ずれおよび導体パターン2に対するリード片4の位置を
認識し、制御手段14が識別手段13からの情報に基づいて
各導体パターン2に対する切断溝12a,12b,12cの選択お
よびその切り始め位置を設定すると、制御手段14からの
情報に基づいてレーザ光17またはセラミック基板1を搭
載したステージ18を移動させるX−Y駆動手段15が動作
し、レーザ照射手段16から出射するレーザ光が導体パタ
ーン11を切断するようになる。In FIG. 3, a position shift recognizing means (television camera or the like) 13 recognizes a shift between the conductor pattern 2 to be opposed and the lead piece 4 and a position of the lead piece 4 with respect to the conductive pattern 2. When the selection of the cutting grooves 12a, 12b and 12c for each conductor pattern 2 and the setting of the cutting start position are set based on the information from the controller 13, the stage on which the laser beam 17 or the ceramic substrate 1 is mounted is controlled based on the information from the control means 14. The XY driving means 15 for moving the 18 is operated, and the laser light emitted from the laser irradiation means 16 cuts the conductor pattern 11.
第4図は本発明の他の実施例に係わり、半導体チップ
搭載基板に形成された導体パターンと連結導体パターン
とを示す模式平面図であり、基板1の上面に設定された
半導体チップ搭載領域22の四方にそれぞれ形成された連
結導体パターン21a,21b,21c,21dは、搭載領域22の同一
側に整列する各導体パターン2の内端部をそれぞれに接
続する構成、即ち第1図に示す連結導体パターン11のコ
ーナ部をなくしたものであり、連結導体パターン11と同
様に切断したとき、該コーナ部が基板上に残らないおよ
び、該コーナ部を除去する手間が省けるようになる。FIG. 4 is a schematic plan view showing a conductor pattern and a connection conductor pattern formed on a semiconductor chip mounting substrate according to another embodiment of the present invention, and shows a semiconductor chip mounting area 22 set on the upper surface of the substrate 1. The connecting conductor patterns 21a, 21b, 21c, 21d formed on the four sides respectively connect the inner ends of the conductor patterns 2 aligned on the same side of the mounting area 22, that is, the connection shown in FIG. The corner portion of the conductor pattern 11 is eliminated, and when the connection portion is cut in the same manner as the connection conductor pattern 11, the corner portion does not remain on the substrate, and the labor for removing the corner portion can be omitted.
以上説明したように本発明方法によれば、半導体チッ
プ搭載基板には導体パターンと該導体パターンの内端部
を連結させる連結導体パターンとを形成し、半導体チッ
プに接続されたリードの外端部を該連結導体パターンに
接続したのち、それぞれが導体パターンとリード片の外
端部とを含むように連結導体パターンを切断するため、
導体パターンにに対するリード片との位置決めは大まか
でよいことによって、半導体チップの搭載作業が容易化
されると共に、全リード片の外端部はその幅全体で外部
接続されるようになるため、該接続の信頼性を確保し得
た効果がある。As described above, according to the method of the present invention, a conductor pattern and a connection conductor pattern for coupling an inner end of the conductor pattern are formed on a semiconductor chip mounting board, and an outer end of a lead connected to the semiconductor chip is formed. After connecting the connection conductor pattern, to cut the connection conductor pattern so that each includes the conductor pattern and the outer end of the lead piece,
Since the positioning of the lead piece with respect to the conductor pattern may be roughly performed, the work of mounting the semiconductor chip is facilitated, and the outer ends of all the lead pieces are externally connected over the entire width thereof. This has the effect of ensuring the reliability of the connection.
第1図は本発明の一実施例の説明図、 第2図は本発明による接続導体パターンの切断溝の形成
例を示す図、 第3図は本発明に使用したレーザ照射装置のシステム主
要構成図、 第4図は本発明の他の実施例の説明図、 第5図は従来技術の説明図、 である。 図中において、 1は半導体チップ搭載基板、 2は導体パターン、 3はICチップ(半導体チップ)、 4はリード片、 11,21a,21b,21c,21dは連結導体パターン、 12,12a,12b,12cは切断溝、 を示す。FIG. 1 is an explanatory view of one embodiment of the present invention, FIG. 2 is a view showing an example of forming a cutting groove of a connection conductor pattern according to the present invention, and FIG. 3 is a system main configuration of a laser irradiation apparatus used in the present invention. FIG. 4 is an explanatory view of another embodiment of the present invention, and FIG. 5 is an explanatory view of a conventional technique. In the figure, 1 is a semiconductor chip mounting substrate, 2 is a conductor pattern, 3 is an IC chip (semiconductor chip), 4 is a lead piece, 11,21a, 21b, 21c, 21d are connection conductor patterns, 12,12a, 12b, 12c indicates a cutting groove.
Claims (1)
プ(3)に内端部が接続された複数本のリード片(4)
の各外端部に接続される複数本の導体パターン(2)が
形成された基板(1)には、少なくとも該半導体チップ
(3)の同一側に配設された複数本の該導体パターン
(2)の各内端部を連結させた連結導体パターン(11)
を形成し、 該連結導体パターン(11)に該リード片(4)の外端部
を接続させたのち、 対応する該導体パターン(2)と該リード片(4)との
位置ずれを位置ずれ認識手段(13)で認識し、 認識手段(13)で得た位置ずれ情報を基に対応する該導
体パターン(2)と該リード片(4)の外端部とが含ま
れるように該連結導体パターン(11)を切断することを
特徴とする半導体装置の製造方法。1. A plurality of lead pieces (4) having a semiconductor chip (3) mounted thereon and having an inner end connected to the semiconductor chip (3).
On the substrate (1) on which a plurality of conductor patterns (2) connected to each outer end of the semiconductor chip (3) are formed, at least a plurality of the conductor patterns (2) arranged on the same side of the semiconductor chip (3). 2) Connected conductor pattern (11) connecting the inner ends
After the outer end of the lead piece (4) is connected to the connecting conductor pattern (11), the displacement between the corresponding conductor pattern (2) and the lead piece (4) is corrected. The connection is performed such that the conductor pattern (2) and the outer end portion of the lead piece (4) corresponding to the conductor pattern (2) are recognized based on the displacement information obtained by the recognition means (13). A method of manufacturing a semiconductor device, comprising cutting a conductive pattern (11).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16462789A JP2663638B2 (en) | 1989-06-27 | 1989-06-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16462789A JP2663638B2 (en) | 1989-06-27 | 1989-06-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0330348A JPH0330348A (en) | 1991-02-08 |
| JP2663638B2 true JP2663638B2 (en) | 1997-10-15 |
Family
ID=15796798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16462789A Expired - Fee Related JP2663638B2 (en) | 1989-06-27 | 1989-06-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2663638B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ID19806A (en) * | 1997-01-31 | 1998-08-06 | Tanaka Sangyo Co Ltd | HANDLES FOR WHEED SEEDS BAG |
| DE102005005471A1 (en) * | 2005-02-04 | 2006-08-24 | Barthelt, Hans-Peter, Dipl.-Ing. | Care bed with balancing circuit |
-
1989
- 1989-06-27 JP JP16462789A patent/JP2663638B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0330348A (en) | 1991-02-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |