JP2663733B2 - Gray-binary conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for performing gray-binary conversion necessary for an analog-to-digital converter.
About the law.

[0002]

BACKGROUND ART ene in analog-to-digital converter
The coder, but Gray code is used to suppress errors due to bubbling or the like to a minimum, the output for outputting a binary code, it is necessary that converts a gray code into a binary code.

FIG. 4 shows a conventional gray-binary conversion method.
Shows a gray over binary conversion circuit according to (n = 8-bit). Here, the n-bit gray and binary codes are G _{n to} G ₁ and B _{n to} B ₁ , respectively, from the most significant bit. In the conventional gray-binary conversion method , the most significant bits match each other, and the m-th binary code B
_m is obtained by taking the exclusive OR of the next higher binary code B _{m + 1} and the m-th bit gray code G _m .

[0004]

SUMMARY OF THE INVENTION However, the conventional
Gray - for binary conversion circuit according to the conversion method, when converting gray code of n bits into a binary code, which must pass through the n-1 exclusive logic gates to binary code B ₁ least significant bit is determined , A time delay corresponding to the gate n-1 stage occurs. Such a time delay becomes a serious problem in a high-speed analog-to-digital converter using a Gray code as an encoder.

[0005] The present invention has been made in view of such problems, gray <br/> Lee can Rukoto minimal time delay - and to provide a binary conversion method.

[0006]

In the gray-to-binary conversion method according to the first aspect of the present invention, when converting an n-bit Gray code into a binary code, first, the m-th bits _Gm and m + 1 of the Gray code are converted. bit G _{m + 1} of an exclusive OR, d (1, m) to generate a (1 ≦ m ≦ n-2 0 = n-
1). Next, d (1,1) to d (1, n-1) generated in this way
Respect of the output, d (1, m) and ^{d (1, m + 2 1} ) takes the exclusive OR, d (2, m) to generate a (1 ≦ m ≦ n-2 1 = n −
2). Here, d (1, n) is _Gn . Similarly, d (2,1)
~ (2, n-2) is ORed with d (2, m) and d (2, m + 2 ² ) to generate d (3, m) (1 ≦ m ≦ ^n-2 2
= N-4). Where d (2, n) = d (1, n) and d (2, n-1) = d (1,
n-1). Here, assuming that a value obtained by converting log ₂ (n) to an integer by rounding up is k, by performing the above procedure k times, an n-bit Gray code is converted into a binary code.

In the gray-to-binary conversion method according to the second aspect of the present invention, the above procedure is performed only on odd bits (or even bits), and the remaining even bits (or odd bits) are obtained. From the odd bits (or even bits) . That is, when converting gray code of n bits in binary code, first, an exclusive OR of the n-2m-1 th bit G _n-2m-1 and n-2m th bit G _n-2m gray code , D (1, INT (n / 2) -m) (I
NT (n / 2) -1 ≧ m ≧ 0). Here, INT () represents truncation to an integer. Next, d (1,1) to d (1, INT (n /
2)), the exclusive OR of d (1, m) and d (1, m + 2 ⁰ ) is generated to generate d (2, m) (1 ≦ m ≦ INT (n / 2) -1). Similarly, for the output of d (2,1) to d (2, INT (n / 2) -1), d (2, m)
And an exclusive OR of d (2, m + 2 ¹ ) and d (3, m) is generated (1 ≦ m ≦ INT (n / 2) −2 ¹ ). Where d (2, INT (n / 2)) = d (1, I
NT (n / 2)). By performing the above operation k times, first, binary codes of B _n and B _{n−2m + 1} (1 ≦ m ≦ INT (n / 2)) are obtained. The remaining codes of B _n−2m (1 ≦ m ≦ UINT (n / 2) −1) are obtained by taking the exclusive OR of the determined B _{n−2m + 1} and G _n−2m. . Here, UINT () represents rounding up to an integer.

[0008]

According to the gray-to-binary conversion method of claim 1 ,
Lever, the gate delay to binary code of the least significant bit is determined in the case of n-bit Gray code, log
When ₂ integer values rounded up to (n) and k, so that requires only the gate delay of XOR k stages min.

According to the gray-binary conversion method of the present invention, only odd bits (or even bits) are obtained by the method of claim 1, and the remaining even bits (or odd bits) are obtained. Calculated by the exclusive OR of the odd bit (or even bit) and the gray code
Therefore , not only the gate delay time can be reduced to the same extent as in claim 1, but also the number of exclusive logic gates required for the gray-to-binary conversion circuit can be reduced by the method according to claim 1. It can be greatly reduced in comparison.

[0010]

FIG. 1 shows a gray-to-binary conversion method according to the first embodiment .
That Gray - shows a binary conversion circuit (n = 8-bit field
) .

[0011] As shown in the figure, the first column of the exclusive logic gates (EX1~EX7) takes the exclusive OR of the only two ^zero next to the gray code, from d (1,1) d ( 1,7) output is generated.

Next, exclusive logic gates (EX8 to EX1) in the second column
3), only 2 ^one takes an exclusive OR of the output of the next, d
An output of d (2,6) is generated from (2,1). Similarly, the third column of the exclusive logic gates (EX14~EX17), only 2 ^two XORs the output of the next to the output of the d (3, 4) from d (3, 1) It has occurred. Then, d (3,1) to d (3,4) correspond to the first to fourth bits of the final binary code, and d (2,5) and d (2,6) correspond to the binary code. 5th bit of 6
D (1,7) corresponds to the 7th bit of the binary code. Thus, the 8-bit Gray code is converted into a binary code with a delay of three stages of exclusive logic gates.

FIG. 2 shows an embodiment of the present invention when n = 10 bits. As shown in the figure, in the case of 10 bits, it can be converted into a binary code with four stages of gate delay.

As described above, in the gray-to-binary conversion method of the present embodiment, the gate delay until the binary code of the least significant bit is determined is obtained by rounding up log ₂ (n) for an n-bit Gray code. If k is an integer value,
The gate delay corresponds to k stages of exclusive OR. On the other hand, in the conventional gray-binary conversion method , in the case of an n-bit gray code, a gate delay of n-1 stages is required. Therefore, for example, when converting a 10-bit Gray code into a binary code, the conventional conversion method requires a delay of 9 gates, but the gray-binary conversion method according to the present invention requires that the delay be reduced to a 4-gate delay. Can be. Also, 16
In the case of a bit gray code, the conventional conversion method requires a delay of 15 gates, but according to the present invention, conversion can be performed with the same delay of 4 gates as in the case of 10 bits. Thus, according to the gray-binary conversion method according to the present embodiment ,
For example , the gate delay time can be reduced exponentially as compared with the conventional conversion method , and extremely high-speed gray-binary code conversion can be performed.

(Embodiment 2) In the case of n = 10 bits, the odd number bits are set as described in claim 1.
Required by law, the remaining even-numbered bits, according to claim 2, wherein obtaining an exclusive logical sum of the odd bits and a gray code obtained
FIG. 3 shows an embodiment using the above method .

As shown in FIG. 1, the exclusive logic gates (EX1 to EX5) in the first column take the exclusive OR of the odd-numbered bit gray code and the upper-order even-numbered bit gray code, and Generate d (1,5) from (1,1). The exclusive logic gates (EX6 to EX9) in the second column take the exclusive OR of the adjacent exclusive logic gates with respect to the output of the exclusive logic gate in the first column, and d (2,1) to d (2,
Generates the output of 4). Similarly, an exclusive logic gate in the third column
(EX10~EX12), only 2 ^one takes the exclusive OR of the outputs of the neighboring generates d (3,3) from d (3,1). Furthermore fourth column of the exclusive logic gates (EX13), only 2 ^two takes an exclusive logical sum of the outputs of neighboring generates d (4,1). At this point, all the odd-bit binary codes have been obtained.

The remaining even bits are obtained by taking the exclusive OR of the odd bits obtained by the exclusive logic gates EX14 to EX17 and the Gray code.

FIG. 3 shows that the maximum delay of this gray-binary conversion circuit is equivalent to four exclusive logic gates and the conversion circuit of FIG. 2, but the number of exclusive logic gates required for conversion is 17 gates. That is, the number of gates is greatly reduced with respect to 25 gates in the case of FIG.

As described above , according to this embodiment , only the odd bits (or even bits) are obtained by the method described in claim 1 , and the remaining even bits (or odd bits) are obtained by the obtained odd bits (or odd bits). 2. The method according to claim 1, wherein the value is obtained by an exclusive OR of an even bit) and a gray code.
Not only can the gate delay time be reduced to the same extent as the method described above , but also the number of exclusive logic gates required for the gray-binary conversion circuit can be significantly reduced as compared with the conversion circuit of the first embodiment. .

[0020]

As described above, when converting an n-bit Gray code into a binary code, the conventional gray code is used.
In the binary conversion method , a time delay of n-1 gates occurs. However, according to the method of claim 1 , log ₂ (n) can be suppressed to a delay of the number of stages obtained by rounding up, and an exponential function It is possible to significantly reduce the time delay.

According to the method of claim 2, only the odd bits (or even bits) are obtained by the method of claim 1 , and the remaining even bits (or odd bits) are obtained.
Is calculated by the exclusive OR of the obtained odd-numbered bits (or even-numbered bits) and the Gray code , so that the time delay can be significantly reduced while the number of exclusive logic gates is suppressed.

[Brief description of the drawings]

FIG. 1 is a gray-binary conversion circuit diagram in the case of n = 8 bits in Embodiment 1 of the present invention.

FIG. 2 is a gray-to-binary conversion circuit diagram when n = 10 bits in the first embodiment of the present invention.

FIG. 3 is a gray-binary conversion circuit diagram in the case of n = 10 bits in Embodiment 2 of the present invention.

FIG. 4 is a circuit diagram of a conventional gray-binary conversion circuit when n = 8 bits.

[Explanation of symbols]

G _n ~G ₁ gray code B _n .about.B ₁ binary code

Claims (2)

(57) [Claims] 1. For an n-bit Gray code, first,
The (n-1) exclusive gates exclusively ORs the gray code <br/> between cormorants Tonarigo, then for their output
The n-2 ¹ exclusive logic gate takes an exclusive OR of outputs of the 2 ^one next, with respect to further their output n-
Binary conversion method - 2 by ^two exclusive gates exclusively ORs the outputs of the 2 ^two neighboring gray to convert the gray code into a binary code by repeating the above method. 2. For an n-bit Gray code, first,
INT (n / 2) number of Tonarigo cormorant grayed by the exclusive logic gate
An exclusive OR between the ray code to every one of the upper (INT represents an integer of truncated), then INT for their output (n / 2) -2 ⁰ amino exclusive gate
The exclusive OR of adjacent outputs by
Nitrile, INT for their output (n / 2) -2 ¹
Number of exclusive exclusively ORs the outputs of the 2 ^one next to the logic gates in order from lower to obtain the binary code every second by repeatedly performing the above method, waited determined remaining binary code binary A gray-to-binary conversion method obtained by an exclusive OR of a code and a gray code.