JP2665934B2 - Method of manufacturing thin film transistor matrix - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A method for manufacturing a thin film transistor matrix, which aims to reduce the number of masks and the number of steps, shorten the throughput, improve the yield, and reduce the cost, The electrode termination process is divided into two steps, a polyimide etching step and a P-CVD insulating film etching step, and the polyimide etching step is performed using a mask used in a display electrode polyimide punching step in the previous step.
The structure is such that the CVD insulating film etching step is performed by a mask for protecting the display portion in the subsequent display electrode lift-off step and the display electrode material itself.

[Industrial applications]

The present invention relates to a method of manufacturing a thin film transistor matrix, and more particularly, to a method of manufacturing a thin-film transistor matrix with improved terminal extension.

[Conventional technology]

Thin Film Transistor (hereinafter, TFT)
Has recently been used heavily for driving liquid crystal display elements and the like. FIG. 4 is a diagram generally used in the related art.
FIG. 3 is a plan view showing an example of the structure of the TFT. As shown in the figure, the TFT has a source 42, a gate 43,
The drain 44 is formed in a layer with an insulating protective film 45 interposed therebetween. The gate 43 is provided with a gate bus line 46, and the drain 44 is provided with a drain bus line 47. FIG. 5 is a longitudinal sectional view taken along line AA 'of FIG. 4. As shown in FIG. 5, the gate 43 is formed directly on the substrate 51, and the gate 43 is insulated by the insulating layer 52. The display electrode 41 and the semiconductor layer 53 are formed on the insulating layer 52, and the source 42 and the drain 44 are provided on the semiconductor layer 53. The display electrode 41 and the source 42 are in contact. Its source 42 and drain 44
In between, an insulating protective film 54 is formed, an adhesion layer 55 is placed, and all of them are made of polyimide insulating protective film 45.
Is covering. However, a contact hole 56 communicates between the drain bus line 47 and the drain 44 on the insulating protective film 45.

The display electrode 41 is formed of ITO (Indium Tin Oxide), and has a charge-sharing effect by a pulse voltage applied between a source 42, a gate 43, and a drain 44 formed in a matrix. It controls the phase change.

[Problems to be solved by the invention]

In manufacturing the above-described thin film transistor, each step as shown in FIG. 6 has conventionally been employed to expose the terminal of the gate electrode. Note that the left side of the figure shows an example of the mask shape, the white portions are etched, and the gray portions are left with resist and the like. The right side of the figure shows the substrate after each step.

The first step is a photolithography step, in which ITO as a display electrode contacts a source on a substrate 61 on which a gate / P-CVD insulating film / source / drain / polyimide interlayer insulating film is formed on a glass substrate. As described above, a pattern for opening a window in the polyimide film is formed using the first mask 62. Next, as a second step, only the polyimide film is opened by dry etching, and then, as a third step, a pattern for exposing the terminal is formed by photolithography using the second mask 63. Further, as a fourth step, a polyimide film and a P-CVD insulating film (SiN) are formed by dry etching.
Is continuously removed, and then a third mask is formed as a fifth step.
A pattern for forming a display electrode by lift-off is formed by photolithography using 64. Thereafter, as a sixth step, lift-off is performed with the ITO deposit, and a drain bus is further formed, thereby completing the process.

As is clear from the above, even during this time, six steps and three masks are required, which makes the steps long and complicated, which causes a reduction in yield and an increase in cost.

The present invention has been made in view of the above problems, and provides a method of manufacturing a thin film transistor matrix that reduces the number of masks and steps, shortens throughput, improves yield, and reduces costs. The purpose is to do.

[Means for solving the problem]

In the present invention, a means for solving the above-mentioned problem is a method of manufacturing a thin film transistor matrix including a display electrode polyimide punching step, a gate electrode terminal step, and a display electrode lift-off step. -The etching process and the P-CVD insulating film etching process are divided into two stages, and the polyimide etching process is performed using the mask used in the display electrode polyimide punching process of the previous process. In this method, a method of manufacturing a thin film transistor matrix using a mask for protecting a display portion in the display electrode lift-off process and the display electrode material itself.

[Action]

The reason why the mask for exposing the gate terminal cannot be reduced is that the gate terminal must be etched up to the P-CVD insulating film, but must be left in the display unit. In the present invention, the etching process is divided into two stages, the etching of polyimide is performed using the mask pattern of the previous process, and the etching of the P-CVD insulating film uses the ITO film itself of the subsequent process as a mask. Where a P-CVD insulating film is to be etched on a substrate on which polyimide has been etched in advance, the structure is created by masking at the time of ITO deposition. After the deposition, before the conventional lift-off process, dry etching is performed so that peripheral P-
The CVD insulating film can be removed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a process chart of one embodiment of the present invention. Also,
FIG. 2 is a plan view showing an example of a thin film transistor matrix formed according to the present invention, and FIG.
It is a longitudinal cross-sectional view by -A '.

First, in FIGS. 2 and 3, reference numeral 21 denotes a glass substrate;
Is ITO, 23 is polyimide, 24 is a gate terminal, and 25 is a resist. Where the P-CVD insulating film is to be etched on the glass substrate 21 on which the polyimide 23 has been etched in advance, the structure shown in FIGS. The peripheral P-CVD insulating film can be removed by performing dry etching after the deposition and before the conventional lift-off process. This is the principle of the present invention.

To implement this principle, five steps are performed in FIG. Note that the left side of FIG. 1 shows an example of the mask shape, in which a white portion is etched and a gray portion is left with a resist or the like. The right side of the figure shows the substrate after each step.

In the first step, ITO as a display electrode is brought into contact with a source on a substrate 1 having a gate / P-CVD insulating film / source / drain / polyimide interlayer insulating film formed on a glass substrate. A window is opened in the polyimide 3 by photolithography using the first mask 2 and a pattern for removing the polyimide in the peripheral portion is formed on the resist 4.
Formed.

In the second step, polyimide 3
Only open the window and remove the polyimide on the periphery.

In the third step, a pattern for lifting off the display electrode is formed by photolithography using the second mask 5 (corresponding to a conventional third mask).

In the fourth step, when depositing the ITO 6, the ITO 6 is shielded by a metal mask 8 so that the ITO does not deposit on the peripheral portion (terminal portion of the gate) 7 of the substrate.

In a fifth step, dry etching is performed using the ITO 6 as a mask for protecting the display unit, thereby exposing the gate terminals 9. Thereafter, lift-off is performed, a drain bus line is formed, and the process ends.

According to this method, two masks are required instead of three masks in the past, and the process is also shortened. This is because the conventional gate electrode terminal extending step is divided and included in the first step and the third step.

〔The invention's effect〕

As described above, according to the present invention, there is provided a method of manufacturing a thin film transistor matrix that reduces the number of masks and steps, reduces the throughput, improves the yield, and reduces the cost compared to the related art. can do.

[Brief description of the drawings]

1 is a process drawing of one embodiment of the present invention, FIGS. 2 and 3 are plan views and longitudinal sectional views of one embodiment of the present invention, and FIGS. 4 and 5 are plan views of a conventional example. FIG. 6 is a process diagram of a conventional example. 1; substrate, 2; first mask 3; polyimide, 4; resist, 5; second mask, 6; ITO, 7; substrate periphery, 8; metal mask, 9;

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoru Kawai 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (1)

(57) [Claims] 1. A method for manufacturing a thin film transistor matrix comprising: a display electrode polyimide punching step; a gate electrode terminal step; and a display electrode lift-off step. It is divided into two stages, the film etching process, the polyimide etching process is performed by using the mask (2) used in the display electrode polyimide punching process in the previous process, and the P-CVD insulating film etching process is performed in the subsequent display electrode lift-off process. And a display electrode material itself (6) by using a mask (5) for protecting the display section and a method for manufacturing a thin film transistor matrix.