JP2666989B2 - Logic circuit delay time analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a delay time for detecting a circuit portion causing a delay time of a logic circuit of a digital system when the delay time is larger than an expected value. The present invention relates to an analyzer.

(Prior Art) In designing a logic circuit, it is necessary to satisfy not only a logical function but also a design constraint on a delay time (hereinafter, referred to as a timing constraint). Therefore, in verifying whether or not the designed logic circuit operates correctly, generally, in addition to function verification by logic simulation or the like, timing verification for verifying whether timing constraints are satisfied is also performed.

Items to be verified in the timing verification include, for example, verification of the element level such as that the setup time and hold time of the flip-flop are satisfied, and that no hazard has occurred in the clock signal. That the maximum delay time satisfies the constraint that it is less than an expected value such as a clock cycle.

Conventionally, as a method of the delay time analysis, a path enumeration method (for example, by MAWold: “Design Verification and
performance Analysis ", 15th Design Automation Confe
rence, p264-270, 1978) and methods based on PERT (for example,
RBHitchcock et al .: “Timing Analysis of Computer H
ardware ", IBM J.RES. & DEVELOP., vol.26 no.1, p100-1
05, 1982) for calculating the delay time of a combinational circuit using a delay time calculation tool. As a result, when there is a signal path whose delay time exceeds the expected value (such a signal path is referred to as a critical path below), the designer analyzes the logic on the critical path The logic circuit was modified (hereinafter referred to as timing correction) so as to be as follows.

Timing correction can typically be resolved by finding the sub-circuit that is causing the critical path and modifying the sub-circuit to operate faster.

(Problems to be Solved by the Invention) However, in the delay time analysis using such a conventional delay time calculation tool, since the partial circuit cannot be automatically detected, the designer analyzes the logic on the critical path. In particular, if there are many logic stages, it is difficult to analyze the logic on the critical path and find the partial circuit that is causing the critical path. There is a problem that time is required to correct the timing. In addition, as a conventional technique regarding such timing correction of a logic circuit,
Japanese Patent Application Laid-Open No. 1-95365 discloses a critical delay table that stores an integrated delay time value and a terminal pin number of a preceding logic element for each terminal pin of a target logic element, and then calculates a delay time. An event table that stores a terminal pin number of the logic element and a start pin number that goes back to the start point of the critical path, from the start point to the end point of the delay time calculation, the critical delay table for each of the logic elements, and A critical path analysis processing method in which delay time calculation processing is executed while rewriting the contents of an event table is disclosed.

However, since the analysis processing method of Japanese Patent Laid-Open No. 1-95365 is intended to quickly determine which path from one terminal to which terminal is a critical path with a small storage capacity, The partial circuit causing the critical path could not be extracted.

In the section of the prior art of Japanese Patent Laid-Open No. 1-95365, the delay value for each stage from the logic element at the starting point to the final logic element on the logic circuit is integrated and finally obtained. The technology that checks whether the accumulated delay value conforms to the design criteria is described, but this is only an example of the method of calculating the delay time in the critical path, and the cause of the critical path Could not be extracted.

The present invention has been made in view of the above problems,
An object of the present invention is to provide a delay time analysis device for a logic circuit, which can easily find a partial circuit causing the critical path when there is a critical path in the delay time analysis and can improve the efficiency of the logic circuit design. It is in.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention relates to a delay time analyzing apparatus provided with a delay time calculating means for obtaining a delay time of a signal path in a logic circuit. The path of the delay time calculated by the delay time calculation means is longer than the expected value, and the critical path search means for detecting the logic element to be analyzed and the logic element detected by the delay time calculation means are detected. Among them, the delay time of the signal path connected to each input terminal of the logic element having a plurality of input terminals is compared between the signal paths connected to the logic element, and if the difference is larger than a preset threshold value, the delay A comparison unit that outputs information on a logic element connected to a signal path having a longer time.

(Operation) In the delay time analysis device having the above configuration, first, the critical path search means follows a signal path whose delay time is larger than an expected value, and sequentially detects logical elements to be analyzed by the comparison means described later. I do. Next, the comparing means calculates the delay time of the signal path connected to each input terminal of the logic element having a plurality of input terminals among the logic elements existing on the signal path traced by the critical path searching means, Comparison between signal paths connected to each input terminal of the logic element,
When the difference is larger than a preset threshold value, the information of the logic element connected to the signal path having the larger delay time in the compared signal paths causes a delay in the critical path. Output as a partial circuit candidate.

In this way, by automatically detecting a partial circuit candidate that causes a critical path, the time required for timing correction can be reduced, and design efficiency can be improved.

(Embodiment) FIG. 1 is a block diagram showing a configuration of an embodiment of a logic circuit delay time analyzing apparatus according to the present invention.

As shown in the figure, this device includes a delay time calculation unit 1
A critical path search unit 2, a threshold setting unit 3,
It comprises a comparison detection section 4, a logic circuit data storage section 5, and a threshold storage section 6.

The delay time calculation unit 1 calculates the delay time of each signal line in the logic circuit data, and stores the calculation result in the logic circuit data storage unit 5.

As a result of the delay time calculation of each signal line by the delay time calculation unit 1, the critical path search unit 2 selects a signal line whose delay time is larger than an expected value, that is, a critical path, if the path exists. The logic elements are traced from the output side to the input side, sequentially detect the logic elements to be analyzed by the comparison detection unit 4 described later, and output as a search path described later.

The threshold setting unit 3 includes an input device such as a keyboard, and stores a threshold input by an operator in the threshold storage unit 6.

In the present embodiment, two thresholds are set as the thresholds stored in the threshold setting unit 3, and these two thresholds will be referred to as an OFF state threshold and an ON state threshold for convenience.

Here, the OFF-state threshold value is a threshold value used for determining a difference in delay time between input signal lines when a process of extracting a partial circuit causing a delay is started in a comparison detection unit 4 described later. In other words, the ON state threshold is a threshold that is applied after starting the process of extracting a partial circuit that causes a delay, that is, from the next logic element to which the OFF state threshold is applied. In this embodiment, OFF state threshold> ON state threshold is set.

The comparison detection unit 4 determines the delay time of the signal path connected to each input terminal of the logic element having a plurality of input terminals among the logic elements on the search path detected in the critical path search failure 2 as the logic element. Between the signal paths connected to
The difference is calculated, and the calculated difference is compared with the threshold value stored in the threshold value storage unit 6. If the difference in delay time is larger than the threshold value, the difference is connected to the input terminal of the logic element. Of the signal lines, the logic element connected to the signal line with the longer delay time is determined to be the cause of the delay, the logic element is obtained from the logic circuit data, and the element name is assigned to the partial circuit. Output as a candidate.

The logic circuit data is stored in the logic circuit data storage unit 5 in the format shown in FIGS. 3 (a) and 3 (b). The logic circuit data includes an element table and a signal table. The element table shown in FIG. 3A stores element names, element types, terminals, and names of signal lines connected to the terminals for each logical element. On the other hand, the signal table shown in FIG. 3B stores the signal line name, the element name and terminal of the source (start point of the signal line), and the element name and terminal of the destination (end point of the signal line) for each signal. Have been. The signal table also has an area for storing the calculated signal line delay time.

Next, the operation of the present embodiment will be described by taking as an example a case where the delay time analysis of the logic circuit shown in FIG. 2 is performed.

The case where the delay time analysis of the logic circuit shown in FIG. 2 is performed will be described as an example. In FIG. 2, G11 to G17 are AND gates, element G18 is a NAND gate, and element G19 is an EXOR gate.

The processing for the logic circuit data is performed as follows.

The delay time calculation unit 1 is configured such that, from the input side to the output side,
The delay time of each signal line is calculated as the delay time of the signal line connected to the output, which is the sum of the delay time of the signal line connected to the input of each logic element and the delay time of that logic element. Then, the delay time is stored in the signal table of the column data storage unit 5. Here, for the sake of simplicity, the delay time due to the capacity of the signal line and the like is ignored.

Assuming that the delay time of each logic element is given as shown in FIG. 4, the delay time of each signal line is calculated as shown in FIG.

If a critical path exists as a result of delay time calculation, the critical path search unit 2 follows the path from the output side to the input side according to the processing flow shown in FIG.

Now, the expected value of the delay time of the logic circuit shown in FIG.
Assuming that it was 20 [ns], the delay time of the output H was 23
[Ns], and since the critical path exists, the search process is started from the output H in the input direction. First,
The logic element connected to the output H signal line S24 is obtained from the logic circuit data storage unit 5 to obtain the element G16 (step ST
1).

Since the element G16 is a 2-input AND gate and the delay time of the element is 3 [ns], 20-3 = 17 [ns] is the expected value of the delay time of the signal line connected to the input side of the element G16. (Steps ST2 to ST3).

The signal lines S20 and S23 are connected to the input side of the element G16. Since the delay time of S20 is 17 [ns], which does not exceed the expected value, it does not continue. On the other hand, since the delay time of the signal line S23 is 20 [ns], which exceeds the expected value, further search processing is performed (step ST4). As the search proceeds in this way, the following two paths (hereinafter referred to as search paths) are obtained (step ST5).

Search path 1; G16 (input 2)-G19 (input 1)-G14 (input 1)-G3 (input)-G18 (input 1)-G13 (input 1)-G1
2 (input 1)-G11 (input 1)-G1 (input) Search path 2; G16 (input 2)-G19 (input 1)-G14 (input 1)-G3 (input)-G18 (input 1)-G13 (Input 1) -G1
2 (input 1) -G11 (input 1) -G7 (input 1)
When the OFF state threshold value is specified as 5 [ns] and the ON state threshold value 2 is specified as [ns], the values are stored in the threshold value storage unit 6 as shown in FIG.

The comparison detection unit 4 performs a process on each search path traced by the critical path search unit 2 according to the flowchart shown in FIG.

First, the element name “G1
6 "and a terminal" input 2 "are obtained (step ST10).

Next, the element G16 is a 2-input AND gate (the number of inputs ≧ 2) according to the logic circuit data shown in FIG. 3, and since the input of the element G16 is connected to the signal line S23, the delay of the signal line S23 is delayed. Time Dp = 20 [ns] is obtained (steps ST11 to ST12).

The signal line connected to the input system terminal other than the input 2 of the element G16 is only S20, and Dmin = 17 [ns] is obtained (step ST13). The time difference between input signal lines is Dp-Dmin =
Since 20−17 = 3 [ns], which is smaller than the OFF state threshold value 5 [ns], the search proceeds and the element name “G19” and “input 1” of the next element on the search path are obtained (step ST14, ST22, ST1
0).

The element G19 has two inputs, and the time difference is Dp−Dmin = 17
Since −6 = 11 [ns]> 5 [ns], detection processing after ST15 is started, and the next element name “G14” on the search path and “input”
1 "and outputs the element name" G14 "(steps ST11 to ST11).
17).

The element G14 has two inputs, and the time difference is Dp−Dmin = 1.
4-1 = 13, which is larger than the ON state threshold value 2 [ns] (steps ST18 to ST21). Therefore, since the number of inputs of the next element name “G3” on the search path is “1”, the next element name “G18” on the search path and the terminal “input 1” are obtained, and the element name is obtained. “G18”
Is output (steps ST18, ST15 to ST17).

By proceeding in this way, two search paths 1, 2
The following output is obtained for both of the above (parts enclosed by broken lines in FIG. 2).

G14-G3-G18-G13-G12-G11 As a result, it can be inferred that this partial circuit is the cause of the critical path, and the timing correction is performed by focusing on the broken line portion of the logic circuit shown in FIG. By doing so, for example, by modifying the logic circuit as shown in FIG. 8, it is possible to exclude the critical path.

Note that the type of threshold and the method of setting the threshold in the present invention are as follows.
It is not limited to the above embodiment. For example, in the above embodiment, two types of thresholds are set, an OFF state threshold and an ON state threshold. However, if the OFF state threshold and the ON state threshold have the same value, only one type may be set. Alternatively, only the OFF state threshold value may be set, and the ON state threshold value may be calculated by a method such as taking the difference between the OFF state threshold value and the delay time of the logic element to be processed. Further, the OFF state threshold value itself may be calculated by a method of statistically analyzing a difference in delay time between each input terminal of each logic element and each input terminal and adding a standard deviation value to an average value thereof.

In the above embodiment, the search of the critical path and the detection of the partial circuit causing the critical path are performed from the output side to the input side, but particularly when the OFF threshold and the ON threshold are the same. In advance, if the difference between the delay time of the signal line and its expected value is calculated in advance, the search is performed from the input side to the output side, and the same process as in the above embodiment is followed from the input side to the output side. You may make it detect.

Further, in the above embodiment, the element name is output when the candidate of the partial circuit causing the critical path is detected. However, this partial circuit is shown on the circuit drawing by using the logic circuit editor. You may do it.

[Effects of the Invention] As described above, according to the present invention, in the timing verification of the logic circuit, when the critical path exists, the candidate of the partial circuit that causes the critical path can be automatically detected, and the timing Correction work can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a delay time analysis device for a logic circuit according to the present invention, FIG. 2 is a view showing an example of a logic circuit for performing delay time analysis, and FIG. 3 is shown in FIG. FIG. 4 shows the logic circuit data of the logic circuit shown in FIG. 4, FIG. 4 shows the delay time of each element, FIG. 5 is a flow chart showing the procedure of the critical path search unit, and FIG. 6 shows the contents of the threshold value storage unit. FIG. 7 is a flowchart showing a processing procedure of the comparison detection unit. FIG. 8 is a logic circuit diagram showing a result of performing timing correction on a partial circuit obtained as an output result of the comparison detection unit and its respective signal lines. FIG. 12 is a diagram showing a result of calculating a delay time for the delay time. 1 delay time calculation unit 2 critical path search unit 3 threshold setting unit 4 comparison detection unit 5 logic circuit data storage unit 6 threshold storage unit

Claims (1)

(57) [Claims] 1. A delay time analyzing device comprising delay time calculating means for calculating a delay time of a signal path in a logic circuit, wherein a signal path whose delay time calculated by said delay time calculating means is larger than an expected value is traced. , A critical path search means for detecting a logic element to be analyzed, and a signal path of a signal path connected to each input terminal of a logic element having a plurality of input terminals among the logic elements detected by the critical path search means. Comparing the delay times between the signal paths connected to the logic element, and if the difference is larger than a preset threshold value, a comparing means for outputting information of the logic element connected to the signal path having the larger delay time. A delay time analysis device for a logic circuit, comprising: