JP2671066B2 - Optical coupling device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical coupling device (photocoupler), and particularly for a program controller, which is intended for stable operation of an optical coupling device which requires output delay due to chattering noise in the input. Is.

[0002]

[Prior art]

(Conventional example 1) A conventional optical coupling device (photocoupler) for a program controller delays output until an input signal becomes stable, and delays output so as to prevent a phenomenon (chattering) intermittently caused by mechanical vibration. A circuit is provided. In order to obtain this output delay, the light receiving unit is
It comprises a light receiving element (photodiode) 1, an amplifier 2, comparators 3 and 4, and a capacitor 5. In the figure, 6 is a constant current circuit, 7 is a transistor, and 8 is a negative feedback resistor. In the light receiving part, each part except the capacitor 5 is monolithically integrated.

Generally, delay time td2 for output delay
Is represented by td2 = C × Vref2 / I (1) Here, C is the capacitance of the capacitor 5, Vre
f2 is the reference voltage of the comparator 4, and I is the current of the constant current circuit 6. The delay time td2 should be reasonably long. Therefore, in order to lengthen the delay time td2, it is more advantageous to reduce I according to the equation (1), but the current obtained by the integrated circuit with high accuracy and small variation is several μA.
Is the limit.

For example, when it is desired to obtain 1 ms for td2, the reference voltage Vref2 of the comparator 4 is 2 V and I = 1 μA.
Then, the capacity C of the capacitor 5 requires 500 PF. Obtaining the capacitance of the capacitor 5 with an integrated circuit requires a large area and can hardly be integrated. Therefore, only the capacitor 5 is externally attached. Therefore, it is an obstacle to downsizing and weight reduction as an optical coupling device for a program controller.

(Prior art example 2) FIG. 4 shows a technique capable of obtaining a large delay without externally attaching a capacitor, and further reducing the size and weight.

According to this technique, as shown in FIG. 4, when the light receiving element 10 receives light and the output of the comparator 12 becomes High as the output voltage of the amplifier 11 rises, the output delay circuit 1
Reference numeral 3 denotes an exclusive OR of the output of the comparator 12 and the output of the D-FF circuit 21 as an RS type flip-flop (RS-F).
F) The logical product of the RS-FF circuit 17 obtained by the AND circuit 19 and the output from the oscillator 18 is divided by the frequency divider 20 as the set signal of the circuit 17, and the divided signal is the D-type flip-flop. (D-FF) As a clock signal for the circuit 21,
The output of the comparator 12 is used as the input signal of the D-FF circuit 21. Therefore, the output of the RS-FF circuit 17 is H
Only when it is high, the output of the oscillator 18 is guided to the frequency divider 20, and is output from the D-FF circuit 21 with a delay by that amount.

Therefore, since the output delay circuit 13 can obtain a large delay which cannot be obtained without externally attaching a capacitor in the conventional example 1, the light receiving element 10, the amplifier 11, the comparator 12 and The output delay circuit 13 can be monolithically integrated into a light receiving section, and the size and weight of the optical coupling device can be reduced.

[0008]

However, in the output delay circuit 13 of FIG. 4, as shown in FIG.
When noise is input when a clock pulse is input to the circuit 21, the output responds to the noise and malfunction occurs. FIG. 5 is a timing chart of the above operation, where I is the comparator 12, II is the exclusive OR circuit 30, III is the RS-FF circuit 17, and IV is the AND circuit 1.
9, V indicates the frequency divider 20, and VI indicates each output waveform of the D-FF circuit 21.

Therefore, the present applicant has proposed a prior art which can further improve the noise resistance.

(Prior Art) In the above-mentioned prior art, as shown in FIGS. 6 and 7, the up-count and down-count of the up-down counter 59 are switched depending on the state of the comparator 54, that is, the output of the comparator 54 is H, for example.
The noise resistance is further improved by counting down when noise enters in the high state and counting up when returning to the normal output High.

That is, the output delay circuit 55 shown in FIG.
Becomes the light receiving state of the light receiving element 50, and when the output of the amplifier 52> the output of the amplifier 53, the output A of the comparator 54 becomes High (I portion of the output A in FIG. 7).
In this state, the output J of the D-FF circuit 60 that synchronizes the output A of the comparator 54 with the clock signal of the up / down counter 59 by using the output of the oscillator 58 as a clock signal is H.
Since it is high, the exclusive OR of the exclusive OR circuit 63
The output of the circuit 79 becomes High, and the output F of the NOT circuit 80 becomes Low. At this time, the output H of the RS-FF circuit 64
Becomes High, and the output state of the up / down counter 59 is (0,
0,0) → (0,0,1) → (0,1,0)
The up-down counter 59 is in the up-counting state. Here, if noise such as II is present in the output A of the comparator 54, the outputs A and J become Low, so the up-down counter 59 counts down, but no noise waveform is output from the up-down counter 59. . When the noise disappears, the output J becomes High, and the up / down counter 59 returns to up counting.

When the output state of the up / down counter 59 becomes (1, 1, 1), the decoder circuit 61
The output C of the NAND circuit 69 becomes low and RS-F
The output E of the F circuit 101 becomes High, where RS-
The delay time 1 shown in the waveform of the output E of the FF circuit 101 is generated. At the moment when the output E becomes High, the discrimination circuit 62
Li set signal shown in a of the output G is RS-FF circuit 64
And the output H of the RS-FF circuit 64 becomes Low. Therefore, the supply of the clock signal to the up / down counter 59 is stopped, and the up / down counter 59 holds the state of (1, 1, 1).

Next, when there is no light, the amplifier 52
Output goes low, and the output A of the comparator 54 goes low. At this time, since the output J is Low and the output E is High, the exclusive OR circuit 79 of the exclusive OR circuit 63 is used.
Is high, the output F of the NOT circuit 80 is low, the set signal is transmitted to the RS-FF circuit 64, and the output I of the gate circuit 67 is high. Therefore, the clock signal is supplied to the up / down counter 59. Since the output J is Low, the up / down counter 59 counts down and the output of each bit of the up / down counter 59 is (1, 1, 1) →
It changes from (1,1,0) to (1,0,1). here,
As shown in Fig. 7, when there is noise such as V, the output J becomes H
It becomes high, and only this time it will count up,
No noise waveform is output from the up / down counter 59.

When the noise disappears, the state of the output J becomes Low, and the up / down counter 59 returns to the down count. When the output state of the up-down counter 59 becomes (0, 0, 0), the output D of the OR circuit 70 is Low, the output E goes Low the RS-FF circuit 101, where the output of the RS-FF circuit 101 The delay time 2 shown in the waveform of E is generated. Moment when the output E becomes Low, Li set signal b at the output G of the discrimination circuit 62 is RS-
The output H of the RS-FF circuit 64 is transmitted to the FF circuit 64.
Goes Low, the supply of the clock signal to the up-down counter 59 is stopped, the up-down counter 59 that holds the state of the (0,0,0).

As described above, the count time is extended by the amount of noise that has entered the comparator, but since the output is performed according to the output of the up / down counter, malfunctions due to noise that entered the comparator are eliminated.

In FIG. 6, reference numeral 51 designates a light-shielding light-receiving element,
Reference numerals 65 and 66 are D-FF circuits.

However, in the above-mentioned output delay circuit 55 of the prior art, the clock signal control circuit section 90 of the up / down counter 59 uses the RS-FF circuit 64, so that the circuit becomes complicated and the circuit is integrated. if you did this,
The chip size is increased and the chip cost is increased.

Further, the RS-FF circuit 64 has a characteristic that if the clock signal control circuit section 90 malfunctions due to radiation noise or the like entering the output E of the RS-FF circuit 101 on the decoder circuit 61 side, the RS-FF circuit 64 holds it. Therefore, there is a problem in the stability of the operation such as a malfunction of the entire circuit.

In view of the above, it is an object of the present invention to provide an optical coupling device which can reduce the chip size and the chip cost when the output delay circuit is integrated and can stably operate the entire light receiving circuit.

[0020]

The means for solving the problems according to claim 1 of the present invention is issued from the light emitting portion as shown in FIGS.
The optical signal is converted into an electric signal by the light receiving unit and output, and the light receiving unit converts the optical signal from the light emitting unit into an electric signal.
For receiving the light receiving elements 50 and 51 and amplifying the electric signal
Amplifiers 52 and 53 for output and the outputs of the amplifiers 52 and 53
Converts force into a high or low level digital signal
And a comparator 54 for delaying the digital signal
And an output delay circuit 55 for controlling the output of the oscillator 58. The output delay circuit 55 inputs an oscillator 58 and a signal obtained by dividing the output of the oscillator 58 as a clock signal, and inputs the input signal.
In the optical coupling device for switching <br/> the up-count and Daunkau down bets of the up-down counter 59 by a up-down counter 59 for counting the output of the comparator 54 based on the item, the output delay circuit 5
5. When the up / down counter 59 is full count
NAND circuit 69 that outputs a low level to
The OR circuit 70 that outputs a low level when the
A decoder circuit 100 which is made, the decoder circuit 100
RS flip-flop (RS-FF) circuit 101 that uses the outputs of the NAND circuit 69 and the OR circuit 70 as a set signal and a reset signal, and the RS-FF circuit 101.
Of the decoder circuit 100 and the exclusive OR circuit 102 that takes the exclusive OR of the output of
An AND circuit 103 for taking a logical product of the outputs of the NAND circuit 69 and OR circuit 70, after taking the logical sum of the output of the output of the exclusive-OR circuit 102 the AND circuit 103
Provided an OR circuit 104 of the stage, the subsequent OR circuit 1
The output of 04 controls the clock signal of the up / down counter 59, and the output of the RS-FF circuit 101.
Is the output of the light receiving section .

Further, the problem solving means according to claim 2 is the output delay circuit 55 according to claim 1, wherein the output of the comparator 54 and the clock signal of the up / down counter 59 are provided between the comparator 54 and the up / down counter 59. A D-FF circuit 60 for synchronizing the
NAND circuit 69 and OR circuit of decoder circuit 100
Between 70 and RS-FF circuit 101, the NAND times
Two DFs for synchronizing the output of the path 69 and the output of the OR circuit 70 with the clock signal of the up / down counter 59.
The F circuits 105 and 106 are provided, and the D-FF circuit 6 is provided.
0, 105, and 106 are configured to read and output data when the clock signal of the up / down counter 59 is neither rising nor falling.

[0022]

In the above means for solving problems, when the light receiving element 50 receives light, the output A of the comparator 54 becomes High. Then, the output E of the RS-FF circuit 101 is Lo.
w, since the output B of the D-FF circuit 60 is High,
The output O of the exclusive OR circuit 102 becomes High. At this time, the output K of the OR circuit 104 becomes High, the clock signal is sent to the up / down counter 59, and the up / down counter 59 enters the up-count state. If noise enters the output A of the comparator 54, D-
Output B of FF circuit 60 and output E of RS-FF circuit 101
Are low, the output O of the exclusive OR circuit 102 is low. However, N of the decoder circuit 100
The output F of the D-FF circuit 105, which receives the outputs C and D of the AND circuit 69 and the OR circuit 70, and the D-FF circuit 10.
Since the output G of 6 remains High, the output H of the AND circuit 103 becomes High. Therefore, the OR circuit 1
The output K of 04 also becomes High, and the clock signal of the up / down counter 59 continues to be sent. Where DF
Since the output B of the F circuit 60 is Low, the up / down counter 59 is in the down count state, but the output from the up / down counter 59 to the RS-FF circuit 10 is reduced.
No noise waveform is output to the output E of 1.

Next, when the noise disappears and the output A of the comparator 54 returns to High, the same operation as above is performed,
The output K of the OR circuit 104 also becomes High, and the up / down counter 59 enters the up-count state. Then, when the count number of the up-down counter 59 reaches the full count, the output F of the D-FF circuit 105 is Low, D
-The output G of the FF circuit 106 is High and RS-F
The output E of the F circuit 101 becomes High and sends a delay signal to the program controller.

At this time, the output B of the D-FF circuit 60 is H
Since the output E of the RS-FF circuit 101 is High, the output O of the exclusive OR circuit 102 is Low .
Since the output F of the D-FF circuit 105 is also Low, the output H of the AND circuit 103 is Low and the output K of the OR circuit 104 is Low. At this time, since the clock signal is not supplied to the up-down counter 59, the state of the full count is maintained.

Since the clock signal of the up / down counter 59 can be controlled by the output of the OR circuit 104, the RS-FF is provided in the clock signal control unit of the up / down counter 59 as in the optical coupling device of FIG. If the circuit is not used, and the output delay circuit 55 is integrated, the chip size is reduced and the chip cost is reduced.

[0026] In addition, the up-down counter 59 performs the information uptake on the falling of the clock, performs the count output at the rising edge of the clock pulse, the up-count / Daunkau down executive switched at the rising edge of the clock pulse of If you have cracks, or up-down counter 59 is made to up-count, an unstable state does not know what will Daunkau down door. Therefore, the D-FF circuit 60
In synchronization with the clock signal of the up-down counter 59 convey the output state of the comparator 54 to the up-down counter 59, to switch the up-count / Daunkau down bets of the up-down counter 59 in a stable period of the up-down counter 59 .

Further, since the up / down counter 59 outputs the count data at the rising edge of the clock pulse, unless the control of the clock pulse is delayed by a predetermined clock pulse, the up / down counter 59 becomes zero count or full count. The clock pulse stops, and the D-FF circuit 60 immediately after the up-down counter 59 reaches the full count or the zero count.
Change of the output cannot be input to the up / down counter 59,
The operation of the up / down counter 59 becomes unstable. Therefore, the D-FF circuits 105 and 106 are connected to the decoder circuit 10
Outputs C and D of 0 NAND circuit 69 and OR circuit 70
Is synchronized with the clock signal of the up / down counter 59, and clock pulse control for delaying by a predetermined clock pulse is performed.

Therefore, the up / down counter 59
Will read and output the data when the clock signal of the up / down counter 59 is neither rising nor falling.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. 1 is a circuit block diagram showing a light receiving portion of an optical coupling device according to an embodiment of the present invention, and FIG. 2 is a timing chart thereof. The same functional components as those of the prior art shown in FIG. 6 are designated by the same reference numerals.

Optical coupling device (photocoupler) of this embodiment
1 has a light emitting unit and a light receiving unit in the same package, an input signal is once converted into light by the light emitting unit, and this light is converted into an electric signal again by the light receiving unit and output. The light receiving unit is a light receiving element (photodiode) 50, 5
1, an amplifier 52, 53, a comparator 54 and an output delay circuit 55 are monolithically integrated.

(Structure of Input Stage of Light-Receiving Section) The input stage of the light-receiving section is similar to that of the prior art shown in FIG.
51, amplifiers 52 and 53, and a comparator 54. The photodiode 51 is shielded from light by a metal or the like. In the figure, 56 and 57 are negative feedback resistors.

(Structure of Output Delay Circuit) The output delay circuit 55 includes an oscillator 58 and a dividing D-type flip-flop (D-FF) for dividing the output of the oscillator 58.
A frequency divider 110 including circuits 110a and 110b, an up / down counter 59 that counts the pulse period of the oscillator 58 divided by the frequency divider 110, and an output of the comparator 54 as a clock signal of the up / down counter 59. A low level when the D-FF circuit 60 for synchronizing and the up / down counter 59 are full count
When the NAND circuit 69 that outputs
A decoder circuit 100 including an OR circuit 70 that outputs a low level to the NAND circuit 6 and the NAND circuit 6 of the decoder circuit 100.
9 and the output of the OR circuit 70 up and down counter 5
Two D-FF circuits 105 and 106 for synchronizing with the clock signal of No. 9 and an RS type flip-flop (RS -FF) circuit 101
And an exclusive OR circuit 10 that takes the exclusive OR of the output of the RS-FF circuit 101 and the output of the D-FF circuit 60.
2, the output of the D-FF circuit 105 and the D-FF circuit 1
An AND circuit 103 for taking a logical product of the output of 06, the A
An OR circuit 104 for ORing the output of the ND circuit 103 and the output of the exclusive OR circuit 102, and the D-
A NAND circuit 111 for giving a clock signal synchronized with the clock signal of the up / down counter 59 to the FF circuit 60 and the D-FF circuits 105 and 106, and a NAND circuit 112 for controlling the clock signal of the up / down counter 59. It consists of

Reference numeral 68 is an initial reset circuit for making the count number of the up / down counter 59 zero when the power source Vcc is turned on, and 113 is an inverter.

(Operation of Output Delay Circuit) The operation of the output delay circuit 55 will be described with reference to the timing chart shown in FIG.

The waveform A output from the comparator 54 is classified into periods I to III according to the movement of the waveform. Further, when the power supply Vcc is turned on, the output of the up / down count 59 becomes zero count by the initial reset circuit 68. Here, up / down count 5
The output of each bit of 9 is represented by a, b, and c.

The photodiode 50 enters the light receiving state,
When the output of the amplifier 52> the output of the amplifier 53, the output A of the comparator 54 becomes High (I portion of the output A in FIG. 2).

The output E of the RS-FF circuit 101 is Low.
Since the output A of the comparator 54, that is, the output B of the D-FF circuit 60 that synchronizes the output of the comparator 54 with the clock signal of the up / down counter 59 is High, the output O of the exclusive OR circuit 102 is High. . At this time, the output K of the OR circuit 104 becomes High, the clock signal is sent to the up / down counter 59, and the up / down counter 59 enters the up-count state.

When noise enters the II portion of the output A of the comparator 54, the output B of the D-FF circuit 60 and RS
Since both outputs E of the FF circuit 101 are Low,
The output O of the exclusive OR circuit 102 becomes Low.

However, the output F of the D-FF circuit 105 that receives the output C of the NAND circuit 69 of the decoder circuit 100 and the output G of the D-FF circuit 106 that receives the output D of the OR circuit 70 are High. Since it is maintained, DF
The output H of the AND circuit 103 that takes the logical product of the output F of the F circuit 105 and the output G of the D-FF circuit 106 becomes High. Therefore, the output K of the OR circuit 104 also becomes High, and the clock signal of the up / down counter 59 continues to be sent.

The output B of the D-FF circuit 60 is Lo.
Since it is w, the up-down counter 59 is in the down-count state, but no noise waveform is output to the output E of the RS-FF circuit 101, and the output does not malfunction.

Next, the output A of the comparator 54, Chi Sunawa <br/>, the output B of the D-FF circuit 60 becomes High (in FIG. 2, period III of the output A), the exclusive OR circuit 102 Output O of the OR circuit becomes High, and the output K of the OR circuit 104 also becomes H.
The clock signal of the up / down counter 59 continues to be sent.

When the count number of the up / down counter 59 is full count, that is, when the output (a, b, c) of the up / down counter 59 becomes (1, 1, 1), NA is obtained.
The output C of the ND circuit 69, that is, the output F of the D-FF circuit 105 is Low, and the output D of the OR circuit 70, that is, D-.
The output G of the FF circuit 106 is High, and RS-FF
The output E of the circuit 101 becomes High. At this time, D-
The output B of the FF circuit 60 is High, and the RS-FF circuit 10
Since the output E of 1 is High, the exclusive OR circuit 10
The output O of 2 is Low, and the output F of the D-FF circuit 105 is
Is also Low, the output H of the AND circuit 103 is also Lo.
w, and the output K of the OR circuit 104 becomes Low. At this time, since the between <br/> the OR circuit 104 and the up-down counter 59 is N the AND circuit 112, thereby sending a clock signal to the up-down counter 59 is stopped, the up-down counter 59 is the full count Hold the state.

In this way, the output delay circuit 55 is connected to the output A of the comparator 54 and the NAND circuit of the decoder circuit 100.
The output E of the RS-FF circuit 101 in which the outputs C and D of the path 69 and the OR circuit 70 are set and reset signals.
An exclusive OR circuit 102 that takes an exclusive OR with the NAND circuit 69 and the OR circuit 70 of the decoder circuit 100.
Output C, an AND circuit 103 for ANDing and D, the output H of the output O and the AND circuit 103 of the exclusive OR circuit 102
And an OR circuit 104 that takes the logical sum of
By controlling the clock signal of the up / down counter 59 by the output K of 04, the output E of the RS-FF circuit 101 is supplied to the clock signal control unit of the up / down counter 59 as in the optical coupling device of FIG. It is not necessary to use an RS-FF circuit that holds the radiated noise that has entered, and when the output delay circuit 55 is integrated, the chip size is reduced and the chip cost is reduced.

As described above, the clock signal of the up / down counter 59 can be stopped when the up / down count number reaches a predetermined number (zero count or full count). Even if noise such as that shown by II in the timing chart is entered, output malfunction does not occur because the count number of the up / down counter 59 is decreased by 2 and thus output malfunction can be prevented.

Here, the output A of the comparator 54 and the NAND circuit 69 of the decoder circuit 100 and the outputs C and D of the OR circuit 70 are synchronized with the clock signal of the up / down counter 59, and the D-FF circuit 60. The decoder circuit 100 receives the clock signal of the down counter 59.
The output C of the NAND circuit 69 and OR circuit 70, the operation of the two D-FF circuits 105 and 106 is synchronized to D will be described.

The up / down counter 59 is, for example, U /
Performs incorporation of information D terminals at the fall of the clock, when performing the count output at the rising edge of the clock pulse, if the switching of the up-count and Daunkau down bets is performed at the rising edge of the clock pulse, the up-down counter 59 is either count up, an unstable state does not know what goes down <br/> count down the door. In order to avoid such a state, the D-FF circuit 60 synchronizes with the clock signal of the up / down counter 59 of the output A of the comparator 54 and synchronizes with the up / down counter 59.
To convey, the P output I of the NAND circuit 112 shown in FIG. 2
To perform the switching between up-counting and Daunkau down preparative range, i.e. to perform switching of the up-count / Daunkau down bets of the up-down counter 59 in a stable period of the up-down counter 59.

As described above, the up / down counter 5
Since 9 outputs the count data at the rising edge of the clock pulse, the clock pulse is stopped as soon as the up / down counter 59 reaches zero count or full count, so that the operation of the up / down counter 59 is unstable. To deal with this, the D-FF circuits 105 and 106
Of the NAND circuit 69 and the OR circuit 70 of the decoder circuit 100 based on the clock signal of the up / down counter 59 .
The outputs C and D are synchronized, and the NAND circuit 69 and the OR circuit 7
The output state of 0 is transmitted in the range of P of the output I of the NAND circuit 112 shown in FIG. That is, the control of the clock pulse is controlled by the D-FF circuits 105 and 106 to 1 /.
The output operation of the up / down counter 59 is stabilized by delaying by 4 clock pulses.

As described above, in order to synchronize the output A of the comparator 54 with the clock signal of the up / down counter 59, the D-FF circuit 60 is inserted between the comparator 54 and the up / down counter 59, and in addition, a decoder is provided. Circuit 100 (NAND circuit 69, OR circuit 70) and R
Between the S-FF circuit 101 and the up-down counter 5
NAND circuit of the decoder circuit 100 for the clock signal of 9
69 and two D-FF circuits 105 and 106 for synchronizing the outputs C and D of the OR circuit 70 are inserted, whereby the D-FF circuit 60 and the D-FF circuit 10 are inserted.
Reference numerals 5 and 106 can read and output data when the clock signal of the up / down counter 59 is neither rising nor falling, and thus a light receiving circuit having a stable output delay function can be configured.

It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many modifications and changes can be made to the above-described embodiment within the scope of the present invention.

[0050]

As is apparent from the above description, according to the first aspect of the present invention, the clock signal of the up / down counter can be controlled by the output of the OR circuit. Therefore, the RS type flip-flop is provided in the clock signal control circuit section of the up / down counter. Since the output delay function can be provided by controlling the clock signal of the up / down counter without using a delay circuit, the chip size and chip cost can be reduced when the output delay circuit is integrated. it can.

According to a second aspect of the present invention, the D-type flip-flop circuit on the side of the comparator and the two D-type flip-flop circuits on the side of the decoder circuit determine whether the clock signal of the up-down counter rises or falls. When it is not, the up / down counter reads and outputs data, so that the operation of the up / down counter is stable and the light receiving circuit can be stably operated.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a light receiving portion of an optical coupling device according to an embodiment of the present invention.

FIG. 2 is a timing chart of the same.

FIG. 3 is a circuit diagram showing a light receiving portion of an optical coupling device according to Conventional Example 1.

FIG. 4 is a circuit block diagram showing a light receiving portion of an optical coupling device according to a second conventional example.

FIG. 5 is a timing chart of the same.

FIG. 6 is a circuit block diagram showing a light receiving portion of an optical coupling device according to a prior art.

FIG. 7 is a timing chart of the same.

[Explanation of symbols]

 50,51 Light receiving element 52,53 Amplifier 54 Comparator 55 Output delay circuit 58 Oscillator 59 Up / down counter 60 D-FF circuit 69 NAND circuit 70 OR circuit 100 Decoder circuit 101 RS-FF circuit 102 Exclusive OR circuit 103 AND circuit 104 OR Circuit 105, 106 D-FF circuit

Claims (2)

(57) [Claims] 1. A light receiving section for converting an optical signal emitted from the light emitting section into an electric signal and outputting the electric signal.
Photoreceptor for converting the optical signal from the light emitting part to an electrical signal
Child, an amplifier for amplifying the electric signal, and the amplifier
Converts the output to a high or low level digital signal
And a comparator for delaying the digital signal.
And an output delay circuit for controlling the output of the oscillator. The output delay circuit inputs an oscillator and a signal obtained by dividing the output of the oscillator as a clock signal, and counts up based on the input signal. and a down-counter, the optical coupling device for switching between up-counting and Daunkau down bets of the up-down counter by the output of the comparator, the output delay circuit, the up-down counter is full
A NAND circuit that outputs a low level when counting
OR times to output low level at zero count
Circuit constituted by a channel and the NA of the decoder circuit
RS-type flip-flop circuit using outputs of ND circuit and OR circuit as set signal and reset signal, and RS
OR circuit for taking the exclusive OR of the output of the flip-flop circuit and the output of the comparator, an AND circuit for taking the logical product of the outputs of the NAND circuit and the OR circuit of the decoder circuit , and wherein the output AN
An OR circuit in the subsequent stage is provided for taking a logical sum of the output of D circuit controls the clock signal of the up-down counter by the output of the OR circuit of the subsequent stage, the RS-type flip
An optical coupling device , wherein the output of the flip-flop circuit is the output of the light receiving section . 2. The output delay circuit according to claim 1,
A D-type flip-flop circuit for synchronizing the output of the comparator and the clock signal of the up / down counter is provided between the comparator and the up / down counter, and the NAND circuit and OR circuit of the decoder circuit and RS are provided.
Type flip-flop circuit and the NAND circuit or
And two D-type flip-flop circuits for synchronizing the output of the OR circuit with the clock signal of the up / down counter. The D-type flip-flop circuit is provided when the clock signal of the up / down counter rises and falls. An optical coupling device characterized in that it is configured to read and output data when neither is the case.