JP2680025B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a memory array configuration method capable of reading signals from a memory array at high speed.

[Conventional technology]

As the memory capacity increases, the number of data lines connected to the input / output lines for reading information from the memory array increases. Therefore, the load capacity of the input / output line increases, and the read operation becomes slow. In SRAM, as a measure against this, there is a method of dividing the input / output line into a plurality of lines as described in Japanese Patent No. 1185869.

FIG. 2A shows an example in which this method is applied to DRAM. In the figure, the memory array MA includes a 2h pair of data lines (D ₁ , ▲ ▼ to D _2n , ▲ ▼ _2n ), a plurality of word lines W (only one is shown in the figure for simplification of the drawing), and data lines. And a plurality of memory cells MC arranged at the intersection of the word line and the word line. The memory cell is composed of one transistor and one capacitor. Further, each data line pair is connected with a sense amplifier SA for amplifying the signal read to the data line and connection switches SW _{1 to} SW _2n for connecting the data line and the input lines IO _a , ▲ ▼, IO _b , ▲ ▼. There is. The input / output line is divided into a plurality of sub input / output lines to reduce the parasitic capacitance. The figure shows the case of two divisions. Connection switch is controlled by an output line YS ₁ ~YS _2n of Y-decoder YD. The sub input / output line is connected to the data output amplifiers AMP _a and AMP _b outside the memory array, and its output terminal is connected to the output buffer circuit DOB through the common output line MO. The data output amplifier is configured as described in Japanese Patent No. 1185869, and is selectively operated by an address signal. XD is an X decoder for selecting the word line W.

Next, the operation of this memory array will be described. When the memory is on standby, the data line pair is charged to a predetermined potential. When the memory is in operation, the word line is selected by the X decoder. Here, if the word line W is selected, a potential change occurs in the data lines D ₁ and D _2n . On the other hand, the potentials of the paired data lines ▲ ▼ and D _2n do not change. Therefore, a minute potential difference is generated between the paired data lines according to the information stored in the memory cell. This potential difference is
Then, it is amplified by the sense amplifier SA. After that, one of the output lines becomes High level by the Y decoder YD. Here, if YS ₁ goes high, D ₁ , ▲
Information of ▼ is read to the sub input / output line IO _b , ▲ ▼. This information is amplified by the decoder output amplifier AMP _b and read out to the output buffer circuit DOB through the common output line MO. Here, the data output amplifier AMP _a connected to the sub input / output line IO _a , ▲ ▼ that is not connected to the data line is inoperative. That is, operation AMP _b If Yotsute the YD, YS ₁ ~ _n are selected, AMPA to operate if the YS _n + ₁ ~ _2n is selected. As described above, the memory is operated at high speed by dividing the input / output line.

[Problems to be solved by the invention]

In DRAM, the memory cell capacity is reduced as the memory is highly integrated, and the read signal to the data line is reduced.
As a countermeasure against this, a so-called multi-divided data line circuit system, which is described in Japanese Patent Laid-Open No. 57-198592, divides a data line into a plurality of lines. In the prior art, no consideration was given to division of input / output lines and arrangement of data output amplifiers when the multi-division circuit system is used.

Japanese Patent Laid-Open No. 59-129983 discloses another semiconductor memory device using the multi-divided data line circuit system.

FIG. 2B shows a DR using the multi-division data line circuit method.
It is a chip configuration example when the conventional input / output line division method is simply used for AM. The memory array is located in the center of the chip, and the peripheral circuits that control the memory array are located above and below. In the figure, the data lines are arranged in the horizontal direction, divided into four, and A ₁ ~
It is a subarray of A ₄ . Each sub-array is composed of the data line pair DP, the word line W and the memory cells MC provided at the intersections thereof, as in FIG. 2A, and the connection switch SW between the data line pair DP and the input / output line pair. The input / output line pair is IP _a ,
Divided by IP _b, the data line above the subarray is IP
_{At a} , the bottom data line of the subarray is connected to IP _b .
The connection switch SW is Y that is commonly provided for multiple sub-arrays.
It is controlled by the output line YS of the decoder YD. Each sub input / output line is connected to the data output amplifier AMP arranged between the sub arrays, and its output terminal is connected to the common output line MO. MO is the output buffer circuit DO located at the top of the chip.
Connected to B. The operation of this memory is shown in FIG.
Is the same as

As shown in FIG. 2 (b), by disposing the AMP between the sub arrays, the AMP can be arranged in the immediate vicinity of the sub input / output line. For this reason, the wiring that connects the AMP and the sub input / output line becomes very short, and the signal delay caused by it can be ignored. Therefore, the information from the memory array can be read at high speed. However, by arranging the data output amplifiers which are irregular and have a relatively low layout density between the subarrays in which the regular repeating patterns are laid out at a high density, an area where the circuit layout is not used is created between the subarrays. This causes a problem that the chip size increases.

FIG. 2 (C) shows a DRAM using a multi-division data line circuit system.
Another chip configuration example in which the input / output line division method is applied to.
Place the data output amplifier on top of the chip outside the memory array,
The point that they are collectively arranged is different from that shown in FIG. By arranging the data output amplifiers outside the memory array in this manner, the inside of the memory array can be laid out at a high density. In addition, since the degree of freedom of layout is relatively large outside the memory array, the layout can be performed without waste, and the chip size does not increase. However, on the other hand, sub-I / O line IP
_{As shown in b} , in the sub input / output line under the sub array, the wiring to the data output amplifier becomes long, and the parasitic resistance and parasitic capacitance increase. The sub input / output line is driven by a sense amplifier (not shown) through the connection switch SW. Normally, in order to reduce the layout size, the connection switch SW and the sense amplifier are MOSFETs with a small gate width.
Composed of. Therefore, the driving capability is small, and if the parasitic resistance and the parasitic capacitance of the sub input / output line increase, the read operation from the memory array becomes slow. Therefore, when the operation of the whole memory becomes slow, a problem occurs.

Object of the present invention, DARM using multi-divided data line circuit system
In order to provide a high-integration and high-speed semiconductor memory device by reducing the above-mentioned increase in chip size and delay in memory operation.

[Means for solving the problem]

The above object is achieved by dividing the output data amplifier group provided in each of the divided sub-input / output lines into two sets and disposing them in the immediate vicinity of both sides of the memory array so as to sandwich the memory array.

[Action]

Placing the data output amplifiers outside the memory array increases the degree of integration within the memory array. Further, since the degree of freedom in layout is high outside the memory array, the data output amplifier can be laid out without waste. Therefore, the chip size does not increase.

Further, by arranging the data output amplifiers on both sides outside the memory array, the sub input / output line and the data output amplifier can be connected with the shortest wiring. As a result, the parasitic resistance and parasitic capacitance of the wiring from the sub input / output line to the data output amplifier are reduced, and the reading of information from the memory array becomes faster.

Therefore, high-speed memory operation can be performed without increasing the chip size.

〔Example〕

 Hereinafter, the present invention will be described with reference to examples.

FIG. 1 shows a first embodiment of the present invention. FIG.
A memory array is placed in the center of the chip CHIP, and data output amplifiers AMP are placed above and below it. Peripheral circuits PRC1 and PRC2 that control the memory array are arranged further outside the AMP. The output buffer circuit DOB is arranged on the upper side of the chip. In the memory array, the data lines are divided into _four subarrays A _{1 to} A ₄ and the word lines W are selected by X.
It is composed of a decoder XD and a Y decoder YD. Each sub-array is composed of a plurality of data line pairs DP, a plurality of word lines W (only one is shown in the figure for simplification of the drawing), and a plurality of memory cells MC arranged at the intersections of the data line pairs and the word lines. ing. The memory cell is one transistor and one capacitor
Composed of individual pieces. The data line pair DP is connected to the input / output line via the connection switch SW controlled by the output line YS of the Y decoder YD. The output line is divided into two sub-output line of the IP _a and IP _b. Subarrays overlying data line pair is connected to the IP _a, IP _a is connected to the data output amplifier AMP disposed in chip top. Moreover, the subarray lower data line pair is connected to the IP _b, IP _b is connected to the data output amplifier AMP disposed below the chip. The output terminal of each data output amplifier AMP is connected to the common output line MO, and MO is connected to the output buffer circuit DOB.

Next, the operation will be described. When the memory is in the standby state, the data line pair DP is charged to a predetermined potential. When the memory is in the operating state, the X decoder selects the word line W, and a minute potential difference occurs in the data line according to the information stored in the memory cell MC. After amplifying this with a sense amplifier (not shown for simplification of the drawing), output line YS of Y decoder YD
Becomes Hihg, and the information of the data line is read to the data output amplifier AMP through the sub input / output line. For example, Yotsute the YD, the subarrays bottom of Y-decoder output line is selected, through the sub output line IP _b, information on the data line is read out to the chip bottom of the data output amplifier AMP. At this time, the data output amplifier on the upper part of the chip is inactive. Further, only one data output amplifier under the chip operates selectively according to the address signal. The output of the data output amplifier is output via the common output line MO to the output buffer circuit DO.
Read to B.

By arranging the data output amplifiers above and below the memory array in this way, the wiring length that connects the sub input / output lines and the data output amplifiers can be shortened, parasitic resistance and parasitic capacitance can be reduced, and information from the memory array can be reduced. Can be read at high speed. For example, as shown in FIG. 1, when the input / output line is divided into two, each sub input / output line can be directly connected to the data output amplifier, so that there is no influence of the wiring between the sub input line and the data output amplifier. . on the other hand,
The wiring length of the common output line MO becomes long. However, since the input stage of the output buffer circuit DOB is usually composed of a small MOSFET, the MO load capacitance is small. Further, since the MO is driven by the AMP having a large driving capability, even if the MO wiring becomes long, the signal delay due to this is small. Therefore, the entire memory can be operated at high speed. By the way, when the Y decoder selects a pair of data lines for each divided input / output line, a plurality of pieces of information can be read from the memory array at once. Therefore, this configuration can easily make a memory with multiple bit outputs.

In this embodiment, the X decoder XD and the Y decoder
An example of arranging YD around the sub array was shown, but XD, Y
Even if D is arranged in the center of the subarray, the same effect can be obtained.

FIG. 3 shows a second embodiment of the present invention. The present embodiment is an example of the chip configuration in the case of considering a so-called parallel test in which a plurality of bits are simultaneously tested. Similar sub-array 8 in the first embodiment and (A ₁ to A _8), by the four X decoder XD and a Y decoder YD, constitute a memory array. Since each sub array has the X decoder XD arranged at the center, it is divided into two vertically. Memory cell,
Lead wires, sense amplifiers, connection switches, etc. are omitted for simplification of the drawing. The input / output line pair is divided into upper and lower parts and connected to orthogonal auxiliary wirings at the center of each sub input / output line pair. For example, the sub input / output line IP ₁ is connected to the auxiliary wiring SI ₁ . SI ₁ and IP ₁ are formed by different conductive layers at the intersection, and the connection is formed by a contact hole. The auxiliary wiring is connected to the data output amplifier AMP arranged on the left and right sides of the memory array. The output of AMP is input to the switching switch CSW composed of CMOS logic gates. In the CSW, the output of the AMP is supplied by the test signal TE to the common output line MO and the test output buffer circuit TOB provided for each AMP.
Switch to. MO is connected to the output buffer circuit DOB located on the top of the chip. On the other hand, the output of each TOB is connected to the test pads TP _{1 to} TP ₈ arranged nearby.

Next, this operation will be described. During normal 1-bit reading, the test signal TE is 0V. At this time, the test output buffer TOB is always deselected by the switching switch CSW and does not operate. In this case, the circuit operation is exactly the same as that of the first embodiment, and the information of the selected one data output amplifier AMP is read out to the outside through the MO and the output buffer. On the other hand, during parallel test, TE is the power supply voltage V Then, the outputs of all data output amplifiers AMP are input to the individually provided test output buffer TOB. The output of TOB is
A plurality of (here, eight) pieces of information are read out at a time via the test pads TP _{1 to} TP ₈ provided in the vicinity.

As shown in this embodiment, by connecting to the data output amplifier at the center of the sub I / O line, the parasitic resistance of the sub I / O line itself can be reduced to about 1/2, so that reading from the memory array can be made even more advanced. Can be done. Even when performing a parallel test, the output from the data output amplifier is output by the test output buffer circuit TOB and the test pads TP _{1 to} TP ₈ provided in the vicinity thereof, so that the speed can be increased.

Output buffer TOB for parallel test and pad TP ₁ ~
The TP ₈ should also be placed on the left and right sides of the memory array. That is, the normal bonding pad is arranged near the peripheral circuit region on the upper and lower sides of the memory array in consideration of the delay of input / output signals. If a pad for testing is further provided in this area, the pad interval becomes narrow, and there is a high possibility that defects during assembly due to bonding mistakes will increase. Further, since there are no bonding pads on the left and right sides of the memory array and they are in the long side direction of the chip, a large number of output buffer circuits and test pads can be easily arranged.

FIG. 4 shows a third embodiment of the present invention. The present embodiment differs from the second embodiment in the arrangement direction of the data lines and word lines, but the data lines are arranged in the vertical direction and the word lines are arranged in the horizontal direction. Even in the case of such a memory array configuration, the same effect as that of the second embodiment can be obtained.

〔The invention's effect〕

As described above, according to the present invention, since the input / output line can be divided without increasing the chip size, the parasitic resistance and parasitic capacitance of the input / output line can be reduced, and the signal delay due to these can be reduced. Therefore, the operation of the memory can be speeded up.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIG.
(A), (b), (c) are diagrams showing a configuration of a conventional semiconductor memory, and FIGS. 3 and 4 are configurations of a semiconductor memory showing second and third embodiments of the present invention, respectively. It is a figure. D ₁ , ▲ ▼, 〜, D _2n , ▲ ▼ …… Data line, W ……
Word line, MC ... Memory cell, SA ... Sense amplifier, SW
₁ , ~, SW _2n ...... Connection switch, YS ₁ , YS _2n ...... Y decoder output line, XD ...... X decoder, YD ...... Y decoder, IO _a , ▲
▼, IO _b , ▲ ▼, IO, ▲ ▼ …… I / O line, M
A …… Memory array, AMP, AMP _a , AMP _b …… Data output amplifier, MO, MO _a , MO _b …… Data output amplifier output line, CSW ……
Switching switch, DO _b ...... Output buffer, DP ...... Data line pair, IP _a , IP _b , IP ₁ , IP ₂ ...... Input / output line pair, PRC ₁ , PRC ₂ ...
… Peripheral circuits, A ₁ , A ₈ ′ …… Sub array, SI ₁ , SI ₂ …… Auxiliary wiring, TE …… Test signal, TOB …… Test output buffer, TP ₁ , TP ₁₆ …… Test pad, CHIP ...... Chip.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Eto 1-280 Higashi Koigokubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hitoshi Tanaka 1448, Kamimizumotocho, Kodaira-shi, Tokyo Hitachi Super L. SII Engineering Co., Ltd. (72) Inventor Masashi Horiguchi 1-280 Higashi-Kengokubo, Kokubunji, Tokyo Metropolitan Institute of Hitachi, Ltd. (72) Yoshinobu Nakagome 1-280 Higashi-Kengokubo, Kokubunji-shi, Tokyo Stock Hitachi, Ltd. Central Research Laboratory (72) Inventor Masakazu Aoki 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Kiyoo Ito 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (56) Reference JP-A-1-1527 44 (JP, A) JP 63-153793 (JP, A) JP 52-58327 (JP, A) JP 59-175093 (JP, A) JP 59-198593 (JP, A)

Claims (4)

(57) [Claims] 1. A plurality of data lines, a plurality of word lines intersecting with the plurality of data lines, a plurality of memory cells arranged at intersections of the plurality of data lines and the plurality of word lines, and First and second memory arrays having a plurality of sense amplifiers connected to a plurality of data lines and sub input / output lines commonly connected to the plurality of data lines, and the first and second memories Semiconductor memory having a first data output amplifier and a second data output amplifier respectively connected to the sub input / output lines of the array, and a decoder for selecting a desired word line of the first and second memory arrays. In the device, the decoder is arranged between the first memory array and the second memory array, and the first data output amplifier is arranged above the first data output amplifier and the decoder. The second data output amplifier is arranged so as to sandwich the first memory array, and the second data output amplifier is arranged so as to sandwich the second memory array between the second data output amplifier and the decoder. Semiconductor memory device. 2. A common output line to which the output of the first data output amplifier and the output of the second data output amplifier are commonly connected, and an output buffer circuit to which the common output line is connected. The semiconductor memory device according to claim 1, wherein the output buffer circuit is arranged closer to the first data output amplifier than the second data output amplifier. 3. The semiconductor memory device according to claim 2, further comprising a plurality of output pads connected to the outputs of the first and second data output amplifiers, respectively. 4. A connection between the outputs of the first and second data output amplifiers and the output buffer circuit, and a connection between the outputs of the first and second data output amplifiers and the plurality of output pads. 4. The semiconductor memory device according to claim 3, further comprising a circuit for switching between the connection and the connection.