JP2680909B2 - Buffer storage - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer storage device, and more particularly to cache control during execution of an instruction for storing a plurality of data in a general-purpose register in a multiprocessor information processing device.

2. Description of the Related Art Conventionally, in an information processing device, an address is automatically sent to another processor between multiprocessors sharing a storage device, and if the data at the address exists in the cache, the data in the cache is saved. The following method is available as a method for matching the data in the cache with the data used by each processor when it has no invalidating function.

That is, when a plurality of processors share the data of the same address in the shared storage device and the data processed by a certain processor is stored at the address in the shared storage device, the data in the cache is compared with other processors. There is a method in which an instruction to invalidate data in the cache is executed so as to invalidate.

FIG. 3 is a block diagram showing a conventional example. In the figure, the buffer storage devices 7-1 and 7-2 have a low read / write processing speed, but a storage device 5 capable of storing a large amount of information and a high speed read / write processing. General purpose registers 2-1 and 2-2 and data path 101-
1, 101-2, 102-1, 102-2 are connected to each other, and a part of the information of the storage device 5 is eliminated in order to eliminate the neck of the information supply amount between the storage device 5 and the general-purpose registers 2-1 and 2-2. It plays the role of having a copy of.

In addition, since there is a probability that recently used data in the storage device 5 and data in the vicinity thereof will be used more than once, these data are stored in the high speed buffer storage devices 7-1 and 7-2.
By storing the data in the buffer storage device 7-
The data in 1, 7-2 can be used in place of the data in the storage device 5, and the effective access time can be shortened.

Therefore, the buffer storage devices 7-1 and 7-2 and the general-purpose register 2
Information can be transmitted and received at high speed to -1, 2-2, but they are connected by data paths 101-1 and 101-2 having a narrow data width, for example, an 8-byte width.

On the other hand, between the storage device 5 and the buffer storage devices 7-1 and 7-2, it is possible to exchange information at low speed so that the data of the storage device 5 that has been used recently and the data in the vicinity thereof can be exchanged as one block. However, they are connected by data paths 102-1 and 102-2 having a wide data width, for example, a 32-byte width.

When the instruction to execute the arithmetic instruction is issued, the arithmetic units 9-1 and 9-2 receive the general-purpose register 2-through the data paths 124-1 and 124-2.
While the data from 1, 2-2 is input, the signal line 121
An execution instruction is input via -1, 121-2, and the calculation result is input to general-purpose registers 2-1 and 2- through data paths 124-1 and 124-2.
Stored in 2.

FIG. 4 is a diagram showing an instruction sequence for explaining the operation in the conventional example. In the figure, the instruction of the instruction sequence a is an instruction to read data from the address 100 of the storage device 5 and store the data in the general-purpose register R7.

Usually, a program divides an instruction sequence into tasks, and the tasks are processed by each processor.

In the case shown in FIG. 4, for simplification, instructions,
Is a task, instructions are one task, and instructions are one task, an instruction and an instruction sequence b-1 of the instruction are allocated to the processor 1-1, and the instruction sequence b- 2 is processor 1
-2 is assigned and executed.

When the instruction sequence assigned to a task is assigned to processors 1-1 and 1-2 with different orders, a synchronization instruction is automatically inserted by software at the beginning of each task to guarantee the instruction history. .

In this case, since the tasks of the instruction and the tasks of the instruction and the task of the instruction are different from each other, the synchronization instruction is inserted before the instruction.

Also, before the instruction, a synchronization instruction is inserted for the same reason as above.

The instruction sequence b-1 of the instruction, ... Is the processor 1-
When the instruction sequence b-2 of the instruction is executed by the processor 1-2, the block data including the address of address 100 from the storage device 5 is transmitted to the data path 102-1 by the instruction in the processor 1-1. Through the buffer storage device 7-1
Data of the target address 100 is further stored from the buffer storage device 7-1 to the seventh register R7 of the general-purpose register 2-1 via the data path 101-1.

7th register of general purpose register 2-1 by instruction
The data of R7 and the data of the fifth register R5 are added by the arithmetic unit 9-1, and the calculation result is the sixth register.
When it is stored in R6, that is, when the processing of the instruction is completed, the synchronization instruction is executed in the processor 1-2 due to the completion of the instruction.

In the processor 1-2, the storage devices 5 to 10 are instructed by the instruction.
Block data including address 0 is data path 102
-2 is stored in the buffer storage device 7-2, and the target data of address 100 is further transferred from the buffer storage device 7-2 to the tenth register R10 of the general-purpose register 2-2 via the data path 101-2. Is stored.

Next, according to the instruction, the arithmetic unit 9-2 adds the data of the 10th register R10 of the general-purpose register 2-2 and the data of the 12th register R12, and the arithmetic result is stored in the 18th register R18. To be done.

The data stored in the 18th register R18 by the instruction, that is, the calculation result of the calculator 9-2 is the data path 101-
The data is stored in the buffer storage device 7-2 via 2 and is further stored from the buffer storage device 7-2 via the data path 102-2 at the address 100 of the storage device 5.

At this time, the buffer storage devices 7-1 and 7-2 in the processors 1-1 and 1-2 store the data corresponding to the address of address 100 of the storage device 5, but the buffer storage device 7-1. , 7
-2 The value stored in each is different.

That is, the data first read from the storage device 5 is stored in the location corresponding to the address 100 of the buffer storage device 7-1, and the location corresponding to the address 100 of the buffer storage device 7-2 is stored in the location corresponding to the address 100. The calculation result of the calculator 9-2 is stored.

Since the arithmetic result of the arithmetic unit 9-2 is stored in the address 100 of the memory device 5, the buffer memory device 7-1
The data at the location corresponding to the address of 100 will be invalid.

When the instruction is executed in the processor 1-1 in the above state, the illegal data at the location corresponding to the address 100 of the buffer memory device 7-1 is stored in the eighth register R8 of the general-purpose register 2-1. Will be done.

In order to prevent such a data inconsistency in the buffer storage devices 7-1 and 7-2 between the processors 1-1 and 1-2, the instruction sequence b-1 is replaced by the instruction sequence c under the responsibility of the software. Instead, that is, a cache clear instruction is inserted between the synchronization instruction and the instruction, and all the data in the buffer storage device 7-1 is invalidated by the cache clear instruction.

When the instruction is executed after the execution of the cache clear instruction, valid data does not exist in the buffer storage device 7-1. Therefore, by reading the data from the storage device 5, the buffer between the processors 1-1 and 1-2 is buffered. Data matching in the storage devices 7-1 and 7-2 was guaranteed.

In addition to the method described above, the following method is available as a method for matching the data in the cache with the data used by each processor.

A cache bypass bit is provided in the table of the address translation buffer in the storage device, and even if a data transfer instruction is executed between the storage device and the general-purpose register when the cache bypass bit is turned on, the buffer storage bit is stored in the buffer storage device. By not storing the data in, the data matching in the buffer storage device of each processor was realized.

Therefore, when the instruction for storing the plurality of data in the storage device in the general-purpose register is executed and the cache bypass bit in the table of the address translation buffer referred to by the virtual address generated by the instruction is on, Since the data read from the storage device is not retained in the cache in the buffer storage device, the data transfer from the buffer storage device to the general-purpose register can be performed only at a fixed data width (8 bytes) at a time, and a plurality of target multiple Block data (for example, 32 bytes of data was transferred eight times) was read from the storage device to the buffer storage device until the data was stored in the general-purpose register.

That is, as shown in FIG. 5, when an instruction to execute an instruction to store a plurality of data in the general-purpose register 2-1 is issued from the storage device 5, the instruction register of the instruction control device 8-1.
A virtual address is generated from 81-1 through an adder 82-1.
The virtual address is transmitted to the control device 71-1 of the buffer storage device 7-1 via the address register 83-1.

When the address data is transmitted from the control device 71-1 to the address translation buffer (ATB) 51 of the storage device 5 via the signal line 134, the state of the cache bypass bit in the table corresponding to the address of the address translation buffer 51 is changed. The signal is transmitted to the selectors 73-1 and 74-1 via the signal line 108.

In the selectors 73-1 and 74-1, if the cache bypass bit is on, the path to the data selection circuit 75-1 is selected, and if the cache bypass bit is off, the path to the cache 72-1 is selected. The path is selected.

If the cache bypass bit is on now, the block data is transferred from the storage device 5 via the data path 102 to the buffer storage device 7-1 by the absolute address generated by the table corresponding to the address of the address translation buffer 51. To the data selection circuit 75-1, the selector 74-1 selects the data path to the data selection circuit 75-1, so that the data selection circuit 75-1 selects the data (8 bytes) to be stored in the general-purpose register 2-1. .

The data selected by the data selection circuit 75-1 is the data path
An address from the instruction control unit 8-1 sent to the general-purpose register 2-1 via the selector 132, selector 73-1 and the data path 101 and input via the signal line 137 is used as the storage address information in the general-purpose register 2-1. Stored in.

The above processing operation is repeatedly executed until a plurality of target data are stored in the general-purpose register 2-1.

Here, as shown in FIG. 6, when the address translation buffer 51 is accessed by the upper address (table number) A1 of the virtual address A, a cache bypass bit is included from the address translation table 51a of the corresponding address translation buffer 51. The data B is read, and the displacement A2 of the virtual address A is added to this data B to generate the absolute address C.

In such a conventional buffer memory device, when the cache bypass bit added to the referenced address translation table 51a in the address translation buffer 51 is turned on, the data is read from the memory device 5 to the buffer memory device 7-1. The cached block data is stored in the buffer 72 in the cache 72.
-1 is not held, the buffer storage device 7-1 stores general data if the cache bypass bit is turned on when an instruction to store a plurality of data from the storage device 5 into the general-purpose register 2-1 is executed. Since the block data must be read from the storage device 5 to the buffer storage device 7-1 as many times as the number of times data is stored in the register 2-1, there is a disadvantage that a lot of processing time is spent.

Further, by reading the block data as many times as the number of times the data is stored in the general-purpose register 2-1, the data path 102 of the storage device 5 is occupied during that time, and the access to the storage device 5 of another processor 1-2 is performed. Has the drawback of being delayed.

OBJECT OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional ones, and can significantly reduce the data transfer time from the storage device, and the access to the storage device from other subsequent processors. An object of the present invention is to provide a buffer memory device that can speed up the operation.

According to the buffer storage device of the present invention, the registration of the data read from the storage device by the address converted by the address conversion table in the cache memory is held corresponding to the address and the data is stored in the cache memory. A buffer storage device including first control means for controlling in accordance with cache bypass information indicating whether to register the data into a general-purpose register. And when the cache bypass information corresponding to the address translated in the address translation table by the instruction indicates that the data is not registered in the cache memory, the plurality of data read from the storage device by the instruction. A second control for controlling data to be registered in the cache memory Control means, read control means for sequentially reading the plurality of data registered in the cache memory under the control of the second control means, and storing the plurality of data in the general-purpose register; The plurality of data read from the storage device and registered in the cache memory by the instruction when all of the plurality of data read and registered in the cache memory are stored in the general-purpose register by the read control means. And means for invalidating the data.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, the buffer storage device 3-1 is provided with a cache 33-1 for supplying the data in the storage device 5 which is commonly used to the general-purpose register 2-1. When storing the data in the register 2-1, the target data is the cache 33-1.
Since the target data can be fetched from the cache 33-1 without reading the target data from the storage device 5 if the target data is present, the target data can be stored in the general-purpose register 2-1 in a short time.

In an information processing device that accesses the storage device 5 using the paging method, when execution start of a memory access instruction is applied, the instruction register 41-1 of the instruction control device 4-1.
From the adder 43-1 to generate a virtual address, and the virtual address is stored in the buffer memory 3 from the address register 44-1.
-1 control device 32-1 to be transmitted to the storage device 5.

The storage device 5 uses the address conversion buffer 51 to perform address conversion for converting the virtual address into an absolute address, and the absolute address is used to read / write data from / to the storage device 5.

Normally, in the load instruction, the virtual address generated by the instruction control device 4-1 is transmitted from the address register 44-1 to the control device 32-1 in the buffer storage device 3-1 via the signal line 105, and the target data is obtained. Is not present in the cache 33-1, it is further transmitted to the address translation buffer 51 of the storage device 5 via the signal line 112.

The virtual address is converted into an absolute address by the address conversion buffer 51, and data is taken out from the storage device 5 by this absolute address and stored in the cache 33-1 via the data path 102.

The data stored in the cache 33-1 is the data path 101,
The instruction control device 4-which is sent to the general-purpose register 2-1 through the selector 104 and selector 35-1 and is input through the signal line 106
The address from 1 is stored in the general-purpose register 2-1 as storage register number information.

However, execution of an instruction to transfer a plurality of data from the storage device 5 to the general-purpose register 2-1 is activated,
Further, when the cache bypass bit in the table of the address translation buffer 51 corresponding to the generated virtual address is turned on, the control device 31-1 operates so as to prevent the cache bypass bit from being turned on.

That is, the control device 31-1 receives the decode signal 107 from the decoder 42-1 of the instruction control device 4-1, that is, the instruction register 4
An instruction for transferring a plurality of data stored in the instruction section 1-1, the signal decoded by the decoder 42-1 and the signal line 108
Depending on the state of the cache bypass bit in the table of the address translation buffer 51 input via the, the cache bypass bit is turned on in the execution of the instruction to transfer a plurality of data from the storage device 5 to the general register 2-1. Then, the selection signal is output to the selectors 53-1 and 36-1 via the signal line 109 so that the selectors 35-1 and 36-1 select the data path with the cache 33-1. Control.

As a result, the block data including the target data sent from the storage device 5 via the data path 102 is stored in the cache 33-1 via the selector 36-1.

Target data in the block data stored in the cache 33-1 is sent to the general-purpose register 2-1 a plurality of times via the data paths 101 and 104 and the selector 35-1.
The address input from the instruction control device 4-1 via the signal line 106 is stored in the general-purpose register 2-1 as storage register number information.

When a plurality of pieces of data are transferred from the storage device 5 to the general-purpose register 2-1 as described above, the processing of the instruction ends.

Further, in order to realize data matching with the cache (not shown) of the other processor 1-2, the control device 31-1 sets the cache 33-1 via the signal line 110 at the time when the instruction is completed. It controls and clears the entries of a plurality of data from the storage device 5 stored in the cache 33-1.

On the other hand, if the cache bypass bit is turned on at the time other than the instruction in which a plurality of data is transferred from the storage device 5 to the general-purpose register 2-1, the control device 31-1 input via the signal line 109. Select signal from the selector 36
Since the data path to the data selection circuit 34-1 is selected by -1, the data selection circuit 34-1 outputs data from the storage device 5 from the control device 32-1 input via the signal line 113. The data corresponding to the address is selected.

The data selected by the data selection circuit 34-1 is the data path
General-purpose register 2 through 101, 103 and selector 35-1
The address from the instruction control device 4-1 which is sent to the No. 1 and is inputted via the signal line 106 is stored in the general-purpose register 2-1 as the storage register number information.

The other processor 1-2 has the same configuration as the processor 1-1, and the processing operation is also the same.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, another embodiment of the present invention is a buffer 67.
1 is the same as that of the embodiment of the present invention shown in FIG. 1 except that the buffer memory device 6-1 including -1 is provided, and the same components are denoted by the same reference numerals. The operation of those same parts is similar to that of the embodiment of the present invention.

 The operation of the buffer storage device 6-1 will be described below.

A plurality of data is transferred from the storage device 5 to the general-purpose register 2-1.
When the cache bypass bit in the table of the address translation buffer 51 corresponding to the virtual address generated by the instruction control device 4-1 is turned on, the instruction to be transferred to the memory is normally used. cache
A buffer used only in this state, apart from 63-1 67
The control devices 61-1 and 62-1 operate to use -1.

That is, the control device 61-1 receives the decode signal 107 from the decoder 42-1 of the instruction control device 4-1, that is, the instruction register 4
An instruction for transferring a plurality of data stored in the instruction section 1-1, the signal decoded by the decoder 42-1 and the signal line 108
Depending on the state of the cache bypass bit in the table of the address translation buffer 51 input via the, the cache bypass bit is turned on in the execution of the instruction to transfer a plurality of data from the storage device 5 to the general register 2-1. Then, a selection signal is output to the selectors 65-1 and 66-1 via the signal line 109 so that the selectors 65-1 and 66-1 select the data path with the buffer 67-1. Along with the control, a storage instruction signal is output to the control device 62-1 via the signal line 115 in order to store the block data from the storage device 5 in the buffer 67-1.

Upon receipt of the storage instruction signal from the control device 61-1, the control device 62-1 signals the storage instruction together with the address sent from the address register 44-1 of the instruction control device 4-1 via the signal line 105. Output to buffer 67-1 via line 116.

As a result, the block data including the target data sent from the storage device 5 via the data path 102 is stored in the buffer 67-1 via the selector 66-1.

The target data in the block data stored in the buffer 67-1 is sent to the general-purpose register 2-1 a plurality of times via the data paths 101 and 117 and the selector 65-1, and the instruction control is input via the signal line 106. The general-purpose register 2 uses the address from the device 4-1 as the storage register number information.
It is stored in -1.

When a plurality of pieces of data are transferred from the storage device 5 to the general-purpose register 2-1 as described above, the processing of the instruction ends.

Here, the processing operation when the data from the storage device 5 is transferred to the general-purpose register 2-1 through the cache 63-1 or the data selection circuit 64-1 is the processing operation according to the above-described embodiment of the present invention. Is the same as.

The other processor 1-2 has the same configuration as the processor 1-1, and the processing operation is also the same.

In this way, an instruction for reading a plurality of data from the storage device 5 and storing it in the general-purpose register 2-1 is executed, and the cache bypass bit corresponding to the address translated in the address translation buffer 51 is turned on by the instruction. At this time, the plurality of data read from the storage device 5 by the instruction are registered in the cache 33-1 under the control of the control device 32-1 and all the plurality of data registered in the cache 33-1 are stored. When the data is read out and stored in the general-purpose register 2-1, the plurality of data registered in the cache 33-1 is invalidated by the control of the control device 31-1, so that the conventional storage device 5 If the cache bypass bit is turned on when transferring a plurality of data to the general-purpose register 2-1, the buffer storage device stores the data in the general-purpose register 2-1. The block data had to be read from the storage device 5 the number of times, but even if the cache bypass bit was turned on, the storage device 5
By registering the block data from the storage device 3 in the cache 33-1, the block data can be transferred from the storage device 5 only several times, so that the data transfer time from the storage device 5 can be significantly reduced.

This reduces the processing time, so the data path
The time for occupying 102 can be shortened, and the access to the storage device 5 from another subsequent processor 1-2 can be speeded up.

An instruction for reading a plurality of data from the storage device 5 and storing it in the general-purpose register 2-1 is executed, and the cache bypass bit corresponding to the address translated by the address translation buffer 51 is turned on by the instruction. At this time, a plurality of data read from the storage device 5 by the instruction is registered in the buffer 67-1 under the control of the control device 62-1 and the data registered in the buffer 67-1 is sequentially read to read the general register 2. By storing the data in -1, the data transfer time from the storage device 5 can be greatly reduced, and the access to the storage device 5 from another subsequent processor 1-2 can be accelerated.

Further, by registering a plurality of data read from the storage device 5 in the buffer 67-1, the cache memory in the buffer storage device between the processors is inserted by the insertion of the cache clear instruction guaranteed by the software. There is no need to perform data matching control,
Since the operation of clearing all the data in the buffer memory device is also unnecessary, the information required by the memory access instruction in the subsequent instruction will exist in the buffer memory device with a high probability, and the processing of the subsequent memory access instruction will be performed. Can run faster.

As described above, according to the buffer storage device of the present invention, an instruction to read a plurality of data from the storage device and store it in a general-purpose register is executed, and the instruction converts the address into an address converted by the address conversion table. When the corresponding cache bypass information indicates that registration in the cache memory is not performed, control is performed to register a plurality of data read from the storage device in the cache memory by the instruction, and the data is registered in the cache memory. When a plurality of data are all read and stored in a general-purpose register, the plurality of data registered in the cache memory are invalidated, thereby significantly reducing the data transfer time from the storage device. It is possible to speed up access to the storage device from other subsequent processors. There is fruit.

According to another buffer memory device of the present invention, an instruction for reading a plurality of data from the memory device and storing it in a general-purpose register is executed, and the cache bypass corresponding to the address translated by the address translation table by the instruction is executed. When the information indicates that the data is not registered in the cache memory, the plurality of data read from the storage device by the instruction is controlled to be held in a holding unit different from the cache memory, and the holding unit is controlled to hold the data. By sequentially reading out a plurality of held data and storing them in a general-purpose register, it is possible to greatly reduce the data transfer time from the storage device and to access the storage device from other subsequent processors. Can be faster,
There is an effect that the processing of the subsequent memory access instruction can be executed quickly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention, and FIGS. 3 and 5 are block diagrams showing the configuration of a conventional example. FIG. 4 is a diagram showing an instruction sequence for explaining the operation of the conventional example,
FIG. 6 is a diagram showing conversion from a virtual address to an absolute address. Description of symbols of main parts 1-1, 1-2 ... processor 2-1 ... general-purpose register 3-1, 6-1 ... buffer storage device 4-1 ... instruction control device 5 ... storage device 31- 1,32-1,61-1,62-1 …… Control device 33-1,63-1 …… Cache 35-1,36-1,65-1,66-1 …… Selector 67-1 …… buffer

Claims (1)

(57) [Claims] 1. Whether to register the data read from the storage device by the address converted by the address conversion table in the cache memory, whether the data is held corresponding to the address and the data is registered in the cache memory. A buffer memory device for controlling in accordance with cache bypass information indicating that a command for reading a plurality of data from the memory device and storing the data in a general-purpose register is executed, and the address causes the address to be read. When the cache bypass information corresponding to the translated address in the translation table indicates that the data is not registered in the cache memory, the plurality of data read from the storage device by the instruction is stored in the cache memory. Second control means for controlling to register,
Read control means for controlling to sequentially read the plurality of data registered in the cache memory and store the data in the general-purpose register under the control of the second control means, and read from the storage device by the instruction and When the plurality of data registered in the cache memory are all stored in the general-purpose register by the read control means, the plurality of data read from the storage device by the instruction and registered in the cache memory are invalid. And a buffering device.