JP2680974B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.

[0002]

2. Description of the Related Art Generally, a resin-sealed type semiconductor device mounts a semiconductor chip on an island, and bonds between a lead arranged around the island and a bonding pad provided on the semiconductor chip. It is electrically connected by wires.

For such semiconductor devices, LOC has been recently used.
A semiconductor device assembled by a new technology called (Lead On Chip) has appeared. This is to eliminate the island for mounting the semiconductor chip and to fix and hold the semiconductor chip by the leads themselves connected to the pins of the package.

FIGS. 3A and 3B are a plan view and a sectional view taken along the line AA 'showing an example of a conventional semiconductor device.

As shown in FIGS. 3A and 3B, an adhesive tape 15 is inserted between the leads 12a to 12d and the semiconductor chip 10 and the semiconductor chip 10 is fixed to the leads by thermocompression bonding. Next, the leads 12a to 12d and the bonding pads 13a to 13d provided on the semiconductor chip are electrically connected by the bonding wires 14a to 14d. Here, in order to enhance the effect of supporting the semiconductor chip by the leads, the width of the tips of the leads 12a to 12d in the portion to be bonded onto the semiconductor chip 10 is increased to increase the contact area with the adhesive tape 15.

When this LOC technique is used, it is not necessary to separate the island and the lead. Therefore, as compared with the case where the assembly technique using the island is used, a semiconductor chip which is larger by an amount corresponding to the separation region is the same. It has the advantage that it can be assembled into a large package. or,
Since the leads are arranged on the semiconductor chip, changing the shape of the leads also has an advantage of increasing the degree of freedom in arranging the bonding pads on the semiconductor chip.

For example, arranging the bonding pad at the center of the semiconductor chip also means that the bonding wire becomes long in a package using an island,
Although the problem of contact with the semiconductor chip has occurred, such a problem does not occur in this LOC technology.

[0008]

However, this L
The conventional semiconductor device assembled by the OC technique has a problem that cracks are likely to occur in the protective film formed on the semiconductor chip. Hereinafter, this point will be described in detail.

Generally, in a semiconductor device, an aluminum wiring is used for the wiring closest to the surface, and a protective film made of a silicon oxide film or a silicon nitride film is further formed on the aluminum wiring for the purpose of protection against external contamination and scratches. Is forming.

However, in the semiconductor device assembled by the LOC technique, the surface of the semiconductor chip is in contact with the lead though the adhesive tape is used. When a semiconductor device having such a structure is subjected to thermal stress such as being kept at a high temperature, a thermal stress is generated at the interface between the aluminum wiring, the protective film, and the lead due to a difference in thermal expansion coefficient between the lead. The protective film in a region sandwiched between the aluminum wiring and the lead receives thermal stress from above and below, and the protective film is damaged and cracks occur. These cracks are more likely to occur as the aluminum wiring is thicker and the contact area with the protective film is larger.

In a semiconductor memory device, aluminum wiring having a width of 50 μm to 100 μm is often provided as a power supply wiring in the peripheral portion on a semiconductor chip, and cracks in the protective film are likely to occur particularly in this portion. .

In order to prevent cracks from occurring in the protective film, the contact area between the aluminum wiring and the protective film and between the protective film and the lead may be reduced. Although slits are formed in the aluminum wiring, slitting over the entire area of the wiring may reduce the effective wiring width, increase wiring resistance, and cause problems in circuit operation. Further, if the leads are thinned in order to reduce the contact area, there arises a problem that the effect of holding the semiconductor chip by the leads peculiar to the LOC is weakened.

An object of the present invention is to provide a semiconductor device in which cracks are prevented from occurring in a protective film supporting a semiconductor chip and reliability is improved.

[0014]

According to the present invention, there is provided a semiconductor device comprising:
A power supply system metal wiring provided in the peripheral portion of the semiconductor chip, a protective film provided on the metal wiring, and a metal wiring are arranged on the protective film across the metal wiring and bonded to the upper surface of the semiconductor chip. In a semiconductor device having a lead supporting the semiconductor chip, a width of a portion of the lead that intersects with the metal wiring is made narrower than other portions.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a first embodiment of the present invention.

As shown in FIG. 1, the leads 12a, 12 are arranged so as to straddle over the aluminum wiring 16 of the power supply system having a width of about 50 μm provided in the peripheral portion of the semiconductor chip 10.
Only the intersecting portion on the aluminum wiring 16 of b is thinner than the other portions. Note that 13a and 13b are bonding pads provided in the peripheral portion of the semiconductor chip 10.

Thus, the aluminum wiring 1 of the power supply system
6, the widths of the leads 12a and 12b are made narrower than the other portions, so that the ability of the leads 12a and 12b to support the semiconductor chip 10 is hardly reduced and the leads 12a and 12b are not reduced.
It is possible to prevent the occurrence of cracks by reducing the contact area between the protective films provided on the a and 12b and the aluminum wiring 16. Further, since the width of the aluminum wiring 16 is not changed at all, there is no problem such as an increase in wiring resistance.

FIG. 2 is a plan view showing a second embodiment of the present invention.

As shown in FIG. 2, the aluminum wiring 1 of the leads 12a and 12b provided on the peripheral portion of the semiconductor chip 10 and straddling the aluminum wiring 16 is provided.
6 has the same configuration as that of the first embodiment except that a slit 17 is provided at the intersecting portion on 6 to reduce the effective contact area with the protective film.

[0021]

As described above, according to the present invention, the width of the portion of the lead, which is adhered to the upper surface of the semiconductor chip and supports the semiconductor chip and intersects with the power supply system metal wiring, is made narrower than the other portions. It has an effect of preventing the protective film formed on the surface of the chip from being damaged by thermal stress.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a plan view showing a second embodiment of the present invention.

FIG. 3 is a plan view showing an example of a conventional semiconductor device and FIG.
A 'sectional drawing.

[Explanation of symbols]

10 Semiconductor Chip 11 Island 12a, 12b, 12c, 12d Lead 13a, 13b, 13c, 13d Bonding Pad 14a, 14b, 14c, 14d Bonding Wire 15 Adhesive Tape 16 Aluminum Wiring 17 Slit 21 Semiconductor Substrate 22 Protective Film

Claims (2)

(57) [Claims] 1. A power supply system metal wiring provided in a peripheral portion of a semiconductor chip, a protective film provided on the metal wiring, and a protective film provided on the protective film across the metal wiring. A semiconductor device having a lead bonded to an upper surface to support the semiconductor chip, wherein a width of a portion of the lead intersecting with the metal wiring is made narrower than other portions. 2. The semiconductor device according to claim 1, further comprising a slit provided in a portion of the lead that intersects with the metal wiring.