JP2681756B2 - MOS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a function to <br/> the MOS type semiconductor equipment, and in particular relates to a semiconductor <br/> equipment having the features in contact with the electrode wiring.

[0002]

2. Description of the Related Art In recent years, the miniaturization of MOS transistors constituting a semiconductor integrated circuit device has progressed, and a so-called deep sub-micron generation has begun to be introduced. Along with this, high integration and high performance of integrated circuits are achieved. It is being promoted more and more. With the miniaturization of MOS transistors in this way, it is called bird's beak in the active area separation method that uses misalignment in the photolithography process and thermal oxidation that is commonly used, such as the selective oxidation method (LOCOS method). The presence of a beak-shaped oxide film on both ends of the separated thick thermal oxide film has become a major obstacle to miniaturization.

Further, in improving performance, the parasitic capacitance and parasitic resistance of MOS transistors have become major factors that hinder the improvement of circuit operation. In particular, the junction capacitance of the drain diffusion layer seriously affects the circuit operation (see Technical Report SDM92-137 of the Institute of Electronics, Information and Communication Engineers).

Under these circumstances, impurities of the same conductivity type or the opposite conductivity type of the same region are ion-implanted below the source region and the drain region through the contact hole opened in the insulating film to form the source region and the drain region. It has been proposed to reduce the junction capacitance between the source region and the drain region only below the contact hole by providing a semiconductor layer having an intermediate impurity concentration between the region and the substrate semiconductor (Japanese Patent Publication No. 4-57097). See the bulletin).

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
MOS formed by the method proposed in Japanese Patent Application No. 097
In the transistor, only the junction capacitance below the contact hole in the source region and the drain region is reduced, and a large effect cannot be expected. On the contrary, when a diffusion layer with an intermediate concentration of opposite conductivity type is formed under the source region and the drain region, the junction area increases as compared to the case where there is no diffusion layer with such an intermediate concentration, On the contrary, it may increase the junction capacitance. SUMMARY OF THE INVENTION It is an object of the present invention to provide a MOS transistor and a method of manufacturing the same that can reduce the diffusion layer junction capacitance by reducing the area of the source region and the drain region, and improve the circuit operation and the degree of integration. To do.

[0006]

According to the present invention, electrode wirings are connected to the source diffusion region and the drain diffusion region through a plurality of contact holes, and at least one of the contact holes in both diffusion regions is The diffusion insulating film is formed over the diffusion region and the isolation insulating film region, the isolation insulating film is removed in the contact hole, and an impurity diffusion layer of the same conductivity type as the source / drain region is formed at the bottom of the contact hole. . At that time, it is preferable that the gate electrode has a curved portion on the active region.

Further , in the present invention, in each of the source region and the drain region, the contact holes are arranged in two rows along the gate electrode, and one row is located in the active region and the other row is active. One contact hole in one row in each of the source and drain regions and two contact holes adjacent to the contact hole in the other row are located at the boundary between the region and the isolation insulating film region. When the centers of the two are connected, they are arranged at positions forming an isosceles triangle with one contact hole in one row as the apex.

One method of manufacturing the semiconductor device of the present invention is
The following steps are included to form a contact with the electrode wiring. (A) A step of depositing an interlayer insulating film on the entire surface of the substrate from above the gate electrode, and (B) so that a plurality of contact holes are formed in each of the source region and the drain region. , A contact hole region is set so that at least one of the contact holes straddles the diffusion region and the isolation insulating film region, and the interlayer insulating film is formed in the contact hole region between the substrate of the source region and the drain region and the isolation insulating film. Etching until the lower substrate is exposed to form a contact hole, (C) ion-implanting a second conductivity type impurity into the substrate through the contact hole, and (D) thereafter, the source through the contact hole. Forming an electrode wiring connected to the region or the drain region.

FIG. 1 shows a first comparative example . (A) is a plan view and (B) is a sectional view taken along line XX ′ in (A). As shown in FIG. 1A, three contact holes 11a are arranged along the polycrystalline silicon gate electrode 4 in each of the diffusion regions 5 of the source region and the drain region. Each contact hole 11a is formed so as to straddle the diffusion region 5 and the field oxide film region which is an insulating film for isolation on the outside thereof. Contact hole 1
The distance between 1a and the gate electrode 4 is set in consideration of misalignment in the photolithography process. In the prior art, the diffusion region 5'was formed up to the region indicated by the broken line, whereas in this comparative example , the position of the contact hole 11a is the same as the conventional position, and the boundary between the diffusion region and the isolation insulating film is in contact. The diffusion region 5 is reduced to the position where it reaches the hole 11a.

Referring to FIG. 1 (B) showing a sectional view, this M
Explaining the structure of the OS transistor, 1 is a P-type silicon substrate, 2 is a P-type well, and a channel region 9 is formed in the active region isolated by the field oxide film 6 of the isolation insulating film.
A gate electrode 4 is formed thereabove with a gate oxide film 3 interposed therebetween, and diffusion regions 5 of a source region and a drain region are formed across a channel region 9. A contact hole 11 is formed in the interlayer insulating film 7 formed on the gate electrode 4.
a is opened, and the contact hole 11a is formed at a position extending over the diffusion region 5 and the field oxide film 6 region. Of the bottom of the contact hole 11a, the field oxide film is selectively removed in the field oxide film region protruding from the diffusion region 5. Contact hole 1
An N-type diffusion layer 10 having impurities introduced by ion implantation through a contact hole 11a is formed at the bottom of 1a. Reference numeral 8 is an electrode wiring for connecting to the diffusion region 5 through the contact hole 11a.
Since the N-type diffusion layer 10 is formed at the position where the field oxide film region contacts the N-type well 2, the electrode wiring 8 does not directly contact the well 2.

In the comparative example of FIG. 1, the diffusion region 5'for the source / drain, which has been required up to the region shown by the broken line in the prior art, is reduced to the region 5 shown by the solid line.
As described above, the area of the diffusion region can be reduced by about several tens of percent as compared with the conventional case. Therefore, the junction capacitance of the diffusion region 5 can be reduced accordingly, and the circuit operation and the degree of integration can be improved at the same time. .

FIG. 2 shows a second comparative example .
Although the area of the diffusion region 5 is not smaller than that of the conventional one, it is intended to increase the current driving capability, that is, improve the circuit operation by increasing the gate width. In the comparative example of FIG. 2, each of the source region and the drain region is provided with three contact holes, but one contact hole 11a among the three contact holes is provided in each region as the diffusion region 5 and the field oxide film. By arranging the gate electrode so as to straddle, the area available for the gate electrode on the active region is increased. The gate electrode 4a has a bent portion bent in a crank shape, and effectively increases the gate width. The contact hole 11a is shown in FIG.
Similar to that shown in (B), the bottom portion extends over the diffusion region 5 and the field oxide film region, and a diffusion layer 10 of the same conductivity type as the diffusion region 5 is formed at the bottom of the contact hole. The other contact holes 11 are present only in the diffusion region 5, and they are the same as the conventional contact holes.

Usually, the most effective and simple method for improving the circuit operation is to increase the gate width. However, as in the prior art, a MOS having a linear gate electrode is used.
If the gate width of the transistor is increased, the area of the diffusion region is increased at the same time, and the junction capacitance of the diffusion region is also increased, which is not so effective when the circuit load is small.
However, in the comparative example of FIG. 2, since the area of the diffusion region 5 is not increased, the junction capacitance is not increased and the gate electrode 4 is not increased.
By providing the curved portion in a, only the gate width can be increased, which is effective in improving the circuit operation. For example, FIG.
The comparative example has the same area as the diffusion region 5'shown by the broken line in FIG. 1, but the gate width can be increased by about 50% by providing the gate electrode 4a with two curved portions.

[0014]

DETAILED DESCRIPTION FIG. 3 shows an embodiment, in which reduced the contact resistance by increasing the number of contact holes. As shown in FIG. 3A, contact holes arranged in two rows along the gate electrode 4 are arranged in the source region and the drain region, respectively. In each region 5, the contact hole 11 in one column is in the diffusion region 5, and the contact hole 11a in the other column is arranged so as to extend over the diffusion region 5 and the field oxide film region.

According to the consideration of the present inventors, except when the gate width is extremely small, the contact resistance has almost no influence on the transistor characteristics when the number of rows of contact holes is two or more. Conventionally, it has been difficult to reduce the contact resistance without increasing the area of the diffusion region. As shown in FIG. 3A, by arranging the contact holes 11 in one column in the diffusion region 5 and arranging the contact holes 11a in the other column across the diffusion region 5 and the field oxide film region, The number of contact holes that can be arranged is increased and the increase in the area of the diffusion region is suppressed.

The shapes of the contact holes 11 and 11a are
Even if it is designed to have a square shape as shown by the broken line in FIG. 3B, the distance between the contact holes becomes larger than the designed value because the corners are rounded and become close to a circle. In order to increase the number of contact holes per unit area, one contact hole 11 (or 11a) in one row and two contact holes 11a (adjacent to that contact hole in the other row) in each diffusion region 5 Alternatively, 11) is arranged at a position forming an isosceles triangle having one contact hole in one row as an apex when connecting the respective centers.

FIG. 4 shows an example of manufacturing the semiconductor device of the present invention, and the case where the contact hole arrangement is as shown in FIG. 1 is taken as an example. However, in FIG.
The same applies to the contact hole arrangement shown in FIG. (A) An N-channel MOS transistor is formed in the active region. A P-type well 2 is formed on the surface of the silicon substrate 1, and a field oxide film 6 is formed in the well 2.
A gate electrode 4 made of phosphorus-doped polycrystalline silicon is formed on the channel region through the gate oxide film 3 in the active region separated by. On the surface of the well 2, a source region and a drain region 5 made of an N ⁺ diffusion layer are formed across the channel region.

In order to form the MOS transistor in this state, the P-type well 2 is formed on the surface of the P-type silicon substrate 1 by a known technique and the thickness of 4500 to 6000 Å is formed by the selective oxidation method (LOCOS method). A thermal oxide film (field oxide film) 6 separates the active region.
A thermal oxide film 3 serving as a gate oxide film having a thickness of 100 to 150Å is formed on the active region, and a polycrystalline silicon film 4 having a thickness of about 3500Å is further formed thereon. The polycrystalline silicon film 4 is finally doped with phosphorus. Such a polycrystalline silicon film 4 may be one in which phosphorus is introduced by a diffusion method or an ion implantation method after forming a polycrystalline silicon film not doped with impurities, and the polycrystalline silicon film is formed by a CVD method. It is also possible that phosphorus is introduced into the reaction gas when depositing, and a phosphorus-doped polycrystalline silicon film is formed in the deposited state. Finally, the phosphorus-doped polycrystalline silicon film 4 is patterned into a gate electrode shape by lithography and etching.

In the active region, the channel region 9 is formed by implanting N-type impurities using the gate electrode as a mask.
A source region and a drain region formed by sandwiching N ⁺
The mold layer 5 is formed. The N ⁺ type layer 5 can be formed, for example, by implanting arsenic ions under the conditions of a dose amount of 6 × 10 ¹⁵ / cm ² and an implantation energy of 50 KeV and performing a heat treatment at 850 ° C. for 20 minutes. A diffusion layer with a depth of about 0.15 μm is obtained.

(B) Next, CV is formed on the entire surface from above the gate electrode.
NSG film of about 3000 Å (silicon oxide film not doped with impurities) by D method, and 50
The interlayer insulating film 7 is formed by depositing a BPSG film (boron phosphorus silicon glass film) of about 00Å. Contact holes 11a are formed in the interlayer insulating film 7 on the source region and the drain region by photolithography and etching.

At this time, as shown in the enlarged sectional view (b) of the contact hole portion, the contact hole 1
The point where the region where 1a is opened is set so as to straddle the diffusion region 5 of the source / drain and the end of the field oxide film 6, and the thermal oxide film 6 ′ existing at the bottom of the contact hole is over-etched by several tens%. Is removed and the surface of the silicon substrate underneath is exposed. The amount of over-etching is based on the amount of just-etching of the interlayer insulating film for forming the contact hole, and a numerical value indicates what percentage of the amount is over-etching. For example, when the contact hole diameter is 0.4 μm and the aspect ratio of the contact hole (contact hole depth / diameter) is about 2, the overetch amount is appropriately set to about 50%.

In the case of contact hole arrangements as shown in FIGS. 2 and 3, not only the contact holes 11a extending over the diffusion region 5 and the field oxide film 6 but also the contact holes 11 arranged only within the diffusion region 5 are formed. Also exists. However, the photolithography and etching processes are the same in all the examples, and there is no problem.

(C) After that, phosphorus or arsenic is ion-implanted into the entire surface of the substrate surface. Thus, the contact holes 11a (FIG. 2, the contact hole 11 is also included in FIG. 3) through the, N-type layer 10 is formed below the contact hole 11a. As the implantation impurity, if it is desired not to heat much in the subsequent process, it is preferable to select phosphorus that can be activated at a lower temperature than arsenic, but under the same implantation energy, phosphorus has a larger projection range than arsenic. Therefore, it is necessary to adjust the implantation energy. For example, when it is desired to make the impurity distribution of the N-type layer 10 similar to that of the N ⁺ -type layer 5, the implantation energy of phosphorus may be set to about 30 KeV. In order to suppress the junction capacitance in the N-type layer 10 below the contact hole 11a, it is preferable to control the impurity distribution so as to be deep and gentle. However, the implantation and activation conditions may be set together with other requirements. . After that, the electrode wiring 8 is formed by a known technique.

The thus formed M of FIG. 4C
In the OS transistor, the field oxide film in the contact hole is completely removed at the bottom surface of the contact hole to expose the surface of the well 2 therebelow, and the surface height of the source / drain region is also high. The height is lower than the height of the original substrate surface (the surface of the well 2 in this embodiment). Further, since the field oxide film is removed, there is a step in the bottom surface of the contact hole. Therefore, the contact area is increased as compared with the conventional case where the contact hole is formed only on the diffusion region, and each contact hole is The contact resistance of is reduced.

Moreover, since the N-type layer 10 due to the impurities injected through the contact hole exists at the bottom of the contact hole, it is possible to prevent the leak from the electrode wiring 8 to the well 2 and the substrate 1 and to prevent misalignment. You can give some margin.

In the above embodiments, the N-channel type MOS transistor having the single drain structure has been described as an example, but the present invention is not limited to the P-channel type MOS transistor, and the MOS having the LDD structure or the gate overlap structure. The present invention can be applied to a transistor and other insulated gate type transistors, and in those cases, the same effect as in the case of the above embodiment can be obtained.

[0027]

According to the present invention, a plurality of contact holes are provided in each of the source / drain diffusion regions,
At least one of the contact holes is formed over the diffusion region and the isolation insulating film region, the isolation insulating film is removed in the contact hole, and the impurity diffusion layer of the same conductivity type as the source / drain region is formed at the bottom of the contact hole. Since the junction capacitance of the diffusion layer that greatly affects the circuit operation is reduced, the current driving force is improved without increasing the area of the diffusion region, and the parasitic resistance of the contact portion is reduced. The circuit operation can be improved. Moreover, since the diffusion layer due to the impurities injected through the contact hole exists at the bottom of the contact hole, it is possible to prevent the leak from the electrode wiring to the well and the substrate, and to give some margin to the misalignment. .

In the source / drain regions, contact holes are arranged in two rows along the gate electrode, one row is located in the active region, and the other row is located at the boundary between the active area and the isolation insulating film area. When positioned, one contact hole in one row and two contact holes adjacent to that contact hole in the other row are connected with their centers, and one contact hole in one row serves as an apex. because disposed at a position constituting the equilateral triangle, the source and drain regions contact Ki hole density out to enhance the in, it is possible to reduce the parasitic resistance of the contact portion without increasing the junction capacitance of the diffusion layer, the integrated The circuit operation can be improved without lowering the degree.

[Brief description of the drawings]

1A and 1B are diagrams showing a first comparative example , FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line XX ′.

FIG. 2 is a plan view showing a second comparative example .

FIG. 3 is a diagram showing an embodiment , (A) is a plan view,
FIG. 3B is a plan view showing the arrangement of contact holes.

FIG. 4 is a process sectional view showing an example of a manufacturing method .

[Explanation of symbols]

 1 P-type silicon substrate 2 P-type well 3 Gate oxide film 4, 4a Gate electrode 5 Source / drain diffusion region 6 Field oxide film 8 Electrode wiring 11, 11a Contact hole

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuyuki Shindo 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Co., Ltd. (56) References JP-A-1-128568 (JP, A) JP-A 6-252394 (JP, A) JP-A-3-203270 (JP, A) JP-A-58-186968 (JP, A)

Claims (1)

(57) [Claims] 1. The activity of a semiconductor substrate separated by an isolation insulating film.
On the channel region of the conductive region through the gate insulating film.
Silicon gate electrode is formed, the substrate surface of the active region
The source and drain regions across the channel region.
In a MOS semiconductor device in which a diffusion region is formed
A plurality of contact holes in each of the diffusion regions.
Electrode wiring is connected via the
At least one is the diffusion region and the isolation insulating film region.
Isolation insulating film formed and in the contact hole
Is removed, and at the bottom of the contact hole
An impurity diffusion layer of the same conductivity type as the source / drain region is formed.
MadeYes, In each of the source and drain regions,
Tact holes are arranged in two rows along the gate electrode,
One row is located in the active area and the other row is in the active area.
Is located at the boundary between the region and the isolation insulating film region, One in each of the source and drain regions
One contact hole in the row and the contact in the other row
The two contact holes adjacent to the
Connect the centers of the to get one contact hole in one row
Placed at the positions that make up the isosceles triangle Is
A MOS type semiconductor device characterized by the above.