JP2683554B2 - Two-phase periodic digital signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a positive-phase periodic digital signal based on a single-phase periodic digital signal and a positive-phase periodic digital signal having the same period as the single-phase periodic digital signal. The present invention relates to an improvement of a two-phase periodic digital signal generation circuit that generates a two-phase periodic digital signal composed of an opposite-phase anti-phase periodic digital signal.

[Prior art]

Conventionally, a two-phase periodic digital signal generation circuit described below with reference to FIG. 2 has been proposed. That is, the single-phase periodic digital signal A from the single-phase periodic digital signal input terminal 3 is input to generate the positive-phase periodic digital signal B having the same period as the single-phase periodic digital signal A, Positive phase periodicity digital signal output circuit 4 outputs the positive phase periodicity digital signal generation circuit 1 and single phase periodicity digital signal A from the single phase periodicity digital signal input terminal 3 Digital signal output terminal 4
And a reverse-phase periodic digital signal generation circuit 2 for generating a reverse-phase periodic digital signal C for the positive-phase periodic digital signal B output from the Have. In this case, the positive-phase periodic digital signal generation circuit 1 connects the gates to the input terminal 6, the drains to the output terminal 7, and the sources to the positive power supply terminal 8 and the negative power supply terminal 9, respectively. P-channel type MIS
It is a vertical line connection circuit with two inverters 10 and 11 configured by using a field effect transistor M1 and an n-channel type MIS field effect transistor 2. In addition, the anti-phase periodic digital signal generation circuit 2 has one inverter 12 having the same configuration as the inverters 10 and 11.
It becomes. The above is the configuration of the conventionally proposed two-phase periodic digital signal generation circuit. According to the two-phase periodic digital signal generation circuit having such a configuration, in the positive-phase periodic digital signal generation circuit 1, the single-phase periodic digital signal A input to the single-phase periodic digital signal input terminal 3 is generated. Positive logic "1" in binary display
MIS field effect transistor M1 of the inverter 10 is turned off when the level of
Turns on and the output terminal 7 is connected to the power supply terminal 9,
The output terminal 7 takes the level of negative logic "0" in the binary display, and therefore, the MIS field effect transistor M2 of the inverter 11 is turned off, but the MIS field effect transistor M1 is turned off.
Is turned on and the output terminal 7 is connected to the power supply terminal 8,
The output terminal 7, and therefore the positive-phase periodic digital signal output terminal 4 takes the level of "1" in the binary display. Further, when the single-phase periodic digital signal A input to the single-phase periodic digital signal input terminal 3 takes the level of positive logic "0" in the binary display, the MIS field effect transistor M2 of the inverter 10 is turned off. However, since the MIS field effect transistor M1 is turned on and the output terminal 7 is connected to the power supply terminal 8, the output terminal 7 takes the level of positive logic "0" in the binary display, and for this reason, the inverter 11 The MIS field-effect transistor M1 turns off, but the MIS field-effect transistor M2 turns on and the output terminal 7 is connected to the power supply terminal 9. Therefore, the output terminal 7, and hence the positive-phase periodic digital signal output terminal 4 is Takes the level of "0" in binary display. Therefore, the positive-phase periodic digital signal generation circuit 1 generates a digital signal having a periodicity with the single-phase periodic digital signal A, and outputs the digital signal to the positive-phase periodic digital signal output terminal 4 in the positive phase. It is output as a periodic digital signal B. Further, in the anti-phase periodic digital signal generation circuit 2,
When the single-phase periodic digital signal A input to the single-phase periodic digital signal input terminal 3 takes the level of "1" in the binary display, the MIS field effect transistor M1 of the inverter 12 is turned off, but the MIS field effect is Since the transistor M2 is turned on and the output terminal 7 is connected to the power supply terminal 9, the output terminal 7 and hence the anti-phase periodic digital signal output terminal 5 takes the level of "0" in binary display. Further, when the single-phase periodic digital signal A input to the single-phase periodic digital signal input terminal 3 takes the level of “0” in the binary display, the MIS field effect transistor M2 of the inverter 12 is turned off, Since the field effect transistor M1 is turned on and the output terminal is connected to the power supply terminal 8, the output terminal 7, and thus the anti-phase periodic digital signal output terminal 5 takes the level of "1" in binary display. Therefore, in the anti-phase periodic digital signal generation circuit 2, the positive-phase periodic digital signal A is output to the positive-phase periodic digital signal output terminal 4 that has the same period as that of the single-phase periodic digital signal A and is in the opposite phase. A digital signal opposite in phase to the phase periodic digital signal B is generated, and this is output to the antiphase periodic digital signal output terminal 5 as the antiphase periodic digital signal C. Therefore, according to the two-phase periodic digital signal generation circuit shown in FIG. 2, based on the single-phase periodic digital signal A, the positive-phase periodic digital signal B having the same period as that and the positive-phase periodic digital signal A two-phase periodic digital signal composed of an anti-phase periodic digital signal C having an opposite phase to B is generated and output to the outside. In this case, since the positive-phase periodic digital signal generation circuit 1 and the negative-phase periodic digital signal generation circuit 2 are both configured by using inverters having the same configuration, the positive-phase periodic digital signal B and the negative-phase periodic signal are generated. The characteristic digital signals C can be powers that are approximately equal to each other and both have the required value. In addition, each inverter constituting the positive-phase periodic digital signal generation circuit 1 and the negative-phase periodic digital signal generation circuit 2 includes a p-channel type MIS field effect transistor M1 and an n-channel type MIS field effect transistor M2. Since it is a so-called CMOS inverter configured by using two MIS field effect transistors having complementarity with each other, each inverter consumes less power, and therefore, a two-phase periodic digital signal can be generated with less power consumption. It also has the feature that

[Problems to be solved by the invention]

However, in the case of the conventional two-phase periodic digital signal generation circuit shown in FIG. 2, the positive-phase periodic digital signal generation circuit 1 is a vertical line connection circuit of the two inverters 10 and 11, while the opposite phase Since the periodic digital signal generation circuit 2 is configured by using one inverter 12, the positive-phase periodic digital signal B is exactly the opposite positive-phase periodicity to the negative-phase periodic digital signal C. It is delayed by a small amount of time from the digital signal. Therefore, when the cycle of the single-phase periodic digital signal A is long, there is no problem, but the single-phase periodic digital signal A
If the period of the signal is short, the negative-phase periodic digital signal C is obtained as a signal that can no longer be called an opposite-phase digital signal with respect to the positive-phase periodic digital signal B. . Therefore, the present invention proposes a novel two-phase periodic digital signal generation circuit without the above-mentioned drawbacks.

[Means for Solving the Problems]

The two-phase periodic digital signal generation circuit according to the present invention inputs a single-phase periodic digital signal as in the case of the conventional two-phase periodic digital signal generation circuit described above with reference to FIG.
While having a positive-phase periodic digital signal generation circuit for generating a positive-phase periodic digital signal having the same period as the single-phase periodic digital signal, the single-phase periodic digital signal is input to the positive-phase periodic digital signal. It has an anti-phase periodic digital signal generation circuit that generates an anti-phase periodic digital signal of opposite phase to the digital signal, and in this case, the positive-phase periodic digital signal generation circuit has complementarity to each other. First configured using first and second MIS field effect transistors
And a cascade connection circuit of the second inverter. However, in the two-phase periodic digital signal generation circuit according to the present invention, in the two-phase periodic digital signal generation circuit having such a configuration, both the anti-phase periodic digital signal generation circuit and the gate have the single-phase periodicity. The source and the drain are connected to an input terminal for inputting a digital signal, one of the source and the drain is connected to an output terminal for outputting the anti-phase periodic digital signal, and the other of the source and the drain is connected to the first and second sides, respectively. 1st and 2nd through resistance
Third complementary terminals connected to the power supply terminals of the
And a fourth MIS field-effect transistor, the gate of which is the middle point of connection between the third MIS field-effect transistor and the first resistor, and the middle point of connection of the fourth MIS field-effect transistor and the second resistor. And one of the source and the drain are both connected to the output terminal, and the other of the source and the drain are connected to the first and second power supply terminals, respectively. A sixth MIS field effect transistor.

[Action / Effect]

According to the two-phase periodic digital signal generation circuit of the present invention, in the positive-phase periodic digital signal generation circuit, as in the case of the conventional two-phase periodic digital signal generation circuit described above with reference to FIG. When the sex digital signal takes the level of "1" (or "0") in the binary display, the output terminal of the first inverter takes the level of "0" (or "1") in the binary display, and , Therefore, the output terminal of the second inverter is "1" (or "0") in binary display.
When the single-phase periodic digital signal takes a binary display of "0" (or "1"), the output terminal of the first inverter shows a binary display of "1" (or "0") level, and therefore, the output terminal of the second inverter is "0" (or "1") in binary display.
Therefore, a digital signal having the same period as that of the single-phase periodic digital signal is generated based on the single-phase periodic digital signal and is output as a positive-phase periodic digital signal. On the other hand, in the anti-phase periodic digital signal generation circuit, when the single-phase periodic digital signal takes the level of “1” (or “0”) in the binary display, the third and fourth MIS field effect transistors respectively The output terminal is connected to the second power supply terminal through the sixth MIS field-effect transistor because it is turned off and on, and the fifth and sixth MIS field-effect transistors are turned off and on, respectively, accordingly. When the output terminal takes a binary display of "0" (or "1") level, and the single-phase periodic digital signal takes a binary display of "0" (or "1") level, The third and fourth MIS field effect transistors are turned on and off, respectively, and accordingly, the fifth and sixth MIS are activated.
Since the field effect transistor is turned on and off respectively, the output terminal is connected to the first power supply terminal through the fifth MIS field effect transistor, so that the output terminal is "1" (or "0") in binary display. Take the level of. Therefore, in the anti-phase periodic digital signal generation circuit, an anti-phase periodic digital signal opposite in phase to the single-phase periodic digital signal is obtained at the output terminal. Therefore, the two-phase periodic digital signal generation circuit according to the present invention is also based on the single-phase periodic digital signal and has the same period as that of the conventional two-phase periodic digital signal generation circuit described in FIG. A two-phase periodic digital signal composed of a positive-phase periodic digital signal and an anti-phase periodic digital signal opposite in phase to the positive-phase periodic digital signal is generated,
Output it externally. Further, the positive-phase periodic digital signal generation circuit is configured by using an inverter as in the case of the conventional two-phase periodic digital signal generation circuit described above with reference to FIG. 2, and the inverter is a MIS field effect transistor. Configured using
In addition, the anti-phase periodic digital signal generation circuit is
Since it is composed of S field effect transistors,
As in the case of the conventional two-phase periodic digital signal generation circuit described above with reference to FIG. 2, the positive-phase periodic digital signal and the negative-phase periodic digital signal are almost equal to each other and both have the required values. Obtainable. Further, as in the case of the conventional two-phase periodic digital signal generation circuit described above with reference to FIG. 2, the inverter constituting the positive-phase periodic digital signal generation circuit has two complementary MIS field effect transistors. Constructed using
Since it is a so-called CMOS, the power consumption in the inverter is small, and also in the anti-phase periodic digital signal generation circuit, the third and fourth MIS field effect transistors are complementary to each other and have an inverse relationship to each other. Turn on and off, and also
Since the fifth and sixth MIS field effect transistors also have complementarity with each other and are turned on and off in an inverse relationship to each other, the power consumption in the anti-phase periodic digital signal generation circuit is small, and therefore, in FIG. As in the case of the conventional two-phase periodic digital signal generation circuit described above, it is possible to generate a two-phase periodic digital signal with low power consumption. However, in the case of the two-phase periodic digital signal generation circuit according to the present invention, the third and fourth MIS field effect transistors are turned on and off (or turned off and on respectively) based on the single-phase periodic digital signal, and accordingly. , Fifth
By turning on and off (or off and off) the sixth and sixth MIS field effect transistors respectively, an anti-phase periodic digital signal is obtained, and in this case, the third and fourth MIS field effect transistors The set corresponds in operation speed to the first inverter of the positive-phase periodic digital signal generation circuit, and the fifth and sixth MIS field effect transistors similarly operate in positive phase period. Since it corresponds to the second inverter of the digital digital signal generation circuit,
The anti-phase periodic digital signal is obtained as a digital signal that is exactly in anti-phase with the positive-phase periodic digital signal.

First Embodiment Next, an embodiment of a two-phase periodic digital signal generation circuit according to the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. In the two-phase periodic digital signal generation circuit according to the present invention shown in FIG. 1, instead of the anti-phase periodic digital signal generation circuit 2 being an inverter 12, both gates are supplied with the single-phase periodic digital signal A. A negative-phase periodic digital signal output terminal 5 which is connected to the single-phase periodic digital signal input terminal 3 and whose drains both output the negative-phase periodic digital signal B.
The source of which is connected to the power supply terminals 8 and 9 through the first and second resistors R1 and R2, respectively, p
It has a channel type MIS field effect transistor M3 and an n channel type MIS field effect transistor M4, and its gate has a connection midpoint between the MIS field effect transistor M3 and the resistor R1 and a connection between the MIS field effect transistor M4 and the resistor R2. A p-channel type MIS field-effect transistor M5 and an n-channel type MIS, which are connected to a midpoint, both drains of which are connected to a negative-phase periodic digital signal output terminal 5 and sources of which are connected to power supply terminals 8 and 9, respectively.
Second except that it has a field effect transistor M6
It has the same configuration as the case of the conventional two-phase periodic digital signal generation circuit described above in the figure. The above is the configuration of the embodiment of the two-phase periodic digital signal generation circuit according to the present invention. Although having such a configuration, according to the two-phase periodic digital signal generation circuit of the present invention, in the positive-phase periodic digital signal generation circuit 1, the conventional two-phase periodic digital signal generation circuit described above with reference to FIG. When the single-phase periodic digital signal A takes a binary display of "1" (or "0"), the output terminal 7 of the inverter 10 displays a binary display of "0" (or "0"). 1 "), and because of this, the output terminal 7 of the inverter 11 has a binary display of" 1 ".
(Or “0”) level, and when the single-phase periodic digital signal A takes a binary display level of “0” (or “1”), the output terminal 7 of the inverter 10 displays a binary value. Takes a level of "1" (or "0"), and because of this, the output terminal 7 of the inverter 11 has a binary display of "0".
(Or “1”) level, a digital signal having the same period as the single-phase periodic digital signal A is generated based on the single-phase periodic digital signal A, and the digital signal is output to the positive-phase periodic digital signal output terminal 4 in the positive-phase periodicity. Output as digital signal B. On the other hand, in the anti-phase periodic digital signal generation circuit 2,
When the single-phase periodic digital signal A takes the level of “1” (or “0”) in the binary display, the MIS field effect transistors M3 and M4 are turned off and on, respectively, and MI is accordingly turned on.
Since the S field effect transistors M5 and M6 are turned off and on, respectively, the antiphase periodic digital signal output terminal 5 is MIS
It is connected to the power supply terminal 9 through the field effect transistor M6, so that the anti-phase periodic digital signal output terminal 5 takes the level of "0" (or "1") in binary display. In addition, the single-phase periodic digital signal A is "0" in binary display.
(Or "1"), the MIS field effect transistors M3 and M are turned on and off, respectively, and the MIS field effect transistors M5 and M6 are turned on and off accordingly. The signal output terminal 5 is connected to the power supply terminal 8 through the MIS field effect transistor M5, so that the anti-phase periodic digital signal output terminal 5 takes the level of "1" (or "0") in the binary display. Therefore, in the anti-phase periodic digital signal generation circuit 2, the anti-phase periodic digital signal C having the opposite phase to the single-phase periodic digital signal B is obtained at the anti-phase periodic digital signal output terminal 5. Therefore, the two-phase periodic digital signal generating circuit according to the present invention shown in FIG. 1 also converts the single-phase periodic digital signal A into a single-phase periodic digital signal A as in the case of the conventional two-phase periodic digital signal generating circuit shown in FIG. On the basis of this, a two-phase periodic digital signal composed of a positive-phase periodic digital signal B having the same period as that of the positive-phase periodic digital signal B and an anti-phase periodic digital signal C having an opposite phase to the positive-phase periodic digital signal B is generated, Is output to the outside. Further, the positive-phase periodic digital signal generating circuit 1 is configured by using the inverters 10 and 11 as in the case of the conventional two-phase periodic digital signal generating circuit described above with reference to FIG. 2 is constructed using MIS field effect transistors M1 and M2, and the anti-phase periodic digital signal generation circuit 2 is similarly constructed using MIS field effect transistors M3 to M6. As in the case of the conventional two-phase periodic digital signal generation circuit described above, the positive-phase periodic digital signal B and the negative-phase periodic digital signal C are obtained with electric power that is substantially equal to each other and both have the required values. You can Further, as in the case of the conventional two-phase periodic digital signal generating circuit described above with reference to FIG. 2, the inverters 10 and 11 forming the positive-phase periodic digital signal generating circuit 1 have two complementary signals. Since it is a so-called CMOS that is configured using the MIS field effect transistors M1 and M2, the power consumption in the inverters 10 and 11 is small, and also in the anti-phase periodic digital signal generation circuit 2, the MIS field effect transistors M3 and Since M4 is complementary to each other and turns on and off in an inverse relationship to each other, and MIS field effect transistors M5 and M6 are also complementary to each other to turn on and off in an inverse relationship to each other, the reverse The power consumption in the phase-periodic digital signal generation circuit 2 is low, and therefore, as in the case of the conventional 2-phase periodic digital signal generation circuit described above with reference to FIG. It can be generated. However, in the case of the two-phase periodic digital signal generation circuit according to the present invention shown in FIG. 2, the MIS field effect transistors M3 and M4 are turned on and off (or off and on) based on the single-phase periodic digital signal A, respectively. , Accordingly, the MIS field effect transistors M5 and M6 are turned on and off (or off and on), respectively, so that the anti-phase periodic digital signal B is obtained, and in this case, MI
The set of the S field effect transistors M3 and M4 is an inverter 10 of the positive phase periodic digital signal generation circuit 1 in terms of operation speed.
In addition, since the set of MIS field effect transistors M5 and M6 also corresponds to the inverter 11 of the positive-phase periodic digital signal generation circuit 1 in terms of operating speed, the negative-phase periodic digital signal is C is obtained as a digital signal having exactly the opposite phase from the positive phase periodic digital signal B. In the above description, only one example of the present invention is shown, the above-mentioned “p-channel type” is replaced with “n-channel type”, and “n-channel type” is replaced with “p-channel type”. It is possible to reverse the polarities of the terminals 8 and 9 to the above-mentioned case and obtain the same operation and effect as the above. In addition, various modifications and changes can be made without departing from the spirit of the present invention. Let's do it.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing an embodiment of a two-phase periodic digital signal generation circuit according to the present invention. FIG. 2 is a connection diagram showing a conventional two-phase periodic digital signal generation circuit. 1 ... Positive-phase periodic digital signal generation circuit 2 ... Reverse-phase periodic digital signal generation circuit 3 ... Single-phase periodic digital signal input terminal 4 ... Positive-phase periodic digital signal output terminal 5 ... Reverse-phase period Digital signal output terminals 10, 11 …… Inverters M1 to M6 …… MIS field effect transistors R1, R2 …… Resistance

 ─────────────────────────────────────────────────── --Continued from the front page (56) References JP 62-98820 (JP, A) JP 53-139456 (JP, A) JP 62-188417 (JP, A) JP 59- 161913 (JP, A)

Claims (1)

(57) [Claims] 1. A positive-phase periodic digital signal generation circuit for inputting a single-phase periodic digital signal and generating a positive-phase periodic digital signal having the same period as the single-phase periodic digital signal; A positive-phase periodic digital signal is input, and a negative-phase periodic digital signal generation circuit that generates an opposite-phase periodic digital signal having an opposite phase to the positive-phase periodic digital signal is provided. A two-phase periodic digital signal generation circuit, in which the signal generation circuit is a cascade connection circuit of first and second inverters configured by using first and second MIS field-effect transistors that are complementary to each other, In the anti-phase periodic digital signal generation circuit, both gates are connected to an input terminal to which the single-phase periodic digital signal is input, and one of a source and a drain is the anti-phase periodic digital signal. Third and fourth complementary to each other connected to an output terminal for outputting a signal, and the other one of the source and the drain is connected to the first and second power supply terminals through the first and second resistors, respectively. Of the MIS field effect transistor and the gate are respectively connected to a connection midpoint between the third MIS field effect transistor and the first resistor and a midpoint between the fourth MIS field effect transistor and the second resistor. , One of the source and the drain is connected to the output terminal, and the other of the source and the drain is connected to the first and second power supply terminals, respectively. A two-phase periodic digital signal generation circuit having a MIS field effect transistor.