JP2684977B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a static RAM in which dummy cells are arranged around a memory cell array.

[0002]

2. Description of the Related Art A static RAM (SRAM) having a structure in which dummy cells are arranged around a memory cell array is known. FIG. 6 is a schematic plan view showing an arrangement in such a conventional SRAM. The SRAM shown in the figure has a memory cell array region 1 formed by arranging memory cells accessed by a large number of bit line pairs and word lines in the column and row directions, and surrounding the memory cell array region 1 in the peripheral portion thereof. The dummy cell region 2 is provided, and the pull-up circuit region 3 formed of pull-up transistors is provided for each bit line.

FIG. 7 exemplifies the circuit configuration of the conventional SRAM described above. In the memory cell region, a large number of memory cells 5 are arranged in columns and rows corresponding to the word lines 8 and the bit line pairs 9, 10. Each memory cell 5 includes a pair of transfer transistors (hereinafter referred to as a transistor T
(may be abbreviated as r) 15, a driver Tr 16, and a high resistance load 29, and its storage node 19
Is transferred to the corresponding word line 8 by the transfer Tr 15 which is turned on by receiving the H level of the selected word line 8.
It is connected to 10 and transmits / receives signals to / from the outside through the bit line pairs 9 and 10.

One dummy cell 6 is arranged corresponding to each bit line pair 9, 10. Each dummy cell 6 has transistors 15 and 16 having the same specifications as the regular memory cell 5 and a high resistance load 29, and has a structure in which internal wiring is partially removed at the time of manufacturing. The dummy cell 6 does not have a function as a memory cell, and is simply configured to have the same element configuration, arrangement, and shape as the regular memory cell 5.

The dummy cell 6 is generally characterized by a difference in exposure condition and etching rate between the inner memory cell and the outermost memory cell when the memory cell is arranged and formed on the semiconductor substrate by the photolithography technique. Since it is easy to cause a difference between the two, it is provided to eliminate this influence. That is, these dummy cells 6 are provided as cells that are not incorporated in the circuit for the purpose of excluding memory cells having characteristics different from those of other memory cells from the circuit. The dummy cell 6 is formed so as to have the same element configuration and wiring configuration as the normal memory cell 5 as much as possible, and the dummy cell 6 is formed not only at the ends of the bit lines 9 and 10 but also at the ends of the row and column of the memory cell. 6) is provided so as to surround it.

Each bit line 9 and 10 is further provided with a pull-up circuit 7 at its end portion. In general, the potential of the bit line pair at the time of signal reading depends on the storage signal of the memory cell selected by the word line, and one of the potentials is Vcc.
The H level is close to the potential, and the other is set to the L level, which is a slightly lower potential. During this period, the bit lines 9 and 10 are connected to the Vcc power supply only through the high resistance load 29 of the memory cell 5 and maintained at the level, so that when the charge leaks from the bit line to the GND line, The potential of the bit line may drop from the normal H level or L level and an erroneous signal may occur.

The pull-up circuit 7 is provided for the purpose of preventing a decrease in level that occurs when the bit line leaks, and the pull-up Tr 23 in the circuit is always turned on to connect the Vcc power supply line and the bit line. Are connected. In this case, the drive capability of the pull-up Tr 23 is set to an appropriate value corresponding to the H level and L level potentials of the bit lines 9 and 10, so that the pull-up Tr 23 is configured to perform the above function. It Pull-up Tr23
Are provided corresponding to the bit lines 9 and 10 as shown in the drawing, and have a circuit region having a length in the bit line direction of about 5 to 10 μm, for example.

8 and 9 are plan views showing the structures of the dummy cell 6 and the normal memory cell 5, respectively. In FIG. 9, reference numeral 8 is a polysilicon first layer forming a word line and a gate electrode of the transfer Tr, reference numerals 27 and 28 are Al wiring first layers forming a bit line, respectively, and reference numeral 32A is a transfer Tr. Sources that make up
Reference numeral 32B denotes a drain diffusion layer, and reference numeral 32B denotes a source / drain diffusion layer constituting the driver Tr. Reference numeral 24 is a direct contact that connects the diffusion layer of the driver Tr and the GND wiring forming the second polysilicon layer. The dummy cell of FIG. 8 is provided with elements and wiring layers corresponding to the element configuration and wiring layer of the normal memory cell as much as possible.

FIG. 9 shows a direct contact 21 connecting the Al first layer wirings 27 and 28 and the diffusion layer 32A of the transfer Tr, and a third layer polysilicon layer 26 constituting a Vcc power source and a high resistance load 29. Polysilicon contact 31 for connecting to diffusion layer 32A of transfer Tr
It is shown that and are formed. Further, the transfer Tr and the driver Tr have their diffusion layers connected to each other via a diffusion layer 19 in the substrate. In FIG. 8, reference numeral 13 indicates a dummy word line provided corresponding to the word line, and the other portions are indicated by the same reference numerals as those in FIG. 9 for easy understanding. The dummy cell has the circuit configuration shown in FIG. 7 because the direct contact 21 and the polysilicon contact 31 of FIG. 9 are not formed. In this way, the dummy cell is formed such that the dummy cell has a shape and arrangement similar to those of the normal memory cell, but its function does not act as the memory cell.

[0010]

In the conventional semiconductor memory device of the above type, a dummy cell region is formed on the outer periphery of the memory cell array region, and a pull-up circuit region is arranged corresponding to each bit line. Therefore, there is a drawback that the chip area is increased due to these regions associated with the memory cell array region.

In view of the above-mentioned problems of the conventional semiconductor memory device, an object of the present invention is to suppress the area of a region associated with the memory cell array region as small as possible without impairing the function of the semiconductor memory device, and thereby the chip thereof. An object of the present invention is to provide a semiconductor memory device whose area can be reduced.

[0012]

In order to achieve the above object, the present invention provides a plurality of word lines, a plurality of bit line pairs,
A plurality of memory cells, each of which is accessed by the word line and the bit pair line, each having a predetermined number of cell transistors, and a dummy transistor corresponding to the cell transistor of the memory cell, and which corresponds to at least the bit line pair. A plurality of dummy cells arranged on the outer periphery of the memory cell array, and at least one of the dummy transistors of the dummy cells corresponding to the bit line pair is a pull-up transistor that maintains the corresponding bit line at a predetermined potential. It is characterized by being configured.

[0013]

In the semiconductor memory device of the present invention, the dummy transistor in the dummy cell arranged corresponding to the bit line pair is formed as a dummy transistor having a pull-up function for maintaining the corresponding bit line at a predetermined potential. By doing so, since the functions of both the dummy transistor and the pull-up transistor are integrated into one transistor and provided in the dummy cell, the chip area thereof is smaller than that of a conventional semiconductor memory device having these transistors separately. It can be reduced.

If a dummy transistor having a pull-up function is arranged in parallel with a transfer transistor of a regular memory cell and its gate length and gate width are the same as the gate length and gate width of the cell transistor, the structure of the dummy cell is obtained. Becomes a structure closer to the structure of the regular memory cell, and the function as a dummy cell is improved.

[0015]

EXAMPLES The present invention will be described in more detail based on the examples of the present invention. FIG. 1 is a schematic plan view showing a semiconductor memory device of a first embodiment of the present invention configured as an SRAM. This SRAM has a memory cell array area 1
And a normal dummy cell region 2 which is arranged so as to surround the memory cell array region 1 in three directions, and a dummy cell region 4 with a pull-up function provided below in the drawing. As can be easily understood by comparing FIG. 1 and FIG. 6, the SRAM of this embodiment does not require an independent region for the pull-up circuit and can reduce the chip area as compared with the conventional SRAM. .

Each dummy cell in the dummy cell regions 2 and 4 has the same element structure, wiring layer structure and arrangement as the normal memory cell in the memory cell array region 1, and a part of the wiring in the normal memory cell is manufactured. It has a structure that was sometimes removed. The dummy cell does not have a function as a memory cell, is formed to have the same configuration as a regular memory cell as much as possible, and is provided so as to surround the entire outer periphery of the memory cell array region.

FIG. 2 is a circuit diagram of a memory cell array region and a dummy cell portion having a pull-up function in the semiconductor memory device of the above embodiment. The normal memory cell 5 is composed of a pair of transfer Tr 15, a driver Tr 16, and a high resistance load 29, and the storage node 19 thereof corresponds to the transfer Tr 15 which receives the H level of the selected word line 8 and becomes conductive. It is connected to the bit line pair 9 and 10 and transmits and receives signals to and from the outside through the bit line pair 9 and 10.

The dummy cell 7 with pull-up function is provided with a pull-up Tr 17 at a position corresponding to the transfer Tr 15 of the normal memory cell 5. Pull-up Tr17 is
It is arranged in parallel with the transfer Tr 15 of the normal memory cell 5 and has the same structure, that is, the same gate length, gate width and diffusion layer arrangement. The pull-up Tr 17 has its gate and drain connected to the Vcc power supply line 14 and its source connected to the bit lines 9 and 10, respectively, and is always on to connect the Vcc power supply line 14 to the bit lines 9 and 10. . In this case, the drive capacity of the pull-up Tr17 is set to the normal cell 5
The same function is achieved by forming the transfer Tr15 with the same driving capability.

FIG. 3 is a schematic plan view showing the structure of the dummy cell in the SRAM of the above embodiment. The regular memory cell has the same structure as the conventional regular memory cell shown in FIG. In these figures, for ease of understanding, the diffusion layers 32A and 32B are left slanted lines, and the polysilicon first layer 1 forming a word line or a Vcc power supply line.
3, 14 and 18 are right slanted lines, and also the third polysilicon layer 26 forming the Vcc power supply line and the high resistance load 29.
Are indicated by bold lines. The polysilicon second layer 25
Form a GND line.

Diffusion layer 32A and polysilicon first layer 14
Respectively configure the source / drain regions and the gate electrode of the pull-up Tr, and the pull-up Tr constitutes the first dummy Tr for the transfer Tr of the normal memory cell. Further, the diffusion layer 32B and the polysilicon first layer 18 form a second dummy Tr22 corresponding to the driver Tr16 of the normal memory cell 5.

In the dummy cell shown in FIG. 3, the pull-up Tr 17 forming the first dummy Tr is always on with the Vcc power supply potential supplied to its gate electrode, and is the bit line forming the Al first layers 27 and 28. , Vcc power supply line 14 is electrically connected. The difference from the normal memory cell in configuration is that the polysilicon first layers 14 and 18 are used as the Vcc power supply line, that one end of the high resistance load 29 and the node 19 are connected.
Is opened, and the diffusion layers of both the pull-up Tr and the second dummy Tr are opened, so that the cell shape and the element arrangement are exactly matched with those of the normal memory cell.

The dummy cell shown in FIG. 3 effectively exhibits its function as a dummy cell by forming a small difference in layout from the normal memory cell as described above. Further, by providing the dummy cell with a pull-up function for holding the bit line within a predetermined potential range, it is possible to reduce the SRAM chip area by eliminating the area required for the pull-up circuit which has been conventionally required. To do.

FIG. 4 and FIG. 5 respectively show the circuit configuration of the SRAM forming the semiconductor memory device of the second embodiment of the present invention.
4 is a circuit diagram similar to FIG. The regular memory cell is the same as that shown in FIG. 9 as in the first embodiment. In the SRAM of the present embodiment, the high resistance load is not formed in the portion of the normal memory cell where the high resistance load 29 is formed, and this is simply configured as the power supply branch line 26. Further, the branch line 26 is connected to the diffusion layer 32A of the pull-up Tr via the direct contact 31 to enable the same arrangement as the direct contact 31 (FIG. 9) of the normal memory cell. Therefore, the arrangement of the polysilicon first layer in the dummy cell can be made exactly the same as the arrangement of the polysilicon first layer in the normal cell.

As can be easily understood by comparing FIGS. 4 and 9, the element structure of the dummy cells and the arrangement of the wiring layers in this embodiment are extremely well matched to the element structure of the normal cells and the arrangement of the wiring layers. . The difference in structure between the two cells is that instead of the Vcc power supply line and the polysilicon third layer forming a high resistance load, this is simply configured as a power supply branch line of the polysilicon third layer, and the pull-up Tr is formed. That is, the diffusion layers of both the first dummy Tr and the second dummy Tr are not connected to each other.

As described above, in the second embodiment, the shape and the arrangement of the gate polysilicon layer in the dummy cell are exactly matched with those of the normal memory cell. Therefore, in the second embodiment, the difference in the configuration between the dummy cell and the normal memory cell can be further reduced as compared with the first embodiment, and the function as the dummy cell is further enhanced.

In the second embodiment, the polysilicon first layer of the dummy cell corresponding to the polysilicon first layer 13 formed as the word line 8 in the normal memory cell.
Although the example in which the layer 14 is configured as the Vcc power supply line has been shown, instead of this configuration, the polysilicon first layer 14 in the dummy cell corresponding to the word line is activated by the activation signal line for activating the pull-up Tr. It can also be configured as.

Further, the configuration of each of the above embodiments is merely an example, and a semiconductor memory device in which various modifications and changes are added to the configuration of each of the above embodiments is also included in the semiconductor memory device of the present invention.

[0028]

As described above, according to the semiconductor memory device of the present invention, the chip area can be reduced while maintaining the function of the conventional semiconductor memory device.

It is also possible to employ a dummy cell having a structure in which a wiring layer extremely close to the wiring layer of the normal memory cell is arranged, and the function as the dummy cell can be further improved.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a chip in a semiconductor memory device according to a first embodiment of the present invention.

2 is a circuit diagram of a memory cell array region and a dummy cell region portion with a pull-up function in the semiconductor memory device of FIG.

3 is a plan view of a dummy cell in the semiconductor memory device of FIG.

FIG. 4 is a circuit diagram of a memory cell array region and a dummy cell region with a pull-up function in a semiconductor memory device according to a second embodiment of the present invention.

5 is a plan view of a dummy cell in the semiconductor memory device of FIG.

FIG. 6 is a schematic plan view of a chip in a conventional semiconductor memory device.

FIG. 7 is a circuit diagram showing a circuit configuration of a bit line pair and a word line portion in a conventional semiconductor memory device.

FIG. 8 is a plan view of a dummy cell in a conventional semiconductor memory device.

FIG. 9 is a plan view of a normal cell in a conventional semiconductor memory device and an embodiment of the present invention.

[Explanation of symbols]

1 memory cell region 2 dummy cell region 3 pull-up circuit region 4 dummy cell region with pull-up function 5 memory cell 6 dummy cell 7 pull-up Tr 8 word line 9, 10, 27, 28 bit line 14, 18 dummy polysilicon first layer 15 transfer Tr 16 driver Tr 17 pull-up Tr 19 polysilicon first layer node 20, 21 Al-diffusion layer contact 22 dummy transistor 24 GND contact 25 GND wiring layer 26 third layer polysilicon 29 high resistance load 30 1 layer poly Silicon-diffusion interlayer contact 31 3-layer polysilicon-1 layer polysilicon contact 32A, 32B Diffusion layer

Claims (2)

(57) [Claims] 1. A semiconductor memory device comprising a plurality of word lines, a plurality of bit line pairs, and a cell array including a plurality of cells arranged in a matrix corresponding to the word lines and bit line pairs. A plurality of cells, each of which is accessed by the word line and the bit pair line, each having a plurality of memory cells each having a predetermined number of cell transistors, and a dummy transistor corresponding to each cell transistor of the memory cells; A plurality of dummy cells arranged corresponding to a pair of bit lines on the outer periphery of the cell array and simulating the shape of the memory cell, wherein at least one of the dummy transistors of the dummy cells sets the corresponding bit line to a predetermined potential. A semiconductor memory device characterized by being configured as a pull-up transistor for maintaining the same. 2. The cell transistor is composed of a transfer transistor and a driver transistor, the pull-up transistor is arranged in parallel with the transfer transistor, and a gate length and a gate length corresponding to the gate width and the gate width of the transfer transistor are provided. The semiconductor memory device according to claim 1, having a gate width.