JP2685028B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2685028B2 JP2685028B2 JP13397095A JP13397095A JP2685028B2 JP 2685028 B2 JP2685028 B2 JP 2685028B2 JP 13397095 A JP13397095 A JP 13397095A JP 13397095 A JP13397095 A JP 13397095A JP 2685028 B2 JP2685028 B2 JP 2685028B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- silicon film
- gas system
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 title description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 8
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 3
- 229910021478 group 5 element Inorganic materials 0.000 claims description 2
- 239000010408 film Substances 0.000 description 77
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 22
- 229920005591 polysilicon Polymers 0.000 description 22
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000007789 gas Substances 0.000 description 10
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 5
- 229910000077 silane Inorganic materials 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000005046 Chlorosilane Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にＣＶＤ法による高速でのシリコン膜（ポリシ
リコン膜又はアモルファスシリコン膜）の形成方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a silicon film (polysilicon film or amorphous silicon film) at a high speed by a CVD method.
【０００２】[0002]
【従来の技術】従来、バッチ式の減圧気相成長（ＬＰ−
ＣＶＤ）装置を用い、不純物として燐（Ｐ）を含むシリ
コン膜を１００〜１５０枚の半導体ウェハー（以下単に
ウェハーという）に一度に形成する場合は、シラン（Ｓ
ｉＨ4 ）とホスフィン（ＰＨ3）からなるガス系を用
い、圧力０．１〜１．０Ｔｏｒｒ，温度５００〜５８０
℃の条件で行っていた。ここで比較的低温で成膜してい
るのは、より高い温度で成膜するとバッチ内でシリコン
膜中に含まれる燐の濃度の均一性が悪化してしまうから
である。この為、成長速度は数ｎｍ／ｍｉｎ〜数十ｎｍ
／ｍｉｎと非常に遅くなる。これは、縦型の装置のスル
ープットが悪いという欠点を持つ半面、成長速度が遅い
ことで反応ガスが段部の隅々まで到達し、ほぼ１００％
の段差被覆性が得られるという利点もある。2. Description of the Related Art Conventionally, a batch type low pressure vapor deposition (LP-
When a silicon film containing phosphorus (P) as an impurity is formed at one time on 100 to 150 semiconductor wafers (hereinafter simply referred to as wafers) using a CVD apparatus, silane (S
iH 4 ) and phosphine (PH 3 ) gas system, pressure 0.1-1.0 Torr, temperature 500-580
It was conducted under the condition of ° C. The reason why the film is formed at a relatively low temperature is that if the film is formed at a higher temperature, the uniformity of the concentration of phosphorus contained in the silicon film in the batch is deteriorated. Therefore, the growth rate is several nm / min to several tens nm.
It becomes very slow with / min. This has the disadvantage that the throughput of the vertical type device is poor, but the slow growth rate causes the reaction gas to reach every corner of the step, resulting in almost 100%.
There is also an advantage that the step coverage can be obtained.
【０００３】また近年半導体ウェハーの大口径化に伴
い、枚葉式ＬＰ−ＣＶＤ装置が出現してきた。枚葉式で
は、バッチ式と異なり、その名の通り一枚一枚処理する
ので、スループットを向上させるには、高温、高速度で
成膜して、一枚あたりの処理時間を短くする必要がある
が、バッチ方式のように、バッチ内の燐濃度均一性を気
にする必要がないので、バッチ式よりも高温、高速度で
成膜することが可能である。Also, with the recent increase in the diameter of semiconductor wafers, single-wafer LP-CVD apparatuses have appeared. Unlike the batch type, the single-wafer type processes one by one as the name implies, so in order to improve throughput, it is necessary to form a film at high temperature and high speed to shorten the processing time per sheet. However, unlike the batch method, it is not necessary to pay attention to the uniformity of phosphorus concentration in the batch, so that the film can be formed at a higher temperature and a higher speed than the batch method.
【０００４】[0004]
【発明が解決しようとする課題】しかし、従来のモノシ
ランやジシラン（Ｓｉ2 Ｈ6 ）を用いたガス系で、開孔
部を有する絶縁膜上に高い成長速度（例えば６５０℃で
１００ｎｍ／ｍｉｎ以上）の成膜を行なった場合、段差
被覆性が悪くなり、図３に示すように、層間絶縁膜２に
形成したビアホール等の埋め込み時にシリコン膜６Ａに
ボイド２が発生するという問題があった。ボイドは、エ
ッチバックによってプラグを形成する際、プラグ部分の
高抵抗化、接合リークの増大、信頼性の低下等により半
導体装置に悪影響を及ぼす。However, in a conventional gas system using monosilane or disilane (Si 2 H 6 ), a high growth rate (for example, 100 nm / min or more at 650 ° C.) is formed on an insulating film having openings. 3), the step coverage deteriorates, and as shown in FIG. 3, there is a problem in that a void 2 is generated in the silicon film 6A when a via hole or the like formed in the interlayer insulating film 2 is filled. When forming a plug by etching back, the void adversely affects the semiconductor device by increasing the resistance of the plug portion, increasing junction leak, lowering reliability, and the like.
【０００５】これに対して、比較的高速で成膜しても段
差被覆性に優れるシリコンソースガスとして、ジクロロ
シラン（ＳｉＨ2 Ｃｌ2 ）が知られている。これまで、
ジクロシランは、７００〜８００℃でシリコン基板への
エピタキシャル成長などに用いられてきたが、成長する
下地の材質に依存して選択的に成長する傾向があり、半
導体装置で絶縁材として通常用いられる酸化膜上には成
長しにくい性質を持っている。無理に酸化膜上に成膜し
ようとすると、図４に示すように、たまたま形成された
核を中心にシリコン膜６Ｂの成長が起こるので、不均一
な異常成長となり、配線等の形成の為の酸化膜上へのブ
ランケット状の成膜は困難であった。On the other hand, dichlorosilane (SiH 2 Cl 2 ) is known as a silicon source gas which is excellent in step coverage even when a film is formed at a relatively high speed. Until now,
Dichlorosilane has been used for epitaxial growth on a silicon substrate at 700 to 800 ° C., but it tends to grow selectively depending on the material of the underlying layer, and it is an oxide film normally used as an insulating material in semiconductor devices. It has the property of being hard to grow on. If the film is forcibly formed on the oxide film, as shown in FIG. 4, the silicon film 6B happens to grow centering on the nuclei that are formed by chance, resulting in uneven and abnormal growth. It was difficult to form a blanket-like film on the oxide film.
【０００６】本発明の目的は、段差被覆性に優れ、かつ
高速にシリコン膜の形成が可能な半導体装置の製造方法
を提供することにある。An object of the present invention is to provide a method of manufacturing a semiconductor device which has excellent step coverage and is capable of forming a silicon film at high speed.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、モノシラン又はジシランを含む第１のガス系
を用いるＣＶＤ法により半導体基板上に第１のシリコン
膜を形成する工程と、ジクロロシランを含む第２のガス
系を用いるＣＶＤ法により前記第１のシリコン膜上に第
２のシリコン膜を形成する工程とを含むことを特徴とす
るものである。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first silicon film on a semiconductor substrate by a CVD method using a first gas system containing monosilane or disilane, and And a step of forming a second silicon film on the first silicon film by a CVD method using a second gas system containing chlorosilane.
【０００８】[0008]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１（ａ）〜（ｃ）は本発明の一実施例を
説明する為の半導体チップの断面図であり、本発明を層
間絶縁膜に設けられたコンタクトホールの埋込みをポリ
シリコン膜で行った場合を示す。尚、成膜温度を低くす
ることによりアモルファスシリコン膜を形成することも
可能である。Next, embodiments of the present invention will be described with reference to the drawings. 1 (a) to 1 (c) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention. The present invention was carried out by filling a contact hole provided in an interlayer insulating film with a polysilicon film. Indicate the case. It is also possible to form an amorphous silicon film by lowering the film forming temperature.
【０００９】まず図１（ａ）に示すように、拡散層等が
形成されたシリコン基板１上に酸化シリコン等からなる
厚さ１μｍの層間絶縁膜２を形成する。次でこの層間絶
縁膜２をパターニングし直径０．３μｍ，深さ１μｍの
コンタクトホール３を形成する。First, as shown in FIG. 1A, an interlayer insulating film 2 made of silicon oxide or the like and having a thickness of 1 μm is formed on a silicon substrate 1 on which a diffusion layer or the like is formed. Next, the interlayer insulating film 2 is patterned to form a contact hole 3 having a diameter of 0.3 μm and a depth of 1 μm.
【００１０】次に図１（ｂ）に示すように、枚葉型のＬ
Ｐ−ＣＶＤ装置を用い第１のガス系として、シラン（又
はジシラン）１００〜５００ｓｃｃｍ，水素ベース１％
のホスフィン１０〜１００ｓｃｃｍ，成膜圧力５〜５０
Ｔｏｒｒ，温度６００℃の条件で第１のポリシリコン膜
４を膜厚１０〜５０ｎｍ成膜する。この時の成膜速度は
１０〜５０ｎｍ／ｍｉｎになるようにして比較的低速度
で成膜を行い、出来るだけオーバーハング形状にならな
いようにする。この第１のポリシリコン膜４は、次に成
膜する第２のポリシリコン膜５の下地となるものであ
る。この第１のポリシリコン膜４が必要な理由は、次の
ジクロロシランによる第２のポリシリコン膜５の成膜が
選択成長する性質があり、酸化膜上には成膜しにくい為
である。この第１のポリシリコン膜を設けることで、ジ
クロロシランによる酸化膜上へのブランケット状の成膜
が可能となる。Next, as shown in FIG. 1B, a single-wafer type L
As a first gas system using a P-CVD apparatus, silane (or disilane) 100 to 500 sccm, hydrogen-based 1%
Phosphine of 10 to 100 sccm, film forming pressure of 5 to 50
The first polysilicon film 4 is formed to a thickness of 10 to 50 nm under the conditions of Torr and the temperature of 600 ° C. At this time, the film formation speed is set to 10 to 50 nm / min, and the film formation is performed at a relatively low speed so as to prevent the overhang shape as much as possible. The first polysilicon film 4 serves as a base of the second polysilicon film 5 to be formed next. The reason why the first polysilicon film 4 is necessary is that the second polysilicon film 5 formed by dichlorosilane has a property of selective growth, and is difficult to form on the oxide film. By providing this first polysilicon film, it becomes possible to form a blanket-like film on the oxide film with dichlorosilane.
【００１１】次に図１（ｃ）に示すように、第２のガス
系としてジクロロシラン１００〜５００ｓｃｃｍ，水素
ベース１％のホスフィン１０〜１００ｓｃｃｍに切り替
え、同一反応室で成膜圧力５〜５０Ｔｏｒｒ，温度７０
０〜７５０℃で第２のポリシリコン膜５を約２００ｎｍ
の膜厚に成膜する。この時成膜速度は１００〜２００ｎ
ｍ／ｍｉｎになるようにする。Next, as shown in FIG. 1 (c), the second gas system is switched to 100 to 500 sccm of dichlorosilane and 10 to 100 sccm of phosphine having a hydrogen base of 1%, and the film forming pressure is 5 to 50 Torr in the same reaction chamber. Temperature 70
The second polysilicon film 5 is about 200 nm at 0 to 750 ° C.
To a film thickness of At this time, the film forming rate is 100 to 200 n
m / min.
【００１２】図２は成長圧力１０Ｔｏｒｒ，水素ベース
１％のホスフィン流量２０ｓｃｃｍ，シラン（Ｓｉ
Ｈ4 ），ジシラン（Ｓｉ2 Ｈ6 ）及びジクロロシラン
（ＳｉＨ2Ｃｌ2 ）の流量を４００ｓｃｃｍに固定し、
成膜温度によって成膜速度を変化させた時の成膜速度
と、そのときの段差被覆性（１００％に近い程段差被覆
性がよいことを示している。）をシランによる成膜とジ
クロロシランによる成膜についてプロット、比較したも
のである。FIG. 2 shows a growth pressure of 10 Torr, a hydrogen-based 1% phosphine flow rate of 20 sccm, and silane (Si).
H 4 ), disilane (Si 2 H 6 ) and dichlorosilane (SiH 2 Cl 2 ) were fixed at a flow rate of 400 sccm,
The film-forming speed when the film-forming speed was changed according to the film-forming temperature and the step coverage at that time (the closer to 100%, the better the step coverage). 3 is a plot and a comparison of the film formation by.
【００１３】図２から分かるように、ジクロロシランに
よる成膜は同じ成長速度のシランによる成膜よりも段差
被覆性に優れるのでコンタクトホール内に出来るボイド
を最小限に抑えながら高速でポリシリコン膜を成膜する
ことが可能である。As can be seen from FIG. 2, the film formation by dichlorosilane is superior to the film formation by silane having the same growth rate in the step coverage, so that the polysilicon film can be formed at a high speed while minimizing the voids formed in the contact holes. It is possible to form a film.
【００１４】このように本実施例によれば、下地依存性
の少いガス系で第１のポリシリコン膜４を酸化膜上に形
成できる為、この上に第２のポリシリコン膜５を厚く形
成することにより、酸化膜上に配線等を形成すること
も、又溝や開孔部を段差被覆性良く埋込むことができ
る。As described above, according to the present embodiment, the first polysilicon film 4 can be formed on the oxide film by using a gas system having a small underlayer dependency, and thus the second polysilicon film 5 can be thickened on the first polysilicon film 4. By forming it, it is possible to form a wiring or the like on the oxide film and also to fill the groove or the opening with good step coverage.
【００１５】尚、上記実施例では、同一反応室内で、ガ
ス系を切り替えて成膜を行っているが、反応室を複数設
け、第１のポリシリコン膜と、第２のポリシリコン膜を
別々の反応室で成膜しても良い。成膜する装置をこのよ
うな構成にすることで、全体のスループットを向上させ
ることが可能である。In the above embodiment, the gas system is switched in the same reaction chamber to perform film formation. However, a plurality of reaction chambers are provided and the first polysilicon film and the second polysilicon film are separated. The film may be formed in the reaction chamber. By configuring the film forming apparatus with such a configuration, it is possible to improve the overall throughput.
【００１６】ただし、第１のポリシリコン膜を成膜後、
第２のポリシリコン膜を形成する反応室へのウェハーの
移動を真空中または、窒素雰囲気で行い、大気又は酸化
性の雰囲気に曝さないように行う必要がある。これは、
第１のポリシリコン膜を成膜後大気に曝すると第１のポ
リシリコン膜の表面に、自然酸化膜が形成され、第２の
ポリシリコン膜を均一に形成出来なくなってしまう為で
ある。However, after forming the first polysilicon film,
It is necessary to move the wafer to the reaction chamber for forming the second polysilicon film in vacuum or in a nitrogen atmosphere without exposing it to the air or an oxidizing atmosphere. this is,
This is because if a first polysilicon film is formed and then exposed to the atmosphere, a natural oxide film is formed on the surface of the first polysilicon film, and the second polysilicon film cannot be formed uniformly.
【００１７】又上記実施例では、不純物として５族元素
の燐をホスフィン（ＰＨ3 ）を用いて導入しているが、
アルシン（ＡｓＨ3 ）を用いてもよく、３族元素のジボ
ラン（Ｂ2 Ｈ6 ）でも良い。Further, in the above embodiment, phosphorus of the Group 5 element is introduced by using phosphine (PH 3 ) as an impurity.
Arsine (AsH 3 ) may be used, or diborane of the Group 3 element (B 2 H 6 ) may be used.
【００１８】[0018]
【発明の効果】以上説明したように本発明は、シリコン
膜の成膜を２段階に分け、第１の成膜ではシラン等下地
依存性の少ないガス系を用いて薄く成膜し、その後第２
の成膜で段差被覆性の良いジクロロシランを用いて行な
うことで、段差被覆性に優れたシリコン膜を高速に成長
させることができるという効果がある。As described above, according to the present invention, the film formation of the silicon film is divided into two stages. In the first film formation, a thin film is formed by using a gas system such as silane which has little dependency on the substrate, and then the first film formation is performed. Two
By using dichlorosilane having a good step coverage for forming the film, it is possible to grow a silicon film having an excellent step coverage at a high speed.
【図１】本発明の一実施例を説明する為の半導体チップ
の断面図。FIG. 1 is a sectional view of a semiconductor chip for explaining one embodiment of the present invention.
【図２】段差被覆性と成膜速度との関係を示す図。FIG. 2 is a diagram showing the relationship between step coverage and film formation rate.
【図３】従来例を説明する為の半導体チップの断面図。FIG. 3 is a sectional view of a semiconductor chip for explaining a conventional example.
【図４】他の従来例を説明する為の半導体チップの断面
図。FIG. 4 is a cross-sectional view of a semiconductor chip for explaining another conventional example.
１ シリコン基板 ２ 層間絶縁膜 ３ コンタクトホール ４ 第１のポリシリコン膜 ５ 第２のポリシリコン膜 ６Ａ，６Ｂ シリコン膜 ７ ボイド 1 Silicon Substrate 2 Interlayer Insulation Film 3 Contact Hole 4 First Polysilicon Film 5 Second Polysilicon Film 6A, 6B Silicon Film 7 Void
Claims (3)
ス系を用いるＣＶＤ法により半導体基板上に第１のシリ
コン膜を形成する工程と、ジクロロシランを含む第２の
ガス系を用いるＣＶＤ法により前記第１のシリコン膜上
に第２のシリコン膜を形成する工程とを含むことを特徴
とする半導体装置の製造方法。1. A step of forming a first silicon film on a semiconductor substrate by a CVD method using a first gas system containing monosilane or disilane, and a CVD method using a second gas system containing dichlorosilane. And a step of forming a second silicon film on the first silicon film.
ガス系を切り替えて第１のシリコン膜と第２のシリコン
膜を形成する請求項１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the first gas system and the second gas system are switched in the same reaction chamber to form the first silicon film and the second silicon film.
導入する不純物として３族又は５族の元素のガスを含む
請求項１又は請求項２記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein at least the second gas system contains a gas of a Group 3 or Group 5 element as an impurity introduced into the silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13397095A JP2685028B2 (en) | 1995-05-31 | 1995-05-31 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13397095A JP2685028B2 (en) | 1995-05-31 | 1995-05-31 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08330423A JPH08330423A (en) | 1996-12-13 |
| JP2685028B2 true JP2685028B2 (en) | 1997-12-03 |
Family
ID=15117341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13397095A Expired - Fee Related JP2685028B2 (en) | 1995-05-31 | 1995-05-31 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2685028B2 (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100367397B1 (en) * | 1998-12-30 | 2003-03-03 | 주식회사 하이닉스반도체 | Contact Forming Method of Semiconductor Device |
| KR20030001642A (en) * | 2001-06-25 | 2003-01-08 | 주식회사 하이닉스반도체 | Method for forming the contact plug of semiconductor device |
| KR100414564B1 (en) * | 2001-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Method of forming a contact plug in a semiconductor device |
| KR100446316B1 (en) * | 2002-03-30 | 2004-09-01 | 주식회사 하이닉스반도체 | Method for forming a contact plug in semiconductor device |
| WO2007040255A1 (en) | 2005-10-06 | 2007-04-12 | Sumco Corporation | Semiconductor substrate and method for manufacturing same |
| JP4788519B2 (en) * | 2006-08-07 | 2011-10-05 | 株式会社デンソー | Manufacturing method of semiconductor substrate |
| KR101598834B1 (en) | 2010-02-17 | 2016-03-02 | 삼성전자주식회사 | Method for manufacturing semiconductor device having contact plug |
| JP5373143B2 (en) * | 2010-04-27 | 2013-12-18 | 東京エレクトロン株式会社 | Method for manufacturing semiconductor device and method for filling contact hole and / or line |
| JP2012004542A (en) * | 2010-05-20 | 2012-01-05 | Tokyo Electron Ltd | Method and apparatus for forming silicon film |
| JP5692763B2 (en) * | 2010-05-20 | 2015-04-01 | 東京エレクトロン株式会社 | Silicon film forming method and apparatus therefor |
| JP5544343B2 (en) * | 2010-10-29 | 2014-07-09 | 東京エレクトロン株式会社 | Deposition equipment |
| JP5864668B2 (en) * | 2010-10-29 | 2016-02-17 | 東京エレクトロン株式会社 | Method for forming silicon film on object to be processed having concave portion |
| FI124354B (en) * | 2011-04-04 | 2014-07-15 | Okmetic Oyj | Method of applying one or more polycrystalline silicon layers to a substrate |
| JP5864360B2 (en) * | 2011-06-30 | 2016-02-17 | 東京エレクトロン株式会社 | Silicon film forming method and apparatus therefor |
| JP5710819B2 (en) * | 2014-03-28 | 2015-04-30 | 東京エレクトロン株式会社 | Method and apparatus for forming amorphous silicon film |
| JP6010161B2 (en) * | 2015-03-04 | 2016-10-19 | 東京エレクトロン株式会社 | Method and apparatus for forming amorphous silicon film |
| JP7601503B2 (en) * | 2020-12-16 | 2024-12-17 | 東京エレクトロン株式会社 | Semiconductor device manufacturing method and substrate processing apparatus |
-
1995
- 1995-05-31 JP JP13397095A patent/JP2685028B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08330423A (en) | 1996-12-13 |
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