JP2685032B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly to a field effect transistor for high frequency power in which a heterojunction is used for a channel and an InGaP layer is inserted as a surface protective layer, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor having a heterojunction channel as a channel usually has an electron supply layer of AlGa.
It is operated by using a two-dimensional electron gas generated at the interface between GaAs and InGaAs which is heterojunction with As.

In particular, since it is spatially separated from the donor level in the electron supply layer, it is less susceptible to electrical scattering, and high-speed operation is possible. At present, for example, it is put to practical use as a low noise element for satellite communication. Has been reached.

Recently, there is a movement to develop a field effect transistor having these heterojunctions as a channel as a field effect transistor for high frequency power.

In order to use it as a device for high frequency power, the method used for developing a low noise device must be modified. In particular, for a device for high output, it is necessary to increase the number of gate fingers and increase the gate width.

However, in order for the large output device to operate properly, uniform operation between the gate fingers is required. Further, the uniform operation of the gate fingers largely depends on the uniformity of recess formation in device formation.

FIG. 2 shows an example of a conventional recess structure in a field effect transistor having a heterojunction as a channel. Note that FIG. 2 does not show a semi-insulating substrate made of InP or GaAs on which an epitaxial structure is formed.

Referring to FIG. 2, the epitaxial structure is
Undoped GaAs or I which is the first semiconductor layer
A second electron supply layer on the nGaAs channel layer 1
The n-AlGaAs layer 2 of the semiconductor layer is provided.

Then, as an ohmic contact layer on the n-AlGaAs electron supply layer 2, an n ^--type GaAs layer 33 which is a third semiconductor layer and an n ^{+ -type} semiconductor layer which is a fourth semiconductor layer.
A GaAs layer 4 is provided.

The recess structure is formed by using the n ⁻ -GaAs layer 33 and the n ⁺ -GaAs layer 4 which are ohmic contact layers.

In the method of manufacturing the device, first, the n ⁺ -GaAs layer 4 is etched to form the first-stage recess.

Next, etching is performed to form a second-step recess smaller than the first-step recess opening width.

After that, a gate metal is formed by vapor deposition or the like so as to be embedded in the recess opening of the second stage. In this way, by embedding the gate, the influence of the surface is avoided and the device characteristics have been improved.

[0014]

As described above, by embedding the gate, the device characteristics are remarkably improved.
The shape of the recess structure largely depends on the temperature, time, and the nature of the epitaxial substrate during etching.

That is, due to the inaccuracy of the recess shape caused by the etching variation in forming the recess structure,
In particular, in a device having a large number of gate fingers for high output, there is a problem that the device characteristics largely vary and desired characteristics cannot be obtained.

Therefore, the present invention solves the above problems,
It is an object of the present invention to provide a high-frequency field effect transistor for high frequency power by using an InGaP layer in the recess forming portion.

[0017]

In order to achieve the above object, the present invention provides an electrode composed of GaAs or InGaAs.
A first semiconductor layer, which is a child traveling (channel) layer, and AlG
a second semiconductor layer which is an electron supply layer made of aAs;
A third semiconductor layer made of nGaP and a fourth semiconductor layer made of n-type GaAs are provided, and the first to fourth semiconductor layers are deposited in this order to form the fourth semiconductor layer. First recess opening penetratingly formed, second recess opening penetrating the third semiconductor layer to an upper portion of the second semiconductor layer, and embedded formation on the second recess opening. And a source electrode and a drain electrode formed on the fourth semiconductor layer, the field effect transistor.

The present invention also relates to GaAs or InGa.
Electron transit layer made of As and electrons made of AlGaAs
Supply layer, a protective layer made of InGaP, and n-type G
aAs layer, the electron transit layer, the electron supply
Layer, the protective layer, and the n-type GaAs layer are deposited in this order.
The source electrode and the source electrode formed on the n-type GaAs layer.
Through the drain electrode and the opening of the n-type GaAs layer.
Embedded in the opening provided in the InGaP layer,
A gate electrode in contact with the surface of the AlGaAs electron supply layer
A field effect transistor characterized by further comprising .

Furthermore, the present invention is characterized in that G is formed on a semi-insulating substrate.
An electron transit (channel) layer made of aAs or InGaAs, an AlGaAs electron supply layer, an InGaP layer, and an n-type GaAs layer are formed in this order, and the InG
The n-type GaA is formed at a predetermined etching selection ratio with respect to the aP layer.
The s layer is etched and opened, and the bottom of the first-stage recess is I
The surface of the nGaP layer is used as the surface of the nGaP layer, and then a photoresist for forming the recess of the second step is formed.
The P layer is etched and opened so that the bottom of the second recess is the surface of the AlGaAs electron supply layer and the gate electrode is the above I
Provided is a method for manufacturing a field effect transistor, which is formed so as to be embedded in a recess of an nGaP layer.

[0020]

The principle and operation of the present invention will be described below.

According to the present invention, by inserting the InGaP layer, the InGaP layer and the AlGaAs layer, or I
Since the buried gate structure is formed by utilizing the etching selection ratio of the nGaP layer and the GaAs layer, the recess height of the buried portion of the gate is the thickness of the inserted InGaP layer. Therefore, the recess shape can be uniquely determined with extremely high accuracy, and the height of the buried gate can be determined at the stage of the epitaxial structure. Therefore, according to the present invention, the element characteristics and the like are aligned with a high yield, and by extension, the high frequency characteristics and the like of the element are improved. Further, in the present invention, the InGaP layer acts as a surface protective layer, so that the AlGaAs electron supply layer is not oxidized,
Further, since the gate electrode is embedded in the InGaP layer, the influence of the surface exposed to the external atmosphere does not affect the channel portion, and the deterioration of device characteristics during high frequency operation is avoided.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic sectional view for explaining the structure of a field effect transistor according to an embodiment of the present invention. In FIG. 1, the semi-insulating substrate made of InP or GaAs on which the epitaxial structure is formed is not shown.

Referring to FIG. 1, the epitaxial structure is
Undoped GaAs or I which is the first semiconductor layer
On the nGaAs channel layer 1, an n-AlGaAs layer 2 as an electron supply layer which is a second semiconductor layer is provided. An n-type InGaP layer 3 which is a third semiconductor layer and an n ⁺ -GaAs layer 4 which is a fourth semiconductor layer are further provided thereon. Then, the gate electrode 7 is embedded in the InGaP layer 3.

The recess forming method according to this embodiment will be described below.

First, the fourth semiconductor layer, n ⁺ -GaA, is used.
By etching the s layer 4, a recess of the first stage is formed. At that time, the InGaP layer 3 which is the third semiconductor layer
The bottom of the recess becomes the InGaP layer 3 by performing etching having a large selection ratio with respect to.

Next, after forming the source electrode 6 and the drain electrode 7, PR (photoresist) for forming the second recess is performed.

First, the InGaP layer 3 is etched by selective etching. At this time, the bottom of the second recess is n
-It becomes the AlGaAs electron supply layer 2.

Finally, the gate electrode 7 is formed so as to be embedded in the InGaP layer 3 by vapor deposition or sputtering. Through the above steps, the buried structure shown in FIG. 1 is formed.

As a result, the recess shape is uniquely determined, so that the device characteristics and the like are aligned with a high yield. That is,
In this embodiment, the InGaP layer 3 and the n-AlGaA are used.
s electron supply layer 2 or InGaP layer 3 and n ⁺ -GaA
Since the buried gate structure is formed by using the etching selection ratio of the s layer 4, the recess height of the buried portion becomes the film thickness of the inserted InGaP, and the recess shape can be uniquely determined at the stage of the epitaxial structure. In addition, in this embodiment, the InGaP layer 3 acts as a surface protective layer,
Since the -AlGaAs electron supply layer 2 is not oxidized and the gate electrode 7 is embedded in the InGaP layer 3, the influence of the surface does not reach the channel portion and the deterioration of the device characteristics during high frequency operation is avoided.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment,
Needless to say, various modes according to the principle of the present invention are included.

[0032]

As described above, according to the present embodiment, the InGaP layer and the AlGaAs layer or the InGaP layer are formed by inserting the InGaP layer in the recess forming portion.
Since the buried gate structure is formed by using the etching selection ratio of the GaAs layer and the GaAs layer, the recess height of the buried portion is the thickness of the inserted InGaP, and the recess shape can be uniquely determined at the stage of the epitaxial structure. The characteristics and the like are uniform with a high yield, and as a result, the high-frequency characteristics and the like of the high-power element are also improved. As described above, the present invention is extremely large in that it contributes to improvement of device characteristics and high yield of a field effect transistor for high frequency power using a heterojunction for a channel.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining a configuration of a conventional field effect transistor.

[Explanation of symbols]

1 undoped InGaAs, GaAs channel layer 2 n-AlGaAs electron supply layer 3 InGaP ohmic contact layer 4 n ⁺ -GaAs ohmic contact layer 5 source electrode 6 drain electrode 7 gate electrode 33 n ^-- GaAs layer ohmic contact layer

Claims (3)

(57) [Claims] 1. An electron composed of GaAs or InGaAs
A first semiconductor layer which is a traveling (channel) layer, a second semiconductor layer which is an electron supply layer made of AlGaAs , a third semiconductor layer which is made of InGaP, and a fourth semiconductor layer which is made of n-type GaAs. And the first to fourth semiconductor layers are deposited in this order and formed, and a first recess opening formed through the fourth semiconductor layer, and the third semiconductor layer to the first recess opening. A second recess opening penetrating to the upper part of the second semiconductor layer, a gate electrode embedded in the upper part of the second recess opening, and a source electrode and a drain formed on the upper part of the fourth semiconductor layer. A field effect transistor comprising: an electrode. 2. An electron composed of GaAs or InGaAs
The electron transit layer, the electron supply layer made of AlGaAs, the protective layer made of InGaP, and the n-type GaAs layer are provided, and the electron transit layer, the electron supply layer, the protective layer, and the
The n-type GaAs layer is deposited in this order, and the source electrode and the drain formed on the n-type GaAs layer.
Through the in electrode and the opening of the n-type GaAs layer,
A gate electrode embedded in the opening provided in the InGaP layer and in contact with the surface of the AlGaAs electron supply layer is formed.
A field effect transistor characterized by further comprising . 3. GaAs or InG on a semi-insulating substrate
electron traveling (channel) layer made of aAs and AlGaA
s electron supply layer, InGaP layer, n-type GaAs layer,
Are formed in this order, the n-type GaAs layer is etched and opened at a predetermined etching selection ratio with respect to the InGaP layer, and the bottom of the recess in the first step is used as the surface of the InGaP layer. Photoresist is used, and the InGaP layer is etched by selective etching to form an opening, the bottom of the second recess is the AlGaAs electron supply layer surface, and the gate electrode is formed to be embedded in the recess of the InGaP layer. A method of manufacturing a characteristic field effect transistor.