JP2686361B2 - Data update controller - Google Patents

Description

The present invention relates to a data update control device for controlling data update when transfer data of a processor that constitutes a data processing system is updated, and a data update process temporary when a processor transfers data. For the purpose of suppressing, simplifying the data transfer process and shortening the processing time, in the data update control circuit when the processor that constitutes the data processing system updates the data to be transferred Data to be stored asynchronously with the system clock at the timing when the first system clock is turned on after the update timing is turned on, and the data of the transfer data at the time of data transfer of the data storage It is configured to include state holding means for suppressing the system clock pulse to the storage unit. You.

[Industrial applications]

The present invention relates to a data update control device for a processor when the transfer data of the processor that constitutes the data processing system is updated.

[Conventional technology]

A system clock signal common to the system is prepared for the data processing system, and data is transferred between processors or between a processor and a memory via a common bus in synchronization with the system clock pulse.

On the other hand, the data processing system has a TOD (TIM) that operates with a timing signal asynchronous with the system clock signal.
E OF DAY) and timer registers, which are used to enter the start and end times of data processing and to aggregate processing time.

[Problems to be solved by the invention]

As mentioned above, TOD and timer register data are
The data value is updated asynchronously with the system clock signal. Therefore, the data value may be updated during the transfer processing of the data in these registers to another processor or memory via the common bus, and an incorrect value may be transferred.

In order to eliminate this inconvenience, conventionally, even if the data value is updated during the data transfer process, the update process of the transfer data and the transfer of the update data are performed normally. In addition, one system clock interval was increased excessively.

Therefore, the process of providing one system clock interval for this update process becomes complicated, and the transfer time becomes longer than the normal data transfer process by the time of one system clock pulse interval to wait for the completion of the update of the data value. ,
There is a problem that the data transfer processing time increases.

The present invention simplifies the transfer data update processing by preventing the data value of the data storage portion from changing during data transfer of the data storage portion, and improves the register data update so as to shorten the transfer processing time. The purpose is to provide a circuit.

[Means for solving the problem]

The means adopted by the present invention will be described with reference to FIG.
FIG. 1 is a diagram illustrating the principle of the present invention.

In FIG. 1, reference numeral 14 denotes a data storage unit that stores data updated at a timing different from the system clock.

Reference numeral 15 is a state holding means, which suppresses a system clock pulse for updating the transfer data to the data storage unit 14 when the data is transferred from the data storage unit 14. Second
In the invention, the state holding means 15 delays the timing pulse to be updated in the data storage section 14.

[Action]

 The data value of the data storage unit 14 is updated.

The data in the data storage unit 14 is read out in synchronization with the system clock signal, while the data in the data storage unit 14 is read out and transferred to another processor.
Holds the state by delaying the pulse for suppressing or updating the system clock pulse for updating so that the data value in the data storage unit 14 is not updated.

As described above, when transferring the updated data,
Since the data update process is temporarily suppressed so that the transfer data value does not change, the data transfer process can be simplified and the data transfer process time can be shortened as compared with the conventional method.

[First Embodiment] A first embodiment of the present invention will be described with reference to FIGS. 2 to 4. FIG. 2 is an explanatory diagram of a configuration common to each embodiment of the present invention, FIG. 3 is an explanatory diagram of a state holding means and a data storage unit of the first embodiment of the present invention, and FIG. 4 is a first embodiment. It is an operation timing chart of an example.

(A) Configuration of the first embodiment In FIG. 2, a data storage unit 14 and a state holding means.
Reference numeral 15 is as described in FIG.

Reference numeral 1 is a processor, which includes a data storage unit 14 and a state holding unit 15 according to the present invention as a part of its constituent elements.

Reference numeral 2 is a transfer request processor, and in the embodiment of the present invention, it is a processor which reads out the data stored in the data storage unit 14 and issues a command to take in the self processor.

A common bus 3 is a bus for transferring data between the processor 1 and the transfer request processor.

An address buffer 11 records the address of the data sent from the transfer request processor.

Reference numeral 12 is a decoder, which codes the data recorded in the address buffer 11.

A multiplexer (MUX) 13 is connected to a plurality of registers (not shown), one of which is selected by the decode signal of the decoder 12 and connected to the gate circuit 18.

Reference numeral 16 is a stage circuit, which starts operation when a data transfer request is issued from the transfer request processor 2 to the processor 1,
The first stage signal (SPT10A), the second stage signal (SPT20A), the third stage signal (SPT30A) and the fourth stage signal (SPT40A) are transmitted in synchronization with the system clock signal (SCLK) common to the system, Each circuit in the processor 1 is caused to start operating.

Reference numerals 17 and 18 denote gate circuits, which are turned on / off to access the processor 1 to the common bus 3.

Next, the state holding means 15 and the data storage unit 14 of the first embodiment will be described with reference to FIG.

In FIG. 3, the state holding means 15 is composed of an AND circuit, and the system clock signal SCLK is suppressed by the third stage signal SPT30A of the stage circuit 16.

14b is a TOD, and the digitization of the TOD is counted up every time the TOD clock signal (TODCK) is input.

Reference numeral 14a is a register, and the data value of the TOD 14b is written in the register 14a every time the update timing pulse is output from the state holding means 15.

(B) Operation of the first embodiment When the transfer request processor 2 issues a data transfer request to the processor 1 via the common bus 3, the stage circuit 16 starts its operation.

The address sent from the transfer request processor 2 is read into the address buffer 11 during the first stage signal SPT10A from the stage circuit 16.

Address buffer 11 during the second stage signal SPT20A period
Data is decoded by the decoder 12.

With the third stage signal SPT30A, the multiplexer MUX13 operates according to the decoding result of the decoder 12, the data storage unit 14 is selected and connected to the gate circuit GII18.

The gate circuit GII18 is turned on by the fourth stage signal SPT40A to transfer the data in the data storage unit 14 to the transfer request processor 2 via the common bus 3.

Next, the operations of the data storage unit 14 and the state holding means 15 will be described with reference to FIG. In FIG.
(A) is the clock SCLK common to the system, (b) is TOD1
TOD clock TODCK that counts up 4b, (c) is TO
D14b data, (d) shows the third stage signal SPT30A, and (e) shows the data of the register 14a.

The TOD clock TODCK is asynchronous with the system clock SCLK, becomes “1” in the periods T1 to T4 and T8 to T11, and counts up the data value of the TOD 14b at the rising edge of the pulse.

Therefore, TOD data is from m to m at TODCK rising T1.
It becomes +1 and at T8, it changes from m + 1 to m + 2.

Now, it is assumed that the transfer request processor 2 requests the processor 1 to transfer the data in the data storage unit 14, the stage circuit 16 operates, and the third stage signal SPT30A is generated at T8.

Since the state holding means 15 inhibits the passage of the system clock SCLK only when SPT30A is "1", the data of the register 14a is not updated at the trailing edge of the time T8, and the same data as the time T8 is held.

The data of the register 14a at the time T2 indicates that the erroneous value X is recorded because the data of the TOD 14b is counting up at the trailing edge of the time T1.

[Second Embodiment] A second embodiment of the present invention will be described with reference to FIGS. 2 and 5 to 7. FIG. 2 is an explanatory diagram of a configuration of an embodiment of the present invention, FIG. 5 is an explanatory diagram of a state holding means and a data storage unit of the second embodiment of the present invention, and FIG. 6 is a state of the second embodiment. FIG. 7 is a diagram showing a specific example of the holding means, and FIG. 7 is an operation timing chart of the state holding means of the second embodiment.

(A) Configuration of the Second Embodiment The basic configuration of FIG. 2 is as described in the first embodiment.

Further, in FIG. 5, the data storage unit 14 and the state holding means 15 are as described in FIG. The register 14a and the TOD 14b are as described in FIG.

In the second embodiment, the state holding means 15 determines that the third stage signal SPT30A, the system clock SCLK, the signal SLTDX indicating that the data storage unit 14 has been selected, and the data read signal REGR3 of the data storage unit 14 are the same. Only TOD14
The count-up timing signal for counting up the data value of b is delayed.

Next, the state holding means 15 of the second embodiment will be described with reference to FIG.

151,152,156 are D-type flip-flops (DFF),
The state is changed by the system clock SCLK.

 Reference numerals 153, 154, 155 and 157 are AND circuits.

 Reference numeral 158 is an OR circuit.

(B) Operation of Second Embodiment The basic configuration of the present invention shown in FIG. 2 is as described in the operation of the first embodiment.

In the second embodiment, the register 14a uses the system clock S
Data of TOD14b is read in synchronization with CLK.

The data value of TOD14b is counted up by the TOD clock TODCK, but by the state holding means 15,
Only when the third stage signal SPT30A, the system clock SCLK, the signal SLTDX indicating that the data storage unit 14 has been selected, and the data read signal REGR3 of the data storage unit 14 match, the timing of counting up the data of the TOD 14b is delayed. .

The operation of the concrete example of the state holding means 15 of the second embodiment will be described below.
This will be described with reference to the drawings. In FIG. 7, (a) is the system clock signal (SCLK), and (b) is the TOD clock (TOD).
CK), (c) DFF151 output, (d) OFF152 output,
(E) is the output of the AND circuit 153, (f) is the third stage signal (SPT30A), (g) is the signal (SLTDX) indicating that the transfer data register 114 has been selected, and (h) is the data storage section 14. Data read signal (REGR3), (i) is output from AND circuit 154, (j) is output from AND circuit 155, (k) is DFF1
56 outputs, (l) is an AND circuit 157 output, and (m) is an OR circuit 158 output.

When the TOD clock (TODCK) “1” is input during the period T3 to T6 asynchronously with the system clock (SCLK), the DFF151 output outputs “1” from T4 to T6 and the DFF152 outputs T5 to T7. , And 153 output has only T4 "1"
The output will be

On the other hand, when a register read command (REGR3) is transmitted from the transfer request processor 2 to the processor 1 from T2 via a control bus (not shown), a signal (SLTDX) from the decoder 12 that selects the data storage unit 14 is transmitted from T3. 1 ”and T4
Then, the third stage signal (SPT30A) becomes "1".

Therefore, the output of the AND circuit 154 is "1" at T4, and the output of the AND circuit 153 is "1". Therefore, the output of the AND circuit 155 is "1".

Since the output of the AND circuit 155 is "1" at T4, DFF15
The output of 6 becomes "1" at T5, and the data value of TOD146 is counted up at the leading edge of T3.

When the output of AND circuit 153 is "1" at T4, SPT30A, SL
If one signal in TDX or REGR3 is “0”, that is, if the count-up of the data in the data storage unit 14 and the data read do not match, the AND circuit 154.
Output of T becomes "0" at T4, and the output of AND circuit 157 becomes
As shown by the dotted line in Fig. 7 (1), it becomes "1" at T4.

Therefore, the output of the OR circuit 158 becomes “1” at T4 and T
The data value of TOD14b is counted up at the leading edge of 4.

As described above, in the second embodiment, when the data transfer of the data storage unit 14 coincides with the count-up of the data value, the count-up of the data value is delayed by one system clock period.

[Effect] As described above, according to the present invention, when transferring data that is updated asynchronously with the system clock signal or data that is updated in synchronization with the system clock signal, the data update process is temporarily suppressed. Since the transfer data value does not change, the data transfer processing can be simplified and the data transfer processing time can be shortened as compared with the conventional method.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is an explanatory diagram of a configuration common to each embodiment of the present invention, and FIG. 3 is an explanation of state holding means and a data storage unit of the first embodiment of the present invention. 4 and FIG. 4 are operation timing charts of the first embodiment, FIG. 5 is an explanatory view of the state holding means and the data storage unit of the second embodiment of the present invention, and FIG. 6 is of the second embodiment. One specific example of the state holding means, FIG. 7 is an operation timing chart of the state holding means of the second embodiment. In FIGS. 1 to 3, 5, and 6, 1 ... Processor, 2 ... Transfer request processor, 3 ... Common bus, 11 ... Address buffer, 12 ... Decoder, 13 ... Multiplexer, 14 ... Transfer data register , 14a ... Register, 1
4b ... TOD, 15 ... state holding means, 16 ... stage circuit, 17,18
… Gate circuit, 151,152,156… D flip-flop, 1
53,154,155,157… AND circuit, 158… OR circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Koichi Odawara 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Eiji Kanaya 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 56) References JP-A-1-250133 (JP, A) JP-A-60-212554 (JP, A)

Claims (2)

(57) [Claims] 1. A data update control device for controlling update of data to be transferred in a processor constituting a data processing system, wherein: (a) update timing of transfer data to be updated is asynchronous with a system clock. A data storage section (14) which is stored at the timing when the first system clock is turned on, and (b) during data transfer of the data storage section (14), the transfer data is transferred to the data storage section (14). A data update control device comprising a state holding means (15) for inhibiting the system clock pulse. 2. The state holding means (15) is a state holding means for delaying the timing of updating the data storage section (14) instead of suppressing the system clock pulse. The data update control device according to claim 1.