JP2686438B2 - A special purpose processor and process control mechanism for offloading many operating system functions in large data processing systems. - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to special purpose processors,
And, especially in large data processing systems,
Many more that are performed by the central processor
For offloading operating system functions
It is about the processor. Description of Prior Art For Multiple Processing Systems and Multiple Programming
An adapted single processing system is a
Start disk scheduling, input / output data transmission
And dealing with external interrupts
Requires an operating system. often
Such an operator called a master control program (MCP)
The operating system is actually a lot of different specific
Processes and subroutines, each of which is specific
Has functions. Such specific processes and subs
Is resident in the main memory and
Processor or other central processor is a specific process
Or when the task is finished, the input / output operation or what
Or other central process, such as when requesting other services
When a server requests service, a particular central process
It must be executed immediately by the service provider. In particular, the operating system
Things to do in case of external interrupt, input / output operation, etc.
Allocate and deallocate elephants, and with these events
A system that implements a set of functions that may be implemented
Maintains the state of processes or tasks running on
Disk priority calculation and to various central processors
Schedule the execution of tasks by the interval timer
Maintain system timers, including some additional billing
And implement the billing function. According to statistical studies, each process in a multiprocessing system is
Operating system is a major part of processor time
Used when performing a function. From these studies,
The management function overhead like 10% and 50
Estimated to be between% and sometimes even higher
Have been. In addition, the operating system functions
A significant portion of the time that the corresponding central processor executes
Establishes process priorities and (previously defined
Function) and perform input / output operation.
Used to kill. Even these latter features are operating
Data processing system, if removed from the
System throughput will be substantially increased. Therefore, the object of the present invention is to improve the throughput.
Is to provide a data processing system having. Another object of this invention is to increase the time of the central processor.
Operating system features that require half
Improved data handling removed from system main memory
It is to provide a management system. A further object of the present invention is to use a conventional memory.
Is part of the operating system stored in
Improved data with facilities to perform the function
It is to provide a processing system. SUMMARY OF THE INVENTION In order to achieve the objectives identified above, the present invention is
Exists in a special purpose processor for type data processing systems
And that special-purpose processor is a central processor
Of the operating system stored in main memory
Central processor execution if routine is to be executed
Operating a system that will spend most of its time
Performs many of the functions of the rating system. More
Physically, the basic functions of the special purpose processor are
Process or task scheduling, and individual tasks
Task to perform individual tasks or
Influencing events to such processes or tasks
It is to allocate to. In particular, such processors may
Executable or available processes linked according to
Maintain a queue of queues, and thus
The processor is also executing a task with a higher priority
Assigned to highest priority task when there is no
To be able to be done. Special purpose processors are also new
When a task is inserted or removed from the queue
Including a mechanism for calculating the task priority. The processor of the present invention also actually co-operates with the generation of requests.
In the event specification table to be assigned to various processes
Maintains an event table where the requesting process (including MCP
Assigns a specific function or "meaning" to the event specification.
Hit it. The processor of the present invention uses the event table for such allocation.
Maintains the state of assigned events and is reassigned
(Or “waiting”) process has an event
Signal what has happened and identify those particular processes
The specific central processor assigned to run
Then allow them to proceed. Next, the feature of the present invention is that of a large-scale data processing system.
A special-purpose processor for
Are executable concatenated in the order of assigned priority
Maintain a queue of active processes and allow the central processor to
Once available, the various central processors of the system
Allow these processes to run and make requests
Assign available events to various processes with
Maintain an event allocation mechanism for BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention are illustrated in the drawings.
From the consideration of the following specification when understood together with aspects
As will be readily apparent, FIG. 1 illustrates a large data processing system using the present invention.
Figures 2A through 2D show a pushdown stack
A portion of memory containing the data to be allocated and / or
Used to access various elements in the tack
FIG. 3 is a diagram showing a plurality of display registers, and FIG. 3 is a schematic diagram of a special purpose processor of the present invention.
Figures 4A and 4B show the process table and
4 stored in the process table for a particular process
FIG. 5 is a schematic diagram of a word format, and FIGS. 5A to 5D are stored in the event table of the present invention.
FIG. 6 is a 4-word format representing an event such as that shown in FIG.
FIG. 7 is a schematic diagram illustrating an input to (ALU), and FIG. 7 shows an example of input and output of the process table of the present invention.
FIG. 8 is a schematic diagram showing, FIG. 8 is a schematic diagram of the event table support logic, and further FIGS. 9A and 9B are waiting to acquire the event.
Processes are queued according to their priority.
And the process waiting for the occurrence of the same event.
Exemplifies how the space is so connected
FIG. GENERAL DESCRIPTION OF THE INVENTION Large data processing systems using the present invention, especially multiplex systems.
The processing system is illustrated in FIG. This system
Is a plurality of main processing units 10 and one or more
Input / output processor 11, each of which is memory-controlled.
Communicates with multiple memory modules 12 via controller 12a
You can fight each other. This invention uses the controller 12a to
A task control professional that also communicates with any one of the
It is added to the system in the form of Sessa 13.
Note that the processor 10 is contrasted with the task control processor 13.
In the following description, it is also called a “main processor”. This invention is a sequential or Neumann pro
It can be used in Sessa's conventional system, but is described below.
As will be appreciated, the preferred embodiment of the present invention is a complex algorithm.
Block structure, which is a natural type for the expression of Gorythm
Programming language, that is, the declaration of nested structures
Also for systems of processors designed for the line
It is. Of such block structure, ie nesting
A specific processor designed to use a structural language
Is US Pat. No. 3,461,434 to Barton et al.
No. 3,546,677 and 3,548,384.
You. These patents refer to the stacking mechanism, ie first-in first-out
The mechanism of the particular higher level language being used.
Operators and related parameters are displayed in a manner that reflects the nesting structure.
Describes a stack-oriented data processor that handles the flow of data.
It is listed. Such languages are ALGOL and
And PL / 1, EULER, etc.
including. (Ei Organic, "Computer
System Organization ", Academic Press, 1973 (EI
Organick, Computer System Organization, Academic Pre
ss, 1973))). A system of the type described in the Burton patent mentioned above.
Is called segmented memory and stack.
Positioning around the concept of specially treated segments
Can be The processor operates on the representation stack and the operators
Take those arguments from the top of the stack and
Leave those results at the top of the hook. Running program
The data address space of the stack and concatenation of the stack
Other stacks created and descriptors contained in the stack structure
Is mapped to the data segment referenced by
You. Address environment of running codestream is stack
It consists of a set of local address spaces contained within. this
Are called activation records or lexical areas, and each
Is an address by index to the base of the activation record
It consists of a specified set of variables. That is, given day
Data item addressing is (Lambda, Delta
(Delta)) is an address pair of
, Lambda is the token of a given activation record on the stack
Level and Delta is the activated record in Level Lambda
It is the offset from the base of the mode to the variable. Star
To access any activation record in the
Each record or lexical area is
The lowest level activation level from the activation record base.
The code is linked together by a pointer. Explained first
In Burton's patent, addressing is a process
By defining an array of "display" registers in the
Optimized, these registers have level i in the array.
In a manner that includes the base of the activation record in
Be held. May reside in one of the memory modules in FIG.
A data stack that does not exist is illustrated in Figure 2A,
And its data stack is 4 at lexical levels 0 to 3
It consists of two activation records, where the top lexical record
The bell value is stored in the lexical level register of the corresponding processor.
Stored. The base message for each of the activation records.
The actual address in memory is shown in Figure 2A and these
The address is the corresponding process in the manner illustrated in Figure 2B.
Stored in the display register of the server. The activation record is played by the processor as a procedure entry.
It is made by performing arithmetic operations. Like this
Figure 2C shows that the processor currently has a different stack
In other words, it shows that it is in operation on a part with a different scale
You. As a result, the display register for a particular processor is
Must be modernized and this modernization is shown in Figure 2D
Indicated by the new contents of the display register as shown
You. Referring again to FIG. 1, the task control processor 13
Many of the most time-consuming features from a star control program
Is designed to mitigate. In the prior art, the first
Each central processor 10 in the figure
Or will be running the process. Ie it
Are working on different stacks in memory
You. For example, if a particular processor is
Execute a branch instruction that requires a branch to
If so, it notifies the master control program
Then the master control program is the requested process
And the requested process is put in a waiting state
To do. Master when the requested process ends
The control program is that the requested process has terminated
To the requesting process and the requesting process
Is activated. Another specific example of the master control program function is
External interrupt operation and input / output operation activation
As previously discussed. Moreover, with prior art systems
Master control program, which process has the highest priority
Depending on whether it has a ranking
Schedule execution of various tasks by processor 10
I do. The task control processor 13 of FIG. 1 is further detailed in FIG.
It is illustrated in detail. The two main functional elements shown there
Are process table 21 and event table 20a. Process table 21
And statistical table 20b as operated by the system of FIG.
Of all tasks or processes scheduled to
Contains information about the state. To explain the specific examples of the present invention,
At any time, there are 4K such
Tasks or processes can run. The process status information in Process Table 21 includes
Process queues or queues according to process priority
It is arranged as a linked list. During the operation of the system of Figure 1, certain processes are completed.
Removed from the linked list in Process Table 21
Sometimes and new processes are inserted.
You. In each case, the task control processor of Figure 3 is a new
Calculate priority levels and redistribute concatenated lists
Place. In this manner, the highest priority process is mandatory.
Assigned to available processor 10 in Figure 1 as needed
Always ready to be The stack is originally a physical location in main memory,
Each task or process is independent of each other.
And occupies the corresponding stack space,
The words "task", "process" and "stack"
It is clear from the description above that the terms are used synonymously.
It should be. Similarly, "stack number", "task
The terms "work number" and "process number" are used interchangeably.
The process status information shown in FIG.
This is the actual address for process table 21. Event table 20a is required by processes running in the system
To include information about the status of various event designations
Used. In the described embodiment of the invention, a maximum of 51
2K such events are available at the same time. Fig. 1
Process executed by a particular processor 10
When it is necessary to specify, it is the task control program shown in Fig. 3.
Requesting such a specified assignment from Sessa,
Control processor then unassigned event fingers.
Assigned to that process and in main memory,
It is placed on the stack of the process that needs the event specification.
Send the event token as you would. Event table 20a is next
The event information to indicate that the event was assigned.
Update information. Event token is an event for event table 20a
Address and one of the processors 10 in FIG.
Make sure you don't accidentally create an event token
Is organized from certain coded bits in order to
You. The event table 20a also shows the specific events that have already been assigned.
To maintain a linked list of various processes that require
The process used by the event and the event owns it.
When freed or released by
The highest priority process requesting the elephant
Assign the event of. As indicated above, event designations are assigned to events
It does not specify the specific function. Function assignment required
Made by the process. Event table 20a shows the event status
If it is available for allocation
Or if it happened, which process waited for it
It is for maintaining whether or not the aircraft is on board. Continuing with the description of FIG.
The event table 20a, statistical table 20b and consolidated table 20c
Not only to extract the rud, but also the information field there
It is used to insert a card. Local memory 23 is output
It acts as a buffer and also each process of FIG.
Pro 10 shows which process is currently running
Maintain the Sessa table. The message transmission to the other processor in FIG. 1 is shown in FIG.
Output register 29 via the memory controller 12a. Me
Message from controller 12a via input register 25
Package buffer 24. It's shown in Figure 3.
As such, the various functional units described in this
Arithmetic logic via logic unit input multiplexer 27
It has an input to the unit module 26. Arithmetic logic unit
Module 26 is process prioritized as previously described.
To calculate rankings, and also other processes in the system.
Used to form a message for transmission to the
Can be The clock timer 28 has an arithmetic logic module 26
(Statistics and task scheduling algorithms only
A particular process in the wait state (not
Time that can wait before it has to be restarted
Calculate how long you are waiting compared to the maximum amount of
Implemented in the arithmetic logic module 26 to help determine
Gives the time clock value. All functional units in Fig. 3 are sequence control memory
Under control of 30 and external via message buffer 24
Invoked upon receipt of a processor request, where it is required
The request command is decoded by the control memory 30. The command received from the external processor is WAIT or PROC
When it is one of the URE directives, the special purpose program of this invention is
The processor is the processor, and the processor
Different processes assigned by special purpose processors
MOVE (Transport) -STAC
Responds by transmitting a K command. This command is the third
Stored in the Figure Local Memory 23 and more fully below
The next with the highest priority for execution, as described.
Process number or stack number of the process available
Signal to the processor that made the first request.
You. The task control processor shown in FIG. 3 has various process states.
1 and each central processor 10 of FIG.
Work to control the execution of those processes by.
The process is in one of four main states:
possible. Active-currently running on the processor, ready-to run if the processor becomes available
Appropriate state, Waiting-Inoperable until some event occurs, Selected-Main processor moves to this process stack.
Commanded and there is still an acknowledgment to this directive
Not received by the task control processor. In addition, the task control processor has a
Two additional status bits, namely "Schedule"
The two bits "done" and "blocking" are maintained. Scale
Scheduled processes are included in the schedule setting mechanism.
And the process is removed from the mechanism.
The schedule is canceled when it should be done. Listed above
4 states apply only to scheduled processes
Is done. The blocked process is
For execution on the processor until
Is not scheduled. The process table 21 and statistical table 20b in FIG.
Maintain the following information for each process in. Toes
The current state of the process, that is, the state of being executable, waiting, etc.
State, process priority, cumulative processor time and
Executable time, a process that can allocate processes to it
Service, maximum allowed processor time, and process service
Information about the type of The type of process depends on the resources of the various process groups.
It is used to realize a sharing system. Task of Figure 3
The control processor is also a processor utilization system
Consumed by overall statistics and different types of processes
Maintain processor time. Attributes of these processes
Process is currently under the control of the task control processor.
With or without software, at any time
It is settable and readable. The task control process shown in Fig. 3 is performed by each main process.
Respond to the process command from the server. The SET-PRIORITY directive
Changes the priority of the specified stack to the given value
You. The SET-CLASS directive collects statistics for the specified stack
Set the classification for doing. The SET-PROCESSOR directive
Only on the specified main processor, on the specified stack
Mark that it can be performed. INSERT directive
The specified stack is included in the scheduling mechanism
And the REMOVE directive does not scale the specified stack.
To be deleted from the Joule mechanism. The above directive is
Task-based to control process scheduling
It is only a concrete example of the types of commands issued to your processor.
However, many other directives are used, but a description of them is given here.
Not needed here. The various commands described above are equivalent to their respective main processors.
Server in the codestream of the process being executed.
When a certain instruction is decoded, it is started by the main processor.
It is. The same is true for requesting event assignments during the process.
The same applies to the case. A given process or task
When requesting an elephant's assignment, this is the process
Is run by one of the main processors running
Can only be communicated to the control processor.
Will be remembered. The general nature of events has been fully explained above. Thing
Access to an elephant is specified by executing the ALLOCATE directive.
The ALLOCATE command is returned by the process
Request an event from the task control processor shown in FIG.
I do. The task control processor then selects from the event table 20a.
Generate event tokens for selected available events
And the token is at the top of the requesting process stack.
It is placed in the upper rank. Often task control processor and request
Communication with the processor depends on these event tokens
Things. In addition to the ALLCOATE function, it responds to received commands
Another function performed by the disk control processor is
Events are returned to the pool of available events
Includes DEALLOCATE and is waiting for that event
Or there is another process trying to acquire
If so, the request processor will be notified.
The PROCURE directive is currently a process running on the request processor
On behalf of, an attempt to obtain the specified event
Resulting. If the event is available, then
The event is marked as unavailable and is currently
The owner is specified as the stack number in the line. Also
If the event is not available, the process is interrupted and
Existing process base priority is at least competing
The same priority as the base priority of the process
Coordinated, and request processor rescheduled
You. The LIBERATE directive takes ownership of the specified event.
Task to the highest priority process that is trying to
It is assumed that the control processor transfers ownership of this event.
Wake up. If no such process exists
For example, the event is marked as available. The SIMPLE-WAIT command is used until the specified event occurs.
The process currently being executed by the request processor is suspended.
Let The MULTIPLE WAIT directive causes the time limit to expire or
Either when one of a set of events occurs
The requesting processor is currently executing a process
Cut off. The CAUSE directive is currently waiting for the specified event.
"Wake up" all processes. Reset option is for
Or a stack for that event
Unless it is either performing a particular function
The event is marked as having occurred. Reset option
Stack is used for the event
Is performing a particular function, the event is
Be left upright. If the event is available and
If there are competitors, the highest priority competitor is the
You are entitled. SET directive may be waiting for some event
The lagging process can be used for the event without restarting.
Mark as done. All tables in Fig. 3 are stopped and loaded by the system
Whenever it is done, it is initialized. The table after that is again
Not loaded and the task control processor has
Dependently modified from time to time. To different processes or different stacks in main memory
The allocation of the various processors 10 of FIG. 1 is shown in FIG.
Sent to each processor under control of control memory 30
Depending on the directive, each processor may have different fingers.
Causes execution to begin at the specified stack. So
After that, the control memory 30 shown in FIG.
The processor is waiting for an event as previously discussed as
Will be rescheduled when the order or acquisition order is executed
To be moved (moved to another stack). Third
The control memory 30 in the figure also shows that the processor is longer than the specified time.
If you decide that it was working on the current stack for a while,
At any time, the processor may move to another stack.
cause. DETAILED DESCRIPTION OF THE INVENTION FIG. 4 shows the case of 16K words, each of which is 17 bits.
The process table 2 in Fig. 3 which is a static RAM that is essential
It is a display of 1 organization. This RAM is as described above
Scheduling and information for 4K processes
4K pieces to give the information needed for operation
It is divided into 4 word blocks. Each 4 word block
To the 12-bit process number, as explained above.
More addressed, and it even has 4
Which of the words is addressed within the word block
Two bits are provided to select which should be done. Figure 4B shows one of the four word blocks in Figure 4A.
The format is illustrated. In WORD-0 of Figure 4B, bit 16 indicates that the process is
Selection as the head of the row ready queue (described below)
It is a selectable bit indicating that it is a candidate.
For the process to be in this state, it is scheduled
Must be present and executable, and
Must not be locked. Bits 15-12 are processes
To aggregate statistics about execution of processes by process category
Identifies the statistical classification to which the current process belongs.
Bits 11-0 are the forward links of the ready queue
And chaining executable queues in descending order of priority
Used in That is, bits 11-0 are
Next lower priority in the linked list of such processes
12-bit process number of the process table
That is, an address. WORD-1 in Figure 4B is the same as WORD-0, but with
Links 11 through 0 are now links in reverse order of the feasible matrix,
Ie the concatenation of system scheduled processes
The process of the next highest priority process in the list
The difference is that it represents a process number. In WORD-2 of Figure 4B, bit 16 is set.
If so, this process is described for WORD-3.
Executable for that particular processor
Indicates that it is at the head of the Noh queue. Of WORD-2
Bits 15-8 are the upper part of the overall process priority
And the priority is either executed by the processor or
Can be set by the task
It is operated by the control processor. Bits 7 to 0
Represents the lower part of the overall process priority, and
Used by the task control processor of the present invention
It is operated by the Turing algorithm. In WORD-3 of Figure 4B, bit 16 is set.
And the current process is scheduled on the system
Indicates whether or not. Bits 15-8 are the original of the process
Indicates the priority of the base. This is a lock race condition
The maximum time a process can fall back when it is resolved.
Is also a low base priority. Bits 7 and 6 are the current
The type of processor on which the process of the row should be run
(That is, the processor is the main processor 10 of FIG.
Or who is the input / output processor 11 of FIG.
Is a future processor type not yet realized?
Indicate). Bits 5 and 4 are waiting and can be executed
Noh, selected (as explained above), and activated
Represents a process state such as a state. Bit 3 is set
When done, indicates that the process is "blocked",
The task control processor is responsible for execution on the processor.
Do not schedule this. Bit 2 is set
And tell the processor to move to this stack number.
Move stack directive interrupts this process
Show that it should. The event table 20a in Fig. 3 shows the status of 512K events.
Including memory. As in process table 21, each of event table 20a
The memory location consists of 4 word blocks. Respectively
The general format of the word is shown in Figures 5A through 5D.
Is shown. Each block in the event table is as described above.
The event number, which is part of the event token, and the 4-word
Two other bits that specify which should be addressed.
And are addressed by. 52 of each of the 4 words
It is a bit width. FIG. 5A shows the general format of WORD-0. So
As illustrated here, there are two main points related to this disclosure.
There is a field. Bits 31-24 are explained above
The event is owned by another process for the reason
In the meantime, competing for this event, or
Shows the priority of the highest priority process trying
You. Bits 18-0 are processes that require the current event
The event number of the next lower priority event owned by
Including. Ie, this field is the owner of the current event
Before the queue of all events currently owned by
It is a link. Figure 5B shows the general format of WORD-1, WO
Similar to that of RD-0, but now with bits 18-0
Owner's queue reverse link, or ownership of current event
Of the next highest priority event owned by
They differ in that they represent event numbers. Figure 5C has two fields of particular relevance here
Represents the general format of WORD-2. Bit 35
Ishi 24 has acquired the event designation corresponding to this WORD-2.
Containing the process number Bits 11-0 are also now
Highest priority trying to take ownership of the phenomenon of
It represents the process number that represents the highest process. Figure 5D is the general format of WORD-3. this
Bit 51 of the word, when set, interrupts the current event.
Indicates that it has been assigned. Bit 50 set
Indicates that this event is available.
Bit 49, when set, has been given specific authorization
The process has taken ownership of the event,
Up from all other processes that had one ownership
It is a special bit that indicates that you have been defeated. bit
48, when set, indicates whether the event has occurred or
Indicates whether you have done it. Bit 47 is set
And any competitors or players attempting to capture this event.
Indicates that there is a process. Bit 46 is set
And there is a process waiting for this event to occur
Indicates that Two other fields related to this disclosure
Do, that is, a set of bits. Bits 19-0 are
On a list of processes waiting for an event to occur
Pointers or links, the list of which is shown in Fig. 3.
It is in consolidated table 20c. Bits 12-0 of this link are
It is the process number of the first process in the list. As explained earlier, WORD-0, 1 and 2 are basic
To a process that is waiting to acquire an event
While related, WORD-3 is basically an event designation
Is waiting for the event to occur
Related to the process. To the process that is waiting for the event
For example, at one time only one process has one event or
It should be emphasized that multiple events can be acquired
It is. However, many processes do not
If not, it may be waiting for a given event. this
For the reason, it was discussed earlier with respect to Figures 2A through 2D.
Block used in the preferred embodiment of the present invention.
It lies in the substance of a structured programming language. That is,
If you use such a block structured language,
The staggered processes are independent, but the process hierarchy
Part of the construction. Therefore, a given process
When requested and assigned, it owns the event
And its parent assigned that function.
Seth, and the parent process in turn
Are assigned specific events and functions.
Notify that. And I need that phenomenon
Put all of its sibling processes in a waiting state until an event occurs
It is. FIG. 6 shows the arithmetic logic unit module 26 of FIG.
And the arithmetic logic unit input multiplexer 27
It is a schematic diagram. In FIG. 6, arithmetic logic unit module
The tool 26 is input from the B register 41 and the accumulator 42.
And an arithmetic logic unit 40 for receiving Arithmetic logic unit
Output of 40 is either 8 bits or 1 bit around the left end
Connect it to the rotator 43 which is a shift mechanism that can shift it.
Has been continued. The output of the rotator 43 is the accumulator 42.
It is connected to the. B register 41 and accumulator
The output of 42 is also provided to output multiplexer 44. Performance
The input to the arithmetic logic unit module 26 is the operation of FIG.
Together form a logic unit input multiplexer 27,
Via successive input multiplexers 27a and 27b.
The inputs to these two multiplexers are with respect to FIG.
It was explained earlier. Figure 7 shows the inputs and outputs for Process Table 21 in Figure 3.
The force logic is illustrated. In Figure 7, the actual process table
Is a 16K x 18 bit static run (including parity)
This is the process RAM 50 that is the dumb access memory. Ad
The data and data are the arithmetic logic unit module of Fig. 3.
Received from process 26, the address is the process RAM input multi
Go to the plexer 51 directly, the data is input to the process RAM 50
Go directly to. Process RAM input multiplexer 51 computes
Logical unit module or process RAM 50 output
Choose an address from either, but it was explained earlier
So that address is a 12-bit process number.
The selected address then addresses process RAM 50
Is sent to the address counter 52 for executing. Figure 3
2 from the sequence control memory 30 to the word register 53 in FIG.
Bits may be received. These, as explained earlier
The 2 bits of each word in the particular process word block
Specifies whether the code should be selected. These two bits
Also selects the priority word for a particular process block.
It may also come from the constants that you select
Either lexer 54 is a constant or the contents of word register 53
Or choose. These two bits are then processed RA
Address Cow to make a 14-bit address to M50
Is added to the 12-bit output of interface 12. Magnitude comparator 56 is addressed in process RAM 50
The priority of the current process block is calculated according to the operation theory of FIG.
Target priority register from the processing unit module 26
Compare with the target priority received by
Work. This target priority is process RAM50
Should be inserted into the linked list of tasks maintained in
Indicates the priority of the task. The selectable task function unit 58 shown in FIG.
Process to run on any available processor
Of type enabling mask 59 to see what is enabled
Compare content and each type of process in process RAM 50
And in that case the sequence control memory of FIG.
30 is notified by the selectable task function 58. Mask system
The functional unit 60 is a process that is currently available.
Type-enabling mask to show how it can be activated
Works to set 59 different bits. Figure 8 shows the event table 20a, statistical table 20b, and consolidated table in Figure 3.
To receive data for input to 20c, and there
Support logic 22 in Figure 3 to retrieve data from
This will be illustrated in more detail. Data to and from those tables
Data transfer is performed by the arithmetic logic unit module 26 of FIG.
Or each table formed from dynamic RAM
Via a stage register 70 that can receive data from itself
You. The stage register 70 also receives data from its output.
And the three inputs are obtained by the input selection unit 71
Selected. The data is either parity or error correction code.
Check (ECC) is checked by the check / generator 7.
The stage register 70 remains on for one clock time
You. The data is then returned to the arithmetic logic unit module.
The field extraction unit 73 sends the fee for transmission.
Can be extracted or all from the stage register 70.
Output data to event table, consolidated table or statistical table respectively
Parity from check / generator 74 for transmission
Can be combined with a bit. To field extraction unit 73
The field extraction input multiplexer 72
Selected. The address for each table is the field extraction unit.
By receiving a 20-bit field from Knit 73
Generated by the address forming functional unit 75. Fig. 3
8-bit literal from sequence control store 30
Addresses the specific table to be addressed by the address forming function.
The knit 75 is notified, and the address forming functional unit 75
Next, form an appropriate address and go to the address counter 76.
Transmitted, from which the address is
Delivered to each table by Plexer 78. Address
The source multiplexer 78 comprises the tables 20a, 20b and 20 of FIG.
when the dynamic RAM in c is being refreshed
Is the address from the refresh address counter 77.
Will also choose. Figure 9A shows how to obtain an event from one process.
How ownership is transferred to the next priority process waiting for
FIG. As shown there, the event
Once available and released by its owning process,
The P head field of the constant event block WORD-2 is
The process of the next lowest priority process requiring a vote
As a pointer to the concatenation table 20c in FIG.
Used. This process as the owner then to the event
Are assigned, and the process then proceeds to FIG.
The next available processor is then the next available in FIG.
Enabled for possible processor 10. That
When a processor becomes available, it will be
You are instructed to move to the set stack number. Thing
When the elephant becomes available again, the above steps are then repeated.
It is. Figure 9B shows that the linkage table 20c in Figure 3 waits for this same event.
How it is used to connect the processes in
I will show you. As shown there, the event
And when its "done" bit is set (Fig. 3
The CAUSE directive received by the task control processor of
(Due to receipt), the WORD-3 of the particular event block
W head to specific process block in process table 21
And also the location finger to the process link in consolidation table 20c.
This behavior is used to determine the linkage table and process.
It spreads all over the table, and all pros waiting for that event.
Set for the next available processor 10 in FIG.
Enabled. Among other things, one advantage of the processor of the present invention is that
No need for interrupts, and such interrupts
Requesting device, eg input / output processor
Is the status of an event
To send a CAUSE directive to change the "currently awakened"
Thus, simply communicate to the special purpose processor of the present invention.
It is just that. Conclusion Processing of various processors in a large data processing system
Operating system functions that consume most of the processing time
A special purpose processor for offloading
Revealed. In particular, special purpose processors are
Processes or processes on various processors as they become available
Each process adapted to schedule a task
Schedule according to the priority assigned to them
Will be The special purpose processor also actually requires a demand process.
Specific to the event specification (including the operating system)
When assigning functions, various processes can be used on demand.
Maintain an event table, which is a table of event specifications to be assigned
You. The event table is then assigned to all such assignments.
To maintain the state of the event and that the event occurred
To all processes that are waiting for the event
Used for Although only one specific example of the present invention is disclosed,
Whether the spirit and scope of the invention as set forth in the claims
Changes and modifications can be made without departing from
It will be apparent to those skilled in the art.

Continuation of front page    (31) Priority claim number 787,781 (32) Priority date October 15, 1985 (33) Priority country United States (US)        Judgment number flat 7-12149 (72) Inventor Keller, John Allen               United States, 19320 Pennsylvania               Barry Gree, Koutsville, Ohio               Driven, 12                (56) References JP-A-60-114940 (JP, A)

Claims (1)

(57) [Claims] In a processing system having a plurality of central processors and at least one memory module for storing a plurality of processes to be executed by the plurality of central processors, the processes may experience various events. Otherwise it cannot complete, and the instructions for assigning events to the processes being executed by the central processors currently being executed and the executing processes are in a waiting state. Input means for receiving instructions for indicating from said certain central processor; and process table means for storing process specifications of processes, including processes that are executable and are scheduled for execution according to their assigned priorities. , Related to various events, connected to said input means, Event table means for storing state information including whether it has been assigned to a process and whether the event has occurred, coupled to the process table means, the event table means and the plurality of central processors, Output means for transmitting to the central processor an event token available to the process and then a transfer command for transferring execution to another process, and further said input means, output means, process table means and event Control means coupled to the table means for maintaining the state of the various events and the state of the process, including for decoding the commands and including whether an event is available to the process. An event assigning mechanism, wherein the control means is responsive to the decoding of commands from the plurality of central processors, A special purpose processor including a control store for a set of control signals transmitted to perform the operations of the stages and the output means. 2. A special purpose processor as claimed in claim 1, wherein said input means includes a message buffer coupled to said control store for storing processor instructions decoded by said control store. 3. In a processing system having a plurality of central processors and at least one memory module for storing a plurality of processes to be executed by the plurality of central processors, the processes may experience various events. Otherwise it cannot complete, and the instructions for assigning events to the processes being executed by the central processors currently being executed and the executing processes are in a waiting state. Input means for receiving instructions for indicating from said certain central processor; and process table means for storing process specifications of processes, including processes that are executable and are scheduled for execution according to their assigned priorities. , Related to various events, connected to said input means, Event table means for storing state information including whether it has been assigned to a process and whether the event has occurred, coupled to the process table means, the event table means and the plurality of central processors, Output means for transmitting to the central processor an event token available to the process and then a transfer command for transferring execution to another process, and further said input means, output means, process table means and event Control means coupled to the table means for maintaining the state of the various events and the state of the process, including for decoding the commands and including whether an event is available to the process. , An event assignment mechanism, wherein the event table means includes a linked list of all events assigned to a particular process. Sessa. 4. In a processing system having a plurality of central processors and at least one memory module for storing a plurality of processes to be executed by the plurality of central processors, the processes may experience various events. Otherwise it cannot complete, and the instructions for assigning events to the processes being executed by the central processors currently being executed and the executing processes are in a waiting state. Input means for receiving instructions for indicating from said certain central processor; and process table means for storing process specifications of processes, including processes that are executable and are scheduled for execution according to their assigned priorities. , Related to various events, connected to said input means, Event table means for storing state information including whether it has been assigned to a process and whether the event has occurred, coupled to the process table means, the event table means and the plurality of central processors, Output means for transmitting to the central processor an event token available to the process and then a transfer command for transferring execution to another process, and further said input means, output means, process table means and event Control means coupled to the table means for maintaining the state of the various events and the state of the process, including for decoding the commands and including whether an event is available to the process. , An event allocation mechanism, wherein the event table means stores a list of all processes that have requested to acquire each particular event A special purpose processor including connection table means for performing. 5. In a processing system having a plurality of central processors and at least one memory module for storing a plurality of processes to be executed by the plurality of central processors, the processes may experience various events. Otherwise it cannot complete, and the instructions for assigning events to the processes being executed by the central processors currently being executed and the executing processes are in a waiting state. Input means for receiving instructions for indicating from said certain central processor; and process table means for storing process specifications of processes, including processes that are executable and are scheduled for execution according to their assigned priorities. , Related to various events, connected to said input means, Event table means for storing state information including whether it has been assigned to a process and whether the event has occurred, coupled to the process table means, the event table means and the plurality of central processors, Output means for transmitting to the central processor an event token available to the process and then a transfer command for transferring execution to another process, and further said input means, output means, process table means and event Control means coupled to the table means for maintaining the state of the various events and the state of the process, including for decoding the commands and including whether an event is available to the process. , An event allocation mechanism, the event table means for all processes that are waiting for each of the allocated events to have occurred. A special purpose processor including concatenation table means for storing a list. 6. In a processing system having a plurality of central processors and at least one memory module for storing a plurality of processes to be executed by the plurality of central processors, the processes may experience various events. Otherwise it cannot complete, and the instructions for assigning events to the processes being executed by the central processors currently being executed and the executing processes are in a waiting state. Input means for receiving instructions to indicate from the central processor; process table means for storing process specifications of processes, including processes executable and scheduled to execute according to an assigned priority. Coupled to the input means, various events are An event table means for storing status information including information whether the event was assigned to a process and whether the event occurred, and coupled to the process table means, the event table means and the plurality of central processors. Output means for transmitting to the central processor event tokens available to a process and then a transfer command for transferring execution to another process, and further said input means, output means, process table means And a event control means coupled to event table means and causing the output means to transmit the requested command. The control means includes a control store for storing a set of control signals for transmission to the input means, the output means, the process table means and the event table means for performing the operations thereof. The process control mechanism according to item 6. 8. Said output means comprises as output buffer a local memory storing said transfer instruction to a new process,
The process control mechanism according to claim 6. 9. 7. The process control mechanism of claim 6 wherein said input means further comprises message buffer means for storing a plurality of commands from said plurality of central processors. 10. Further included is logic unit means coupled to the control means and the process table means for changing process state designations in the process table means as various processes change from a running state to a waiting state or a runnable state. The process control mechanism according to claim 6. 11. Further comprising priority calculation means coupled to the process table means and the control means for changing the priority of various process designations in the process table means when a new process is scheduled to be executed by the processing system. The process control mechanism according to claim 6. 12. 7. The process control mechanism according to claim 6, wherein said event table means includes a linked list of all events assigned to a particular process. 13. 7. A process control mechanism according to claim 6 wherein said event table means includes concatenation table means for storing a list of all processes that have requested to acquire each particular event. 14． 7. Process control according to claim 6, wherein said event table means comprises concatenated table means for storing a list of all processes waiting for each assigned event to have occurred. mechanism.