JP2687393B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2687393B2 JP2687393B2 JP63040098A JP4009888A JP2687393B2 JP 2687393 B2 JP2687393 B2 JP 2687393B2 JP 63040098 A JP63040098 A JP 63040098A JP 4009888 A JP4009888 A JP 4009888A JP 2687393 B2 JP2687393 B2 JP 2687393B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- silicon thin
- island
- crystal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 title description 37
- 239000010409 thin film Substances 0.000 claims description 62
- 239000013078 crystal Substances 0.000 claims description 49
- 229910052710 silicon Inorganic materials 0.000 claims description 40
- 239000010703 silicon Substances 0.000 claims description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 239000010408 film Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 24
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000137 annealing Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 239000007790 solid phase Substances 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 silicon ions Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁基板上に形成される半導体装置の製造
方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device formed on an insulating substrate.
絶縁膜上に結晶粒の大きな多結晶シリコン薄膜あるい
は、単結晶シリコン薄膜を形成する方法は、SOI（Silic
on On Insulator）技術として知られている。例えば、
固相成長法，レーザービーム再結晶化法などの方法があ
る。（参考文献応用物理 第54巻 第12号 1274ページ
1985年）また、固相成長法として、シリコン薄膜にシリ
コンイオンをイオン注入し、その後約600℃程度の低温
でアニールすると結晶成長するという方法も報告されて
いる。（参考文献 J.Appl.Phys.59（７）,1April,2422
ページ 1986年） 〔発明が解決しようとする課題〕 前記固相成長法においては、結晶成長の種となる核
が、多数存在する為に数多くの結晶粒が成長し該結晶粒
のひとつひとつは大きく成長しない。また、結晶粒がラ
ンダムに成長する為に、結晶粒界がどこに存在するのか
わからない。従って、このような従来の方法で得られた
多結晶シリコン膜を用いて薄膜トランジスタを作製する
と電気的特性のバラツキが大きく実用化できない。例え
ば、結晶粒径の大きさが２μｍ程度に成長した多結晶シ
リコン薄膜にチャネル長１μｍの薄膜トランジスタを作
製した場合を考える。従来の方法では、これまで述べて
きたように、結晶粒界がランダムに存在する為に、基板
上の場所によって、薄膜トランジスタのチャネル内に結
晶粒界が１個存在する場合と、結晶粒界がまったく存在
しない場合があり、この２つの薄膜トランジスタの電気
的特性はまったく異なる。一方、レーザービーム再結晶
化法においては、レーザービームのくり返し走査が必要
な為に大面積を一括して結晶成長させる事はむずかし
い。さらにレーザービーム内のエネルギー分布をも制御
する必要がある為大がかりで高価な装置が要求される。A method for forming a polycrystalline silicon thin film with large crystal grains or a single crystal silicon thin film on an insulating film is the SOI (Silic
On On Insulator) technology. For example,
There are methods such as solid phase growth method and laser beam recrystallization method. (References Applied Physics Volume 54 Issue 12 Page 1274
(1985) In addition, as a solid phase growth method, a method of implanting silicon ions into a silicon thin film and then annealing it at a low temperature of about 600 ° C. to perform crystal growth has been reported. (Reference J.Appl.Phys.59 (7), 1April, 2422
(Page 1986) [Problems to be solved by the invention] In the solid phase growth method, a large number of nuclei serving as seeds for crystal growth exist, so that many crystal grains grow and each of the crystal grains grows large. do not do. Further, since the crystal grains grow randomly, it is not known where the crystal grain boundaries exist. Therefore, when a thin film transistor is manufactured using a polycrystalline silicon film obtained by such a conventional method, there is a large variation in electrical characteristics, and it cannot be put to practical use. For example, consider a case where a thin film transistor having a channel length of 1 μm is formed on a polycrystalline silicon thin film having a crystal grain size of about 2 μm. In the conventional method, as described above, since the crystal grain boundaries exist at random, depending on the location on the substrate, there is one crystal grain boundary in the channel of the thin film transistor, and when there is one crystal grain boundary. It may not exist at all, and the electrical characteristics of the two thin film transistors are completely different. On the other hand, in the laser beam recrystallization method, repeated scanning of the laser beam is necessary, so that it is difficult to grow crystals over a large area at once. Further, since it is necessary to control the energy distribution in the laser beam, a large and expensive device is required.
本発明は、上記のような従来のSOI法の問題点を解決
し、絶縁基板上の所定の位置に多結晶シリコンの結晶領
域を形成させ、該結晶領域内に薄膜トランジスタなどの
半導体装置を作製し、単結晶シリコンを用いた場合と同
程度の特性の半導体装置を絶縁基板上でバラツキなく実
現する事を目的とする。非常に簡単で安価な方法で上述
のような特性のすぐれたバラツキの少ない半導体装置を
実現する事を目的とする。The present invention solves the problems of the conventional SOI method as described above, forms a polycrystalline silicon crystal region at a predetermined position on an insulating substrate, and manufactures a semiconductor device such as a thin film transistor in the crystal region. It is another object of the present invention to realize a semiconductor device having characteristics similar to those in the case of using single crystal silicon without variation on an insulating substrate. It is an object of the present invention to realize a semiconductor device having excellent characteristics as described above and having a small variation by a very simple and inexpensive method.
本発明の半導体装置の製造方法は、絶縁基板上に、シ
リコン薄膜を堆積させる第１の工程と、該シリコン薄膜
上に島状酸化膜を形成する第２の工程と、該島状酸化膜
に覆われていない該シリコン薄膜領域を酸化させる第３
の工程と、前記島状酸化膜をエッチング除去してシリコ
ン表面を露出させる第４の工程と、非晶質シリコン薄膜
を堆積させる第５の工程と、該第４の工程で露出された
シリコン表面を核とし、該非晶質シリコン薄膜を結晶成
長させて多結晶シリコン薄膜を形成する第６の工程と、
該多結晶シリコン薄膜の結晶粒界部分を除く結晶領域内
に半導体装置を形成する第７の工程を少なくとも有する
ことを特徴とする。A method of manufacturing a semiconductor device according to the present invention comprises a first step of depositing a silicon thin film on an insulating substrate, a second step of forming an island-shaped oxide film on the silicon thin film, and a step of forming the island-shaped oxide film. Third, oxidizing the uncovered area of the silicon thin film
Step, a fourth step of exposing the silicon surface by etching away the island-shaped oxide film, a fifth step of depositing an amorphous silicon thin film, and a silicon surface exposed in the fourth step. A sixth step of crystallizing the amorphous silicon thin film to form a polycrystalline silicon thin film, using as a nucleus,
At least a seventh step of forming a semiconductor device in a crystal region of the polycrystalline silicon thin film except for a crystal grain boundary portion is included.
ここでは、アクティブマトリクス基板あるいは密着型
イメージセンサーなどに本発明を用いた場合を例として
本発明の実施例を説明する。従って絶縁基板は可視光を
透過する透明性絶縁基板を用いる。第１図（ａ）におい
て、石英基板などの透明性絶縁基板１−１上に、シリコ
ン薄膜１−２を堆積させる。該シリコン薄膜１−２は結
晶性の良好な膜である事が望ましい。堆積方法として
は、EB蒸着法（Electron Beam蒸着法），スパッタ法,MB
E（Molecular Beam Epitaxy）法，常圧CVD法，プラズマ
CVD法，光励起CVD法などがある。堆積させたままでもよ
いが再結晶化させる為の熱処理工程を入れてもよい。例
えば、EB蒸着法やスパッタ法やMBE法により堆積させら
れたシリコン薄膜は、500℃から700℃の低温アニールに
より結晶粒が１〜２μｍに結晶成長する。また減圧CVD
法などで堆積させられたシリコン薄膜は、シリコンイオ
ン注入を行ないシリコン薄膜を一担非晶質化させ、その
後500℃から700℃の低温アニールすると結晶粒が１〜２
μｍに結晶成長する。またプラズマCVD法などで堆積さ
せられたシリコン薄膜は、膜中に多量の水素を含んでい
るので、300℃から450℃程度のアニールで水素を放出さ
せ、その後500℃から700℃の低温アニール１〜２μｍの
結晶粒に結晶成長させる。Here, an embodiment of the present invention will be described by taking, as an example, a case where the present invention is applied to an active matrix substrate or a contact image sensor. Therefore, a transparent insulating substrate that transmits visible light is used as the insulating substrate. In FIG. 1A, a silicon thin film 1-2 is deposited on a transparent insulating substrate 1-1 such as a quartz substrate. The silicon thin film 1-2 is preferably a film having good crystallinity. As the deposition method, EB evaporation method (Electron Beam evaporation method), sputtering method, MB
E (Molecular Beam Epitaxy) method, atmospheric pressure CVD method, plasma
The CVD method and the photo-excited CVD method are available. The deposit may be left as it is, but a heat treatment step for recrystallization may be added. For example, a silicon thin film deposited by the EB vapor deposition method, the sputtering method, or the MBE method has crystal grains grown to 1 to 2 μm by low temperature annealing at 500 ° C. to 700 ° C. Also low pressure CVD
The silicon thin film deposited by the method such as the above is subjected to silicon ion implantation to make the silicon thin film partly amorphous, and then subjected to low temperature annealing at 500 to 700 ° C.
Crystals grow to μm. In addition, since the silicon thin film deposited by the plasma CVD method contains a large amount of hydrogen in the film, hydrogen is released by annealing at about 300 ° C to 450 ° C, and then low temperature annealing at 500 ° C to 700 ° C 1 The crystal is grown to a crystal grain of ˜2 μm.
このようにして得られたシリコン薄膜１−２上に島状
酸化膜１−３を形成する。例えば減圧CVD法，常圧CVD
法，プラズマCVD法などの方法で前記シリコン薄膜１−
２上に酸化膜（SiO2）を堆積させホトリソグラフィ法で
該島状酸化膜１−３を形成する。酸化膜ではなく窒化膜
でもよいことはもちろんである。該島状酸化膜１−３ひ
とつひとつの大きさ（以後ｌと呼ぶ）と、該島状酸化膜
間の距離（以後ｘと呼ぶ）とは、本発明の目的とする結
晶性の良好な多結晶シリコン薄膜を作製する上で重要な
ファクターとなるので以降必要に応じて説明する。概略
を述べるとｌは１〜２μｍ、ｘを50μｍ程度となる。An island-shaped oxide film 1-3 is formed on the silicon thin film 1-2 thus obtained. For example, low pressure CVD method, atmospheric pressure CVD
Method, plasma CVD method, etc.
An oxide film (SiO 2 ) is deposited on the second layer 2 and the island-shaped oxide film 1-3 is formed by photolithography. Of course, a nitride film may be used instead of the oxide film. The size of each of the island-shaped oxide films 1-3 (hereinafter referred to as “l”) and the distance between the island-shaped oxide films (hereinafter referred to as “x”) are polycrystals having good crystallinity, which is the object of the present invention. Since it is an important factor in producing a silicon thin film, it will be described below as necessary. The outline is that l is 1 to 2 μm and x is about 50 μm.
次に熱酸化を行ない、前記シリコン薄膜１−２におい
て島状酸化膜１−３におおわれていない領域をすべて酸
化膜とする。このように形成された酸化膜をここではフ
ィールド酸化層１−４と呼ぶ。一方、シリコン薄膜１−
２において、島状酸化膜１−３におおわれていた領域
は、島状シリコン薄膜１−５として残る。前記フィール
ド酸化層１−４の形成方法としては乾燥酸素中で700℃
から1400℃に加熱するdry酸化法，酸化速度のより速い
方法としては水蒸気を導入して加熱するWet酸化法など
の方法がある。これらの熱酸化は、フィールド酸化層が
透明性絶縁基板表面に達するまで行なう。従って、この
工程まで終了した基板はほぼ透明となっており、透明性
絶縁基板として扱っても何ら問題はない。また、島状酸
化膜１−３の部分は、くぼんだ形状となっている。一
方、熱酸化工程は上述したように高温熱処理であるの
で、前記島状シリコン薄膜１−５は、前工程での状態と
比べてさらに結晶化が進んでいる。Next, thermal oxidation is performed to make all the regions of the silicon thin film 1-2 not covered by the island-shaped oxide film 1-3 as oxide films. The oxide film thus formed is referred to as a field oxide layer 1-4 here. On the other hand, silicon thin film 1-
In 2, the region covered with the island-shaped oxide film 1-3 remains as the island-shaped silicon thin film 1-5. The method for forming the field oxide layer 1-4 is 700 ° C. in dry oxygen.
The dry oxidation method of heating from 1 to 1400 ° C, and the Wet oxidation method of introducing steam for heating are the methods with a faster oxidation rate. These thermal oxidations are performed until the field oxide layer reaches the surface of the transparent insulating substrate. Therefore, the substrate completed up to this step is almost transparent, and there is no problem even if it is handled as a transparent insulating substrate. Further, the island-shaped oxide film 1-3 has a concave shape. On the other hand, since the thermal oxidation step is the high temperature heat treatment as described above, the island-shaped silicon thin film 1-5 is further crystallized as compared with the state in the previous step.
続いて基板表面の酸化膜をエッチングして、島状酸化
膜１−３を除去し、島状シリコン薄膜１−５の表面１−
６を露出させる。この工程まで終了した時の基板の状態
を第１図（ｄ）に示す。島状シリコン薄膜の表面１−６
が清浄に保たれているうちに非晶質シリコン薄膜１−７
を堆積させる。該非晶質シリコン薄膜１−７は、膜質が
均一であることが望ましい。堆積方法としては、前にも
述べたように、EB蒸着法，スパッタ法,MBE法，減圧CVD
法，常圧CVD法，プラズマCVD法，光励起CVD法などの方
法がある。いずれの方法においても堆積温度を高くする
と小さな結晶粒の存在する多結晶となってしまうので高
くても700℃以下としたほうがよい。水素が膜中に含ま
れないという点でEB蒸着法，スパッタ法,MBE法などが有
効である。その他の方法で堆積し膜中に水素が含まれて
いる場合は350℃から400℃の低温アニールで水素をゆっ
くりと放出させる。Subsequently, the oxide film on the surface of the substrate is etched to remove the island-shaped oxide film 1-3, and the surface 1- of the island-shaped silicon thin film 1-5.
Expose 6 The state of the substrate at the end of this process is shown in FIG. Surface of island-shaped silicon thin film 1-6
Amorphous silicon thin film 1-7
Deposit. It is desirable that the amorphous silicon thin film 1-7 have uniform film quality. As described above, the EB deposition method, the sputtering method, the MBE method, and the low pressure CVD are used as the deposition method.
Methods, atmospheric pressure CVD method, plasma CVD method, photo-excited CVD method and so on. In any of the methods, if the deposition temperature is increased, a polycrystal having small crystal grains is formed. The EB evaporation method, sputtering method, MBE method, etc. are effective in that hydrogen is not contained in the film. When the film is deposited by other methods and contains hydrogen, the hydrogen is slowly released by low temperature annealing at 350 ° C to 400 ° C.
続いて、前記島状シリコン薄膜１−５を結晶成長の核
として、該非晶質シリコン薄膜１−７を結晶成長させ
る。前記島状シリコン薄膜１−５は、前に述べたように
大きさｌが１〜２μｍで、結晶粒径が１〜２μｍである
ので、該島状シリコン薄膜１−５には結晶粒界がまった
く含まれないか、あるいは多くても１個含まれるだけで
ある。結晶成長は島状シリコン薄膜１−５に重なってい
る部分を中心として放射状にすすむ。そして島状シリコ
ン薄膜１−５間の中間点で両方向から成長してきた結晶
粒がぶつかり合い、結晶粒界１−８が生じる。結晶粒の
成長は100μｍ程度に達する。従って前記島状シリコン
薄膜１−５の間の距離ｘを100μｍ以下にしておけば、
前記島状シリコン薄膜１−５と結晶粒界１−８との間の
領域は完全な結晶領域１−９となる。結晶粒の成長が10
0μｍ以上に達成される場合にはｘをさらに大きくする
事ができ、より大きな結晶領域を実現できる。結晶成長
の方法は、500℃から700℃の低温アニールで、前記島状
シリコン薄膜１−５を核として結晶成長させる。一種の
固相エピタキシャル成長ということもできる。非晶質シ
リコン薄膜１−７を堆積させた状態で結晶成長させても
よいが、該非晶質シリコン薄膜１−７上に酸化膜などを
キャッピングしてから結晶成長させる事も考えられる。
この場合は結晶領域１−９の表面の平担性を保つ点で効
果がある。もちろん結晶成長後、該酸化膜は除去しても
よいし、あるいはその後作製する半導体装置の一部とし
て利用してもよい。Then, the amorphous silicon thin film 1-7 is crystal-grown using the island-shaped silicon thin film 1-5 as a nucleus for crystal growth. Since the island-shaped silicon thin film 1-5 has a size 1 of 1 to 2 μm and a crystal grain size of 1 to 2 μm as described above, the island-shaped silicon thin film 1-5 has crystal grain boundaries. It is not included at all, or at most one is included. Crystal growth proceeds radially around a portion overlapping the island-shaped silicon thin film 1-5. Then, at the intermediate point between the island-shaped silicon thin films 1-5, the crystal grains grown from both directions collide with each other to form a crystal grain boundary 1-8. The growth of crystal grains reaches about 100 μm. Therefore, if the distance x between the island-shaped silicon thin films 1-5 is set to 100 μm or less,
The region between the island-shaped silicon thin film 1-5 and the crystal grain boundary 1-8 becomes a complete crystal region 1-9. 10 grain growth
When it is 0 μm or more, x can be further increased, and a larger crystal region can be realized. The method of crystal growth is low temperature annealing at 500 ° C. to 700 ° C. to grow crystals using the island-shaped silicon thin film 1-5 as a nucleus. It can also be said to be a kind of solid phase epitaxial growth. Crystal growth may be performed in the state where the amorphous silicon thin film 1-7 is deposited, but it is also possible to cap the oxide film on the amorphous silicon thin film 1-7 and then perform crystal growth.
In this case, it is effective in maintaining the flatness of the surface of the crystal region 1-9. Of course, after the crystal growth, the oxide film may be removed or may be used as a part of a semiconductor device manufactured thereafter.
このようにして島状シリコン薄膜１−５と結晶粒界１
−８との間に形成された結晶領域１−９の部分を利用し
て半導体装置を作製する。核となる島状シリコン薄膜１
−５には多くても１個の結晶粒界しか含まれないので、
本発明において半導体装置を作製する点において何ら問
題にならない。本実施例においては薄膜トランジスタを
作製する場合を例として説明する。結晶領域１−９の中
にホトリソグラフィ法により単結晶能動領域１−10をパ
ターニングし、続いてゲート酸化膜１−11を形成する。
ゲート酸化膜は熱酸化法で形成する。その後多結晶シリ
コンなどでゲート電極１−12を形成し該ゲート電極１−
12をマスクとして、ソース及びドレイン領域１−13を形
成する。Ｐチャネルの場合はＢ（ポロン）Ｎチャネルの
場合は、Ｐ（リン）,As（ヒ素）を不純物添加する。添
加方法としてはイオン注入法あるいは拡散法などがあ
る。次に層間絶縁膜１−14として酸化膜あるいは窒化膜
を堆積させ、コンタクトホールを形成して金属電極１−
15を形成する。In this way, the island-shaped silicon thin film 1-5 and the grain boundaries 1
A semiconductor device is manufactured by utilizing the portion of the crystal region 1-9 formed between the crystal region 1 and −8. Island-shaped silicon thin film 1 serving as a nucleus
Since -5 includes at most one grain boundary,
In the present invention, there is no problem in manufacturing a semiconductor device. In this embodiment, a case where a thin film transistor is manufactured will be described as an example. A single crystal active region 1-10 is patterned in the crystal region 1-9 by photolithography, and subsequently a gate oxide film 1-11 is formed.
The gate oxide film is formed by a thermal oxidation method. After that, a gate electrode 1-12 is formed of polycrystalline silicon or the like, and the gate electrode 1-12 is formed.
Source and drain regions 1-13 are formed using 12 as a mask. In the case of P channel, B (poron) and in the case of N channel, P (phosphorus) and As (arsenic) are added as impurities. Examples of the addition method include an ion implantation method and a diffusion method. Next, an oxide film or a nitride film is deposited as an interlayer insulating film 1-14, a contact hole is formed, and a metal electrode 1-
Form 15.
実施例では薄膜トランジスタの場合を例にとって説明
したが、バイポーラ型トランジスタなどその他の半導体
装置にももちろん応用することができる。In the embodiment, the case of a thin film transistor has been described as an example, but the present invention can be applied to other semiconductor devices such as a bipolar transistor.
種結晶の上に非晶質シリコン薄膜を堆積し、該非晶質
シリコン薄膜を低温で固相成長させることができるので
絶縁基板、特に石英基板のような透明性絶縁基板上にほ
ぼ単結晶に近いシリコン薄膜を作成することができる。
結晶粒界の位置及び結晶領域の位置を基板上所定の場所
に形成することができるので、結晶領域のみを用いて半
導体装置を作製することができ、単結晶シリコン薄膜を
用いた半導体装置と同等の特性が得られる。Since an amorphous silicon thin film can be deposited on a seed crystal and the amorphous silicon thin film can be solid-phase grown at a low temperature, it is almost a single crystal on an insulating substrate, particularly a transparent insulating substrate such as a quartz substrate. Silicon thin films can be created.
Since the position of the crystal grain boundary and the position of the crystal region can be formed at predetermined positions on the substrate, a semiconductor device can be manufactured using only the crystal region, which is equivalent to a semiconductor device using a single crystal silicon thin film. The characteristics of are obtained.
本発明を薄膜トランジスタに応用すれば、ドライバー
回路を同一基板内に作り込んだアクティブマトリクス基
板の高速化が実現できる。さらに電源電圧の低減、消費
電流の低減、信頼性の向上に関しても大きな効果があ
る。If the present invention is applied to a thin film transistor, it is possible to realize high speed of an active matrix substrate in which a driver circuit is built in the same substrate. Further, it has a great effect on reduction of power supply voltage, reduction of current consumption, and improvement of reliability.
本発明を、光電変換素子とその走査回路を同一チップ
内に集積した密着型イメージセンサーに応用した場合に
は、読み取り速度の高速化、高解像度化、及び階調を取
る場合に非常に大きな効果を生み出す。電源電圧の低
減、消費電流の低減、信頼性の向上にも効果は大きい。
高解像度化が達成されるとカラー読み取り用密着型イメ
ージセンサーへの応用も容易となる。When the present invention is applied to a contact-type image sensor in which a photoelectric conversion element and its scanning circuit are integrated in the same chip, a very large effect is obtained when the reading speed is increased, the resolution is increased, and gradation is obtained. Produce. It is also very effective in reducing power supply voltage, reducing current consumption, and improving reliability.
When a higher resolution is achieved, application to a contact image sensor for color reading becomes easier.
レーザービーム照射装置などの精巧で高価な装置を必
要としないので、作製が簡単であり、費用の低減化に役
だつ。Since elaborate and expensive equipment such as laser beam irradiation equipment is not required, it is easy to manufacture and helps to reduce costs.
以上述べたように、本発明は、絶縁基板特に透明性絶
縁基板上に単結晶シリコン薄膜を作製する場合に、非常
に有効なものである。As described above, the present invention is very effective when a single crystal silicon thin film is formed on an insulating substrate, especially a transparent insulating substrate.
第１図（ａ）から（ｇ）は、本発明における半導体装置
の製造方法を示す工程図である。 １−３……島状酸化膜 １−４……フィールド酸化層 １−５……島状シリコン薄膜 １−６……島状シリコン薄膜の表面 １−８……結晶粒界 １−９……結晶領域FIGS. 1A to 1G are process diagrams showing a method for manufacturing a semiconductor device according to the present invention. 1-3 ... Island oxide film 1-4 ... Field oxide layer 1-5 ... Island silicon thin film 1-6 ... Surface of island silicon thin film 1-8 ... Crystal grain boundary 1-9. Crystal region
Claims (1)
第１の工程と、該シリコン薄膜上に島状酸化膜を形成す
る第２の工程と、該島状酸化膜に覆われていない該シリ
コン薄膜領域を酸化させる第３の工程と、前記島状酸化
膜をエッチング除去してシリコン表面を露出させる第４
の工程と、非晶質シリコン薄膜を堆積させる第５の工程
と、該第４の工程で露出されたシリコン表面を核とし、
該非晶質シリコン薄膜を結晶成長させて多結晶シリコン
薄膜を形成する第６の工程と、該多結晶シリコン薄膜の
結晶粒界部分を除く結晶領域内に半導体装置を形成する
第７の工程を少なくとも有することを特徴とする半導体
装置の製造方法。1. A first step of depositing a silicon thin film on an insulating substrate, a second step of forming an island oxide film on the silicon thin film, and a step not covered with the island oxide film. A third step of oxidizing the silicon thin film region and a fourth step of exposing the silicon surface by etching away the island-shaped oxide film
Step, a fifth step of depositing an amorphous silicon thin film, and the silicon surface exposed in the fourth step as a nucleus,
At least a sixth step of crystal-growing the amorphous silicon thin film to form a polycrystalline silicon thin film and a seventh step of forming a semiconductor device in a crystalline region of the polycrystalline silicon thin film excluding a crystal grain boundary portion. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63040098A JP2687393B2 (en) | 1988-02-23 | 1988-02-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63040098A JP2687393B2 (en) | 1988-02-23 | 1988-02-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01214110A JPH01214110A (en) | 1989-08-28 |
| JP2687393B2 true JP2687393B2 (en) | 1997-12-08 |
Family
ID=12571392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63040098A Expired - Fee Related JP2687393B2 (en) | 1988-02-23 | 1988-02-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2687393B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6323071B1 (en) | 1992-12-04 | 2001-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a semiconductor device |
| US6997985B1 (en) | 1993-02-15 | 2006-02-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor, semiconductor device, and method for fabricating the same |
| US20090078940A1 (en) * | 2007-09-26 | 2009-03-26 | Sharp Laboratories Of America, Inc. | Location-controlled crystal seeding |
| US7947523B2 (en) * | 2008-04-25 | 2011-05-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing photoelectric conversion device |
| US8338218B2 (en) * | 2008-06-26 | 2012-12-25 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device module and manufacturing method of the photoelectric conversion device module |
-
1988
- 1988-02-23 JP JP63040098A patent/JP2687393B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01214110A (en) | 1989-08-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6399429B1 (en) | Method of forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device | |
| US4808546A (en) | SOI process for forming a thin film transistor using solid phase epitaxy | |
| JPH02140915A (en) | Manufacturing method of semiconductor device | |
| JP2982792B2 (en) | Method for manufacturing thin film transistor | |
| US4868140A (en) | Semiconductor device and method of manufacturing the same | |
| JP2687393B2 (en) | Method for manufacturing semiconductor device | |
| JPH08102543A (en) | Crystallization method and thin film transistor manufacturing method using the same | |
| JPH03215391A (en) | Method for growth of crystal | |
| JPS6158879A (en) | Preparation of silicon thin film crystal | |
| JP2638868B2 (en) | Method for manufacturing semiconductor device | |
| JP2687394B2 (en) | Method for manufacturing semiconductor device | |
| JP2720473B2 (en) | Thin film transistor and method of manufacturing the same | |
| JP2867402B2 (en) | Method for manufacturing semiconductor device | |
| JP2707654B2 (en) | Method for manufacturing thin film transistor | |
| JP2707632B2 (en) | Method for manufacturing semiconductor device | |
| JP2876598B2 (en) | Method for manufacturing semiconductor device | |
| JP2766315B2 (en) | Semiconductor manufacturing method | |
| JPH01216519A (en) | Manufacture of semiconductor device | |
| JP2505764B2 (en) | Method for forming single crystal semiconductor thin film | |
| JPS59134819A (en) | Manufacture of semiconductor substrate | |
| KR100379685B1 (en) | Planarization method of silicon layer | |
| JPH0786601A (en) | Polycrystalline silicon MOS transistor and manufacturing method thereof | |
| JP2503626B2 (en) | Method of manufacturing MOS field effect transistor | |
| JPH01220820A (en) | Manufacturing method of semiconductor device | |
| JPS63236310A (en) | Semiconductor device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |