JP2690640B2 - Missing clock detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting clock loss in a system composed of a plurality of unit devices driven according to a clock distributed and supplied from a clock distribution device.

In recent years, information processing apparatuses have improved processing capabilities,
Inside, there are a large number of unit-unit devices (collectively referred to as “unit devices”) that perform various operations. Each unit device is driven generally in synchronization with the clock distributed and supplied by the clock distribution device. But,
When a clock is missing in a certain unit device and the clock is lost, the synchronization between the unit devices is lost, which causes the operation of the information processing device. Therefore, when a clock is missed in any of the unit devices, a detection circuit that strictly detects the clock is required.

[0003]

2. Description of the Related Art As a known conventional example, a "clock synchronization deviation detection method" proposed by the present applicant (Japanese Patent Laid-Open No. 61-984).
25) FIG. 5 is a diagram showing the conventional example. In FIG. 5, the clock distribution device 50 distributes the clock generated by the oscillator 53 by the distributor 54 and supplies the clock to the two unit devices 51 and 52. In each of the unit devices 51 and 52, the clock phase adjusting circuit 5 that absorbs the phase difference due to the difference in the length of the clock distribution line
5, 56 generate clocks of the same phase between the unit devices 51, 52.

In accordance with this clock, in the respective unit devices 51 and 52, the respective adders 57 and 58 add the values of the respective counters 59 and 60. The decoder 61 of the unit device 51 inputs the value of the counter 59 and outputs a synchronization signal. The decoder 62 of the unit device 52 operates according to the control signal output from the flip-flop 63, and when the input value of the counter 60 does not reach the expected value, the flip-flop 64 is set and the clock omission occurs. Let me know. Further, the flip-flop 63 that receives the synchronization signal outputs a signal that resets the counter 60 in order to synchronize the next addition operation.

FIG. 6 is a timing chart for explaining the circuit operation shown in FIG. In FIG. 6, the counters 59 and 60 of the respective unit devices 51 and 52 are
It is a 2-bit counter. As shown in FIG. 6, the value of the 2-bit counter changes in the order of “00” → “01” → “10” → “11” → “00” → ... In synchronization with the clock. The synchronization signal output by the unit device 51 is turned on when the value of the counter 59 reaches “11”.

The flip-flop 63 of the unit device 52 which receives the synchronization signal turns on the control signal for controlling the decoder 62 at the next clock when the synchronization signal is turned on. When the control signal is turned on, the decoder 62
It is checked whether the value of the counter 60 is "11". If it is not "11", the output is turned on to notify that the clock omission has occurred. Further, the counter 60 is reset at the next clock when the control signal is turned on, and starts the adding operation again.

[0007]

In FIG. 6, the clock omission of the unit device 51, which occurs at the timing indicated by the letter Ta, appears in the output of the decoder 62 of the unit device 52 at the timing indicated by the letter Tb. It can be seen from FIG. 6 that the “clock synchronization deviation detection method” correctly detects a clock loss. However, if there is an asynchronous reset signal generated at an arbitrary timing in a certain unit device, this conventional example has a problem that a clock omission is erroneously detected.

When the asynchronous reset is applied, the counter value of the unit device becomes the initial value of zero. On the other hand, the counters of the other unit devices continue the adding operation regardless of the asynchronous reset. Therefore, the synchronization of the counter held between the unit device to which the asynchronous reset is applied and the other unit device is lost. At this time, the value of the counter of the unit device on the side receiving the synchronization signal does not reach the expected value even if the clock is normal, so that the clock omission is erroneously detected.

In view of the above-mentioned conventional problems, the present invention strictly detects a clock loss so as not to erroneously detect a clock loss even if any unit device is reset asynchronously. It is intended to improve the reliability of a processing device.

[0010]

According to the invention, the above-mentioned object is achieved by the means described in the claims. That is, the present invention provides a plurality of unit devices that operate in synchronization with the clock supplied by the clock distribution device ,
It is provided for each of the multiple unit devices and is the same as the clock.
A counter of the same cycle that performs addition in time,
The counter of any of the unit devices
Signal indicating the value of and the counter of other unit device
The counter signal that indicates the value of
If a signal is present, the corresponding unit device and other
There was a missing clock with the unit device
Output from the comparator circuit and an external asynchronous reset
When the comparison is performed, the comparison operation by the comparison circuit is
Reset detection circuit that outputs a valid signal to pause
And a road.

[0011]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, a clock distribution device 1 distributes a clock generated by an oscillator 4 by a distributor 5 and supplies the clock to the two unit devices 2 and 3. In each of the unit devices 2 and 3, the clock phase adjustment circuits 6 and 7 that absorb the phase difference due to the difference in the lengths of the clock distribution lines generate clocks of the same phase between the unit devices 2 and 3.

In accordance with this clock, the counters 8 and 9 in each unit device 2 and 3 perform addition operation. The value indicated by the counter 8 of the unit device 2 is sent to the unit device 3 as a counter signal. The value indicated by the counter 9 is used as one input signal of the comparison circuit 16 and the other input signal is compared as the count signal. The unit device 2 is provided with a reset detection circuit 10 that detects an asynchronous reset.

The reset detection circuit 10 turns off the valid signal when it detects an asynchronous reset. This valid signal is
The unit device 2 sends it to the unit device 3. In the unit device 3, the series of flip-flops 11 to 14 that receive the counter signal and the valid signal sent by the unit device 2 are means for transmitting the counter signal, means for synchronizing the counter 9 with the counter 8, and comparison. It is a means for controlling the circuit 16. The comparison circuit 16 operates by a control signal generated based on the valid signal, and does not perform comparison when the valid signal is turned off due to the asynchronous reset. Flip-flop 1
Reference numeral 5 is a register for storing the comparison result of the comparison circuit 16. When the value of the counter 8 and the value of the counter 9 do not match, the comparison circuit 16 detects missing clock,
The flip-flop 15 stores the detection result.

[0014]

FIG. 2 is a diagram showing an embodiment of the present invention. 3 and 4 are timing charts for explaining the operation of the circuit shown in FIG. FIG. 3 shows a case where a clock dropout occurs, and FIG. 4 shows a case where an asynchronous reset is applied. The embodiment shown in FIG. 2 will be described below with reference to FIGS. 3 and 4.

In FIG. 2, the clock distribution device 20 distributes the clock generated by the oscillator 23 by the distributor 24 and supplies the clock to the two unit devices 21 and 22. In each of the unit devices 21 and 22, clock phase adjustment circuits 25 and 26 that absorb the phase difference due to the difference in the lengths of the clock distribution lines generate clocks of the same phase between the unit devices 21 and 22.

In accordance with this clock, each unit device 2
Counters 27 and 28 in 1 and 22 perform addition operation.
The counter 27 and the counter 28 are 1-bit counters, and the values thereof change like “0” → “1” → “0” → “1” → ... Counter 27 is flip-flop 3
2 and the counter 28 has an AND circuit 35 and a flip-flop 36. The output of the counter 27 becomes the input of the flip-flop 29 and is sent to the unit device 22 as a counter signal with a delay of one clock. As shown in FIGS. 3 and 4, the counter signal is turned on when the counter 27 indicates “1”, but is turned off at the timing of first indicating “1”. Similarly, the valid signal has a timing of 1 being turned on by the flip-flop 30.
It is behind the clock.

Reset detection circuit 31 of the unit device 21
Has one of its inputs as the output of the flip-flop 30, forming a loop. Therefore, as shown in FIG. 4, the unit at the timing indicated by the letter marks T _X device 2
1. The flip-flop that constitutes the counter 27 provided in FIG.
Asynchronous reset signal is input to groups 32, 29, 30
And the valid signal is delayed by one clock after the counter signal.
It indicates that it is set and turns off. During this time, the clock is "H".
The counter 27 alternately outputs "0" and "1".
Stops the returning addition operation and outputs "0" continuously .

In the unit device 22, the counter signal sent from the unit device 21 is processed by the four-stage flip-flops 37 to 40, and this is used as one input of the comparison circuit 33. Then, the value of the counter 28 is used as the other input, and the values of the two counters 27 and 28 are compared. In FIG. 3, since the comparison results do not match at the timings indicated by the letters Tb and Td, the clock dropout error is detected. This error occurs when the flip-flop 34
Is stored.

Comparing circuit 33 performs a comparing operation according to the control signal output from latch 48. When the control signal is on, the comparison circuit 33 does not perform the comparison operation and its output is invalid. On the other hand, when the control signal is off, a comparison operation is performed, and when a clock loss error is detected as a result of the comparison, on is output to notify the clock loss error. The latch 48 is a four-stage flip-flop 41 to 44 that processes the valid signal sent from the unit device 21.
In addition, the control signal is generated based on the output signal of the circuit configured by the three AND circuits 45 to 47. As shown in FIGS. 3 and 4, the control signal is turned on for two clocks from the timing when the valid signal changes from off to on. While the control signal is on, the comparison operation of the comparison circuit 33 is suppressed, so that even if the values of the two counters 27 and 28 do not match, the clock missing error is not detected.

In FIG. 3, the missing clock generated in the unit device 22 at the timing indicated by the letter Ta is indicated by the letter T.
It is correctly detected at the timing indicated by b. Further, the clock omission occurring in the unit device 21 at the timing indicated by the letter Tc is correctly detected at the timing indicated by the letter Td. In FIG. 4, it is shown that the clock reset error is not erroneously detected by the asynchronous reset generated in the unit device 21 at the timing indicated by the letter Tx. Conventionally, at the timing indicated by the letter Ty, the clock loss error is turned on as shown by the wavy line, and the clock loss error was erroneously detected.

[0021]

As described above, according to the present invention,
It is possible to strictly detect a clock missing error. Therefore, even if an asynchronous reset is input to any one of the plurality of unit devices, there is an effect that a clock missing error is not erroneously detected, and the reliability of the information processing system is improved. There is a big contribution.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a timing chart illustrating the operation of the circuit shown in FIG.

FIG. 4 is a timing chart illustrating the operation of the circuit shown in FIG.

FIG. 5 is a diagram showing a conventional example.

6 is a timing chart illustrating the operation of the circuit shown in FIG.

[Explanation of symbols]

1,20,50 Clock distribution device 2,3,21,22,51,52 Unit device 4,23,53 Oscillator 5,24,54 Distributor 6,7,25,26,55,56 Clock phase adjustment circuit 8 , 9, 27, 28, 59, 60 Counter 10, 31 Reset detection circuit 11-15, 29, 30, 32, 34, 36-44, 6
3,64 Flip-flop 16,33 Comparison circuit 35,45-47 AND circuit 48 Latch 57,58 Adder 61,62 Decoder

Claims (1)

(57) [Claims] 1. A plurality of unit devices of the clock distribution device operates in synchronism with a clock supplied, provided in each of the plurality of unit devices the clock
A counter of the same cycle for performing the addition in synchronization with, and a unit device in front of an arbitrary unit device of the plurality of unit devices.
Counter signal indicating counter value and other unit device
No comparison by comparing with the counter signal indicating the counter value of
If there is a counter signal of
A clock drop may occur between the device and another unit device.
If a comparator circuit that outputs a signal indicating that there is an asynchronous reset is applied from the outside, the comparator circuit
Outputs an effective signal to pause the comparison operation for a certain time
And a reset detection circuit for
Unplugged detection circuit.