JP2692838B2 - Image processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a digital printer and a digital facsimile, and in particular, multi-level image data representing image information is input and converted into binary data. Image processing apparatus.

[Conventional technology]

Conventionally, as a binarization method for reproducing halftones in digital printers, digital facsimiles, etc.,
There is a dither method that uses a dither matrix whose threshold value varies periodically. In this method, the number of gradations that can be expressed is limited by the dither matrix. For example, when the number of gradations is about 16 gradations, there is a drawback that a pseudo contour is generated in an output image. In addition, 2 which has been receiving attention recently
As a binarization method, there is a method called an error diffusion method in which an error generated in the binarization process is dispersed to surrounding pixels. This technique,
In 1975 by Floid and Steinberg, “An Adaptive Algori
It was proposed in a paper called thm for Spatial Gray Scale "SID DIGEST", and it is a method superior in both resolution and gradation to the dither method.

[Problems to be solved by the invention]

However, according to the above method, in the highlight part of the image where the density of the original is low, there is a part where dots are not hit at all, and dots appear close to each other in the reproduced image after that part, and they are connected in a line. However, there is a drawback that the quality of the image is remarkably deteriorated.

That is, when the low image density portion is binarized by the error diffusion method, the positive error diffused in the surroundings at the time of binarization is small, and thus the positive error gathered in the target pixel is also small. As a result, the density of the pixel of interest does not easily exceed the threshold for binarization (usually 127), and a portion where no dot is generated occurs. Then, since the error is diffused to a plurality of pixels, once a pixel exceeding the threshold value occurs, dots continuously occur.

The present invention eliminates the above-mentioned drawbacks of the prior art, prevents white spots and dot connection in the highlight portion of an image,
It is an object of the present invention to provide an image processing device capable of obtaining a high quality reproduced image.

[Means for solving the problem]

In order to achieve the above-mentioned object, the present invention provides an image processing apparatus for inputting multi-valued level image data representing image information and converting it into binary data, by forming dots in a binarized region composed of a plurality of pixels. A detection unit that detects whether or not there is binary data to be turned on, and a variation width depending on the level of the input image data when the detection unit detects that there is no binary data to turn on the dot. The data obtained by adding the dither signal to the signal of the predetermined level is set as the threshold value for the binarization process, and when the detection unit detects that the binary data for turning on the dot exists, the threshold value of the high level is set. The input image data is converted into binary data by the error diffusion method using the setting unit that sets the threshold value for the binarization process and the threshold value for the binarization process set by the setting unit. And having a digitizing unit.

〔Example〕

 First, the principle of this embodiment will be described below.

In this embodiment, the threshold T for binarization is changed according to the input data D to control the appearance of dots in the highlight portion of the image.

 There are the following two means for realizing this.

(1) Dot detection means for checking the appearance state of ON dots of already binarized data in the window of the size selected based on the image density D.

(2) A fluctuation data generating means for adding fluctuation data whose amplitude changes in accordance with the density in a highlighted portion of an image to a fixed threshold value and turning on the dot with a specific probability.

Using the output signals from these two means, the threshold value T for binarization is controlled by the following procedure.

(A) If there is a dot in the proximity area due to the output of (1), the threshold value T is set high and the output data B is controlled to 0 in the image binarization processing. As a result, the correction data D ′, which is the difference between the input data and the output data, is diffused to the unprocessed surrounding pixels as an error.

(B) When there is no dot in the proximity area due to the output of (1), the binarization process is performed by adding the fluctuation data having the amplitude corresponding to the input data D and the fixed threshold value as a new threshold value T. To do.

 The first embodiment will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Input image data D read by the image reading device 1
(100) is the correction data ΔD of the target pixel 11 in the adder 10.
(100) is added to obtain corrected data D '(102).
D'is compared with the threshold value T (103) by the comparator 12, and D '
Output B (104) that becomes 1 when ≧ T and 0 when D ′ <T
Get.

The output data B is the maximum value of the input data in the level converter 13.
The level is converted into D _max and the minimum value D _min to obtain a signal B ′ (105). For example, when the input is 8-bit data, it is converted into a value of 0 → 0, 1 → 255. This output B'is subtracted from D'in a subtractor 14, and an error component signal (106) E = D'-B 'is obtained. Based on the error signal E, the distributor 15 calculates error data distributed to the error buffer memory 16 of 12 pixels around the target pixel. As a result, the cumulative value of the error data is stored in each error buffer memory.

Further, the output signal B is sent to the line memory 17. The line memory 17 is composed of a FIFO (Fast In First Out) memory and is connected so that the output 107 of the first stage is the input of the second stage. This is 3 steps (17-1,17-
2, 17-3) By combining, it is possible to refer to the binarized data for four lines (l ₀ , l ₁ , l ₂ , l ₃ ).

On the other hand, the input image data D is input to the dot detector 18 and the fluctuation data generator 19. The dot detector 18 changes the window size composed of the output from the 1-bit line memory on the basis of the input data D, detects the presence or absence of dots in the window, and uses this result as the threshold selection circuit 20 and the fluctuation data generator 19 Output to.

The fluctuation data generator 19 is a circuit that generates fluctuation data that swings positively and negatively around 0, and generates, for example, a dither signal. The amplitude value of the fluctuation data changes according to the value of the input data D. For example, as shown in FIG. 2, a curve having a larger amplitude as D becomes smaller is taken. However, the value of D = 0 also sets the amplitude to 0. This indicates a highlight portion with lower density as D becomes smaller. By increasing the amplitude here,
Dots can be dispersed.

The output signal 108 from the dot detector 18 is also used as a control signal when updating the fluctuation data, and within the window of the 1-bit line memories 17-1 to 17-3 (the window size depends on the input data D). The change data is controlled so that it is updated only when there is no dot. As a result, the periodicity of the variation data can be destroyed and the influence of the periodicity of the variation data can be reduced. This variation data is input to the threshold selector 20. The dot detector 18, the fluctuation data generator 19, and the threshold value selector 20 are collectively referred to as a threshold value determining circuit 21.

FIG. 3 is a diagram for explaining that the window size formed by the output of the 1-bit line memory is changed based on the input data D. In the example, the window size is switched in four stages.

(However, D ₁ <D ₂ <D ₃ ) D ₁ , D ₂ , and D ₃ are experimentally determined parameters.

Here, 0, 1, 2, and 3 are values output from the encoder 35 in FIG. This window size is not limited to this example, and better threshold value control can be achieved by allowing selection in a wider range in several stages.

Here, the lower the image density is, the larger the processed area is referred to, so that the dots can be printed with uniformity according to the image density, and the image quality can be improved.

FIG. 4 is a block diagram showing details of the threshold value determining circuit 21.

The latch circuit 30 has one bit line memory 17-1, 17-2,
The outputs l ₀ , l ₁ , l ₂ , l ₃ from 17-3 are input and outputs WD ₁ , WD ₂ , WD ₃ are obtained.

 FIG. 5 shows details of the latch circuit 30.

Input from 1bit line memory l ₀ , l ₁ , l ₂ , l ₃ are latch 50a
.About.50x, and pixel data delayed by one pixel each is obtained.

Output signal line WD ₁ is latch 50a, 50b, 50c, 50d, 50e, 50f, 50
It shows the output of 12 pixels of g, 50h, 50n, 50o, 50u, 50v.

Output signal line WD ₂ is latch 50i, 50j, 50k, 50l, 50m, 50p, 50
It shows an output of 8 pixels of t and 50w.

The output signal line WD ₃ shows the output of four pixels of latches 50q, 50r, 50s, 50x.

The size A indicates a total area of 24 pixels of WD ₁ , WD ₂ and WD ₃ , and the size B indicates a total area of 12 pixels of WD ₂ and WD ₃ .
The size C indicates a 4-pixel area of WD ₃ .

Next, in FIG. 4, all logical ORs of the pixel groups of WD ₁ , WD ₂ and WD ₃ are taken by the OR circuits 31a, 31b and 31c. Next, the OR circuit 32, 33
At, the logical OR of the following equations is taken and signals WA, WB, WC are obtained.

(However, ∪ is a logical OR) By taking this logical OR, the output of WA, WB, and WC becomes 1 if the dot is on even for one pixel in the window. This output signal enters the I _{0 to} I ₂ terminals of the selector. I ₃ is fixed at 0. The output of the selector 34 selects I ₀ , I ₁ , I ₂ , I ₃ according to the outputs of ₀ , ₁ , ₂ , ₃ , 4 from the encoder 35. In the selector 34, the 2-bit output signal Sel-W from the encoder 35 according to the level of the input signal D as shown in Expression 1
The signals of WA, WB, WC, 0 are switched for 0, 1, 2, and 3 of 300, and the Sel-T300 signal is sent to the selector 36. Sel-T outputs 1 if there is at least one dot in the reference area and outputs 0 if there is no dot.

The dither ROM 37 is a circuit that generates an original signal of the threshold fluctuation signal, and outputs the data indicated by the address counter 38. A Bayer type dither is suitable for the dither matrix. Note that this dither matrix has positive and negative values. Then, this output is subjected to amplitude value control corresponding to the data D by the gain controller 39 as shown in FIG. 2, and is added to the value of the fixed threshold value 44 by the adder 45, and the selector 36
Input to the I ₀ pin of. The terminal I _{1 of the} selector 36 is
A high threshold value is set so that the output of the binary comparator 12 is always 0. High threshold hold circuit
40 is wired and these signals are switched by the Sel-T signal 300.

That is, when Sel-T is 1, that is, when there is a dot in the already binarized reference area, a high threshold value, or Sel-T
When -T is 0, that is, when there is no dot in the reference area, the variation threshold value is selected.

The output of the encoder 35 is checked by the comparator 41 so that the output is 3 or 3, and the NOR of this signal and the Sel-T signal is taken by the NOR circuit 42. The output of the NOR circuit and the pixel ClK302 are ANDed by the AND circuit 43, and the result is input to the ClK terminal of the address counter 38. As a result, the address is updated only when the density is smaller than D ₃ and there is no 1 in the reference window, and the influence of the periodic structure of the dither ROM can be reduced.

According to the embodiment described above, in the portion where the image density is low, the gain controller 39 increases the amplitude of the value of the dither matrix having a negative value, so that the fixed threshold value can be lowered, and It is possible to prevent the phenomenon that the dots that were generated in the lower part do not get hit and come out white. further,
By controlling the magnitude of the amplitude according to the image density, it is possible to suppress the deterioration of the character portion and also maintain the smoothness of the image.

Also, if a dot is hit in the reference area that has already been binarized, a high threshold is selected in the high threshold hold 40, so that the dot is forcibly prevented from being hit in the pixel of interest. Can prevent the dots from connecting.

Further, since the reference area is changed according to the density, the dot can be controlled according to the density. Further, since the threshold value is obtained by controlling the gain of the value of the dither ROM and adding it to the fixed threshold value, the hardware scale can be simplified as compared with the case where a random number is generated for the threshold value and used.

Furthermore, since the output of the dither ROM is controlled based on the image density and the presence or absence of dots in the reference area, it is possible to reduce the influence of the periodic structure of the dither ROM.

FIG. 6 shows a block diagram obtained by partially modifying the embodiment shown in FIG.

In FIG. 6, the same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

T ₀ 70 is the initial value of the threshold and ΔT 72 is the variation of the threshold. The initial value T ₀ is initially held in the latch 69, and the calculation of T ′ = T ₀ −ΔT is performed by the adder 71.

When the output of NOR 42 is 0, that is, when the input density data D is larger than D ₃ , or when the dot is turned on in the reference area, T ₀ is selected. On the other hand, when that is D output of NOR 1 is less than D _3, if dots in the reference region is not T 'is selected. And this T ₀ or T'is the selector
Input to 36 I ₀ pin. In other words, selector 67 is NOR42
I ₀ and I ₁ are selected and output according to 1,0. At the same time, this data is entered in the latch 69. When the output of NOR42 is 1 and T'is selected, the adder 71 calculates T "= T '-. DELTA.T. In this way, when the output of NOR42 is 1, that is, 0D <D.
_{As long as 3} and 1 does not exist in the window,
The threshold value T is lowered by ΔT, and the probability of turning on the dot is increased.

On the other hand, once a dot is hit, 1 is displayed in the window.
, The output of NOR42 becomes 0, and selector 6
7 selects the initial value T ₀ . This prevents the dots from being continuously hit.

Also, when the input data D> D ₃ , the output of NOR 42 becomes 0, and the threshold value is initialized.

As described above, according to the second embodiment, when the density is low and there is no dot in the binarized reference area, the threshold value is lowered so that the dot is not hit at all in the low density portion and becomes white. It can be prevented from coming off.

When the present embodiment is used in a color image processing apparatus, it can be realized by providing the circuit of the present embodiment with necessary colors.

〔The invention's effect〕

As described above, according to the present invention, when the binary data for turning on the dot does not exist in the predetermined area, the dither signal whose fluctuation range changes according to the level of the input image data is added to the signal of the predetermined level. Since the set data is set as the threshold value for the binarization process and the binarization process is performed, it is possible to prevent the occurrence of white spots in the highlight portion. Further, when there is binary data for turning on dots in a predetermined area, a high level threshold value is set as a threshold value for binarization processing and binarization processing is performed. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a block configuration diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of amplitude control of fluctuation data, FIG. 3 is an explanatory diagram of a window for referring to already binarized data, FIG. 4 is a diagram showing a first embodiment of the threshold value determining circuit, FIG. 5 is a block diagram of a latch circuit, and FIG. 6 is a diagram showing a second embodiment of the threshold value determining circuit. Image reading device, 10 is an adder, 11 is a pixel of interest, 12 is a comparator, 13 is a level converter, 14 is a subtractor, 15 is an error distributor, 16 is an error buffer memory, 17-1, 17-2 , 17-3 is
1-bit line memory, 18 dot detector, 19 variable data generator, 20 threshold selector, 21 threshold decision circuit,
Reference numeral 22 is an image output device.

Claims (1)

(57) [Claims] 1. An image processing apparatus for inputting multi-valued image data representing image information and converting it into binary data, wherein binary data for turning on dots in a binarized area consisting of a plurality of pixels. And a dither signal whose variation range changes in accordance with the level of the input image data when the detection unit detects that there is no binary data for turning on the dot. The data added to the level signal is set as a threshold value for binarization processing, and when the detection means detects the presence of binary data for turning on the dot, the high level threshold value is set for binarization processing. And a binarizing unit for converting the input image data into binary data by an error diffusion method using the binarizing threshold set by the setting unit. The image processing apparatus according to claim.