JP2693785B2 - Line switching method - Google Patents

Description

The present invention relates to a line switching system, and more particularly to a line switching system when a line is duplicated to ensure reliability in data transmission.

[Conventional technology]

In the conventional line switching system of this type, when an error is detected in the received data string coming from the selected line, the line is switched to the other line.

[Problems to be solved by the invention]

The above-described conventional switching system has a drawback that when switching received data from two different lines, an error such as data loss or duplication at the time of switching occurs due to a difference in propagation delay time on both lines.

[Means for Solving the Problem] The line switching system of the present invention preliminarily stores a synchronization pattern generation circuit for generating synchronization data having a predetermined pattern on the transmission side, generation data of the synchronization pattern generation circuit, and transmission data in advance. A synchronization pattern insertion circuit for multiplexing in a predetermined frame format, a synchronization pattern detection circuit for detecting the presence or absence of frame synchronization loss on the receiving side, and the reception data except the synchronization data from the reception data string are output. The separation circuit and the buffer circuit for temporarily storing the reception data output by the separation circuit are provided in two systems each, and further, an address generation circuit for generating a signal for instructing a read address of the buffer circuit and the synchronization pattern detection circuit. Selection for selecting one of the reception data output from the two buffer circuits in response to the detection result And a circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are block diagrams showing an embodiment of the present invention. In the figure, reference numeral 1 is a transmission device equipped with the transmission / reception circuit shown in FIG. 1B, 2 is a synchronization pattern generation circuit, 3 is a synchronization pattern insertion circuit, 4 is a synchronization pattern detection circuit, 5 is a separation circuit, and 6 is A buffer circuit, 7 is a read address creating circuit, and 8 is a selecting circuit. The transmission device 1 exchanges data signals with each other via the duplex line of the route A and the route B. Transmission is performed by sending the output signal from the same circuit to both routes, and reception is performed by providing a circuit for each route and selecting and outputting the output signal of the circuit with no error. To do. That is, in FIG.
On the transmitting side, m bits of synchronization bits generated by the synchronization pattern generation circuit 2 are added to 1 bit of transmission data by the synchronization pattern insertion circuit 3 to make (l + m) bits as one frame, and the synchronization pattern has one frame of n frames. Takes a multi-frame structure as a unit. On the receiving side, routes A and B
The sync pattern detection circuit 4 detects the synchronization of the synchronization bits of the multi-frame from the received data coming from, and the separation circuit 5 separates the 1-bit received data corresponding to the above-mentioned transmission data according to the detection result. Send to the buffer circuit 6. This received data is written in the address of the buffer circuit 6 set in advance so as to be correlated with the frame number of the multi-frame detected by the synchronization pattern detection circuit 4 and uniquely respond. The multiframe length and the capacity of the buffer circuit 6 are set to be equal to or larger than the difference between the delay amounts of the routes A and B. The read address creation circuit 7 creates a signal that indicates the read address cyclically in synchronization with the received data. In both the routes A and B, the data in the buffer circuit 6 is read according to the read address signal. The reception data output by both buffer circuits 6 is selected by the selection circuit 8 and output as reception data. While the received data from the routes A and B are both normal, for example, while the received data of the route A is being selected by the selection circuit 8 and the received data is being obtained,
When a failure occurs in the route A, if the synchronization pattern detection circuit 4 of the route A detects loss of synchronization, the selection circuit 8 selects and outputs the reception data of the route B according to the detection result. Then, switch the connection. At this time, the write address of the buffer circuit 6 is set so as to uniquely correspond to the frame number of the multi-frame, and the read addresses have the same timing on both the routes A and B. There will be no missing data or duplication errors.

〔The invention's effect〕

As described above, according to the present invention, a synchronization pattern having a data multi-frame structure is added on the transmitting side, data is once written in the buffer circuit on the receiving side and read at the same timing, so that data omission or duplication error occurs. There is an effect that the line can be switched without the need.

[Brief description of the drawings]

1 (a) and 1 (b) are block diagrams showing an embodiment of the present invention. 1 ... Transmission device, 2 ... Sync pattern generation circuit, 3 ...
Sync pattern insertion circuit, 4 ... Sync pattern detection circuit,
5 ... Separation circuit, 6 ... Buffer circuit, 7 ... Read address creating circuit, 8 ... Selection circuit.

Claims (1)

(57) [Claims] 1. A synchronization pattern generation circuit for generating synchronization data having a predetermined pattern on the transmission side, and a synchronization pattern insertion circuit for multiplexing the generation data and transmission data of the synchronization pattern generation circuit into a predetermined frame format. A synchronization pattern detection circuit for detecting the presence or absence of frame synchronization loss on the receiving side, a separation circuit for outputting the reception data by removing the synchronization data from the reception data string, and a reception data output by the separation circuit. A buffer circuit for temporary storage is provided for each of the two systems, and further, two systems of the buffer circuits are provided in response to the detection result by the address creating circuit for generating a signal indicating the read address of the buffer circuit and the synchronization pattern detection circuit. A line switching system that includes a selection circuit that selects one of the received data output by.