JP2695005B2 - Charge detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a charge detection circuit for performing charge detection with high gain.

(Prior Art) In charge detection used in a conventional CCD (Charge Coupled Device) or the like, a floating diffusion layer is formed on the same substrate and signal charges are allowed to flow into the floating diffusion layer while maintaining a predetermined phase relationship with a reset pulse. A method of detecting a potential change in the floating diffusion layer with a buffer having a high input impedance, for example, a source follower circuit is used.

When the gain G of the charge detection circuit is defined by the ratio of the output voltage to the unit signal charge, this is C, which is the capacitance of the floating diffusion layer.
G = (1 / C) Av where the voltage gain of the source follower circuit is Av
It is expressed. In order to increase the gain G, it is necessary to reduce the capacitance C or increase Av.

By the way, the capacitance C is limited due to processing precision such as device mask alignment and floating capacitance of the floating diffusion layer.
Also, the voltage gain Av generally does not exceed 1 in value. Therefore, in order to increase the gain of charge detection, it has been considered to add on-chip amplification, that is, to provide an output terminal of the source follower circuit with an amplification circuit.

The conventional charge detection circuit will be described below with reference to FIG. This circuit includes a source follower circuit (215) for detecting a signal voltage, a voltage generating circuit (205a) for generating a voltage applied to a load MOS transistor (210) of the source follower circuit (215), and a source follower circuit (215). It is composed of three inverter amplifier circuits (205b) that amplify the output voltage. The configuration of each part will be sequentially described below. First, regarding the source follower circuit (215), the floating diffusion layer (201
a) is a MOS transistor (202a) that is a reset switch
Connected to the source side of. It is a reset switch
The drain of the MOS transistor (202a) is connected to the reset drain voltage (203), and the gate is connected to the reset pulse applying terminal (204a). Next, the voltage generation circuit (205a) will be described. The floating diffusion layer (201b) is also connected to the source side of the MOS transistor (202b) which is a reset switch. MO which is a reset switch
The drain of the S transistor (202b) is connected to the reset drain voltage (203), and the gate is connected to the reset pulse applying terminal (204b).

This circuit is composed of a load MOS transistor (207) and a driver MOS transistor (208). load
The gate of the MOS transistor (207) is a floating diffusion layer (210b)
And the drain is connected to the power supply voltage (206). The gate of the driver MOS transistor (208) is connected to the drain and also to the source of the load MOS transistor (207). The input of the inverter circuit (205a) is input to the gate of the driver MOS transistor (208), and the output is output from the drain of the driver MOS transistor (208).

The source follower circuit (215) is composed of a driver MOS transistor (209) and a load MOS transistor (210). Source follower (215) input is driver M
It is input from the gate of the OS transistor (209), and the output is output from the source of the driver MOS transistor (209). The gate of the driver MOS transistor (209) is connected to the floating diffusion layer (201a), and the drain is the power supply voltage (20
6) Connected to. The output of the inverter circuit (205a) is connected to the gate of the load MOS transistor (210), and the drain is connected to the source of the driver MOS transistor (209).

The inverter circuit (205b) is a load MOS transistor (21
1) and a driver MOS transistor (212). The input of the inverter circuit (205b) is input from the drain of the driver MOS transistor (112), the output is output from the source of the load MOS transistor (211), and is connected to the output terminal (216). The gate of the load MOS transistor (211) is connected to the drain, and the drain is connected to the power supply voltage (206). Driver M
The gate of the OS transistor (212) is the source follower circuit (2
15) is connected to the source of the driver MOS transistor (209) and the drain is the load MOS transistor (211)
Connected to the source.

Now, in order to equalize the potentials at V _B , V _C , and V _D of the circuit, the conditions of the MOS transistor are set as follows. MOS transistor gate length is L, gate width is W
As W / L of the MOS transistor. For example, if the ratio of the MOS transistor (207) of the inverter circuit (205a) is W ₁ / L ₁ ,
If the ratio of the MOS transistor (208) is W ₂ / L ₂ , then that ratio (W ₁ /
Calculate L ₁ ) / (W ₂ / L ₂ ) (formation ratio). Similarly, the ratio of the source follower circuit (215) and the inverter circuit (205b) is obtained. Now all of these values are made equal and the potentials at V _B , V _C and V _D are made equal.

Next, the operation will be described. First, the power supply voltage (206) and the reset drain voltage (203) are set to the same voltage. The signal charges obtained from the charge transfer device (not shown) maintain the predetermined phase relationship with the reset pulse and are in the floating diffusion layer (201a).
The potential change in the floating diffusion layer (201a) changes the current flowing in the driver MOS transistor (209) of the source follower circuit (215) and is detected as a voltage signal. The other floating diffusion layer (201b) is provided to reduce the reset noise generated at the reset pulse application terminals (204a) and (204b), and the charge does not flow in, and the reset drain voltage ( 203)
Has taken the value of.

Now, apply the reset pulse to the reset pulse applying terminal (204a) (at this time, the reset pulse applying terminal (204a)
The reset pulse is also applied to b) at the same time), and MOS transistors (202a) and (202b) that are reset switches.
When turned on, the floating diffusion layers (201a), (201a)
The potential of b) becomes equal to the power supply voltage (206). In the ON state, the power supply voltage (206) is applied to the gate of the driver MOS transistor (209) and the potential V _B is applied to the gate of the load MOS transistor (210), so the potential V _{C at} the output of the source follower circuit (215) and the inverter circuit The potential V _{B at} the output of (205a) becomes equal. The potential V _{D at} the output of the inverter circuit (205b) is also equal to the potential V _C because the power supply voltage is applied to the gate of the load MOS transistor (211) and V _B is applied to the gate of the driver MOS transistor (212). At this time, the inverter circuit (205a), (205
b) and the source follower circuit (215) have the same shape ratio, the potentials of V _B , V _C, and V _D become equal, and the output of the source follower circuit (215) becomes an inverter circuit (205b).
Can be within the input dynamic range of. Therefore, if the input / output characteristics of the inverter circuit (205b) are the characteristics shown in FIG. 3, since the input and output are equal, the input and output take a certain value in a linear region in which the input and the output increase in proportion.

Next, the MOS transistor (202
Turn off (a) and (202b). At this time the potential
V _B and V _C fluctuate by the amount of reset noise, but if this potential fluctuation is small, the operating point of the inverter circuit (205b) can be set.

In the off-state, the potential in the floating diffusion layer (201a) into which the signal charge has flown decreases with an increase in the amount of charge and is applied to the gate of the driver MOS transistor (209) of the source follower circuit (215). When the gate voltage of the driver MOS transistor (209) changes, the current flowing through the source follower circuit (215) changes and the potential of V _C changes. The potential of V _C is applied to the gate of the driver MOS transistor (212) of the inverter circuit (205b), changes the current flowing in the inverter circuit (205b), and the potential of V _D changes and is output to the output terminal (216). It

According to the above configuration, the inverter circuit (205b) can be provided as an amplification stage to perform high-gain charge detection. However, the power supply voltage (206) is applied to the gate of the load MOS transistor (211) of the inverter circuit (205b). Therefore, when the power supply voltage (206) fluctuates, the potential of V _D fluctuates. Noise or the like may be mixed in the power supply potential (206), which causes power supply fluctuation. For this reason,
This fluctuation of the power supply voltage (206) may be added to the potential change due to the signal charges flowing into the floating diffusion layer (201a), which causes a problem that a stable potential cannot be obtained.

In addition, in order to solve this problem, an inverter circuit (20
Although it is possible to separate the power supply connected to the gate of the load MOS transistor (211) and the power supply connected to the drain of 5b), it is necessary to provide a separate power supply, and the manufacture thereof. It costs money. The threshold values V _TH of the MOS transistors (207), (209), (211) are the same, and E transistors having an extremely small V _TH are used. MOS transistors (208), (210),
The threshold values V _TH of (212) are the same, and V _TH is medium (2
~ 3V) E-transistor. MOS transistor (201
a) and (201b) are D transistors.

(Problems to be Solved by the Invention) In the conventional charge detection circuit, although the operating point of the amplification stage is automatically set, the power source is supplied to the gate of the load MOS transistor of the first inverting amplifier provided as the amplification stage. Since the voltage is applied, if there is a fluctuation in this power supply voltage,
This fluctuation appears in the output, and there is a problem that stable charge detection cannot be performed.

In the present invention, the second stage is provided after the first inverting amplifier.
The purpose of this invention is to automatically set the operating point of the amplifying stage by adding the inverting amplifier, and to reduce the fluctuation of the output due to the power supply voltage to perform stable charge detection.

[Configuration of the Invention] (Means for Solving the Problems) In the present invention, a floating diffusion layer formed on a semiconductor substrate, a reset switch for resetting the potential of the floating diffusion layer, and a potential of the floating diffusion layer are set. A source follower circuit that receives input from the gate side of the first driver MOS transistor, and an output of this source follower circuit is used as a second driver MOS transistor.
A first inverting amplifier that receives an input from the gate side of the transistor, and an output of the first inverting amplifier that is a third driver MO.
A second inverting amplifier that receives an input from the gate side of the S-transistor; and a third inverting amplifier that connects an output to the gate of the load MOS transistor of the source follower circuit. There is provided a charge detection circuit characterized in that the output is connected to the gate of the fourth driver MOS transistor of the third inverting amplifier.

(Operation) In the charge detection circuit of the present invention, the operating point of the amplification stage is automatically set, and the second inverting amplifier is provided after the first inverting amplifier, whereby the first inverting amplifier is provided. The fluctuation of the output of the first inverting amplifier that occurs due to the application of the charge voltage to the gate of the load MOS transistor of the type amplifier is inverted so that a stable output can be obtained with respect to the fluctuation of the power supply voltage.

(Example) Hereinafter, an example of the present invention will be described with reference to FIG. The floating diffusion layer (101a) is connected to the source side of a MOS transistor (102a) which is a reset switch. The drain of the MOS transistor (102a) which is the reset switch is connected to the reset drain voltage (103), and the gate is connected to the reset pulse applying terminal (104a). or,
One floating diffusion layer (101b) is similarly connected to the source side of a MOS transistor (102b) which is a reset switch. MOS transistor (102
The drain of b) is connected to the reset drain voltage (103), and the gate is connected to the reset pulse applying terminal (104b).

The inverter circuit (105a) is a load MOS transistor (10
7) and a driver MOS transistor (108). The gate of the load MOS transistor (107) is connected to the floating diffusion layer (101b) and the drain is connected to the power supply voltage (10
6) Connected to. Driver MOS transistor (10
The gate of 8) is connected to the drain and also to the source of the load MOS transistor (107). The input of the inverter circuit (105a) is input from the gate of the driver MOS transistor (108), and the output is output from the drain of the driver MOS transistor (108).

The source follower circuit (115) is composed of a driver MOS transistor (109) and a load MOS transistor (110). The input of the source follower circuit (115) is input from the gate of the driver MOS transistor (109), and the output is output from the source of the driver MOS transistor (109). The gate of the driver MOS transistor (109) is connected to the floating diffusion layer (101a), and the drain is connected to the power supply voltage (106). Load MOS transistor (11
The gate of (0) is connected to the output of the inverter circuit (105a), and the drain is connected to the source of the driver MOS transistor (109).

The inverter circuit (105b) is a load MOS transistor (11
1) and a driver MOS transistor (112). The input of the inverter circuit (105b) is input from the drain of the driver MOS transistor (112), and the output is output from the source of the load MOS transistor (111). The gate of the load MOS transistor (111) is connected to the drain, and the drain is connected to the power supply voltage (106). The gate of the driver MOS transistor (112) is the driver MOS transistor (109) of the source follower circuit (115). Of the load MOS transistor (111) and its drain is connected to the source of the load MOS transistor (111).

The additional inverter circuit (105c) is composed of an additional MOS transistor (113) and a driver MOS transistor (114). The input of the additional inverter circuit (105c) is input from the gate of the driver MOS transistor (114), the output is output from the source of the load MOS transistor (113), and is connected to the output terminal (116). The gate of the load MOS transistor (113) is connected to the power supply voltage (106), and the drain is similarly connected to the power supply voltage (106). The gate of the driver MOS transistor (114) is the load MOS transistor (111) of the inverter circuit (105b).
Of the load MOS transistor (1
13) connected to the source.

Now, the conditions of the MOS transistor are set as follows in order to equalize the potentials at V _B , V _C , and V _D of the respective circuits. The gate length of the MOS transistor is L and the gate width is W, and W / L of the MOS transistor is obtained. For example, set the ratio of the MOS transistor (107) of the inverter circuit (105a) to W ₃ / L
_3. Assuming that the ratio of the MOS transistor (108) is W ₄ / L ₄ , the ratio (W ₃ / L ₃ ) / (W ₄ / L ₄ ) is obtained. Similarly, the ratio of the source follower circuit (115) and the inverter circuit (105b) is obtained. Now, all of these values are made equal and the potentials at V _B , V _C , and V _D are made equal. Next, the operation will be described. First, the power supply voltage (106) and the reset drain voltage (103) are set to the same voltage. A signal charge obtained from a charge transfer device (not shown) flows into the floating diffusion layer (101a) while maintaining a predetermined phase relationship with the reset pulse, and a potential change in the floating diffusion layer (101a) causes a source follower circuit (115). The current flowing through the driver MOS transistor (109) is changed and detected as a voltage signal. The other floating diffusion layer (101b) is provided in order to reduce the reset noise generated at the reset pulse application terminals (104a) and (104b). 103)
Has taken the value of.

Now, apply the reset pulse to the reset pulse applying terminal (104a) (at this time, the reset pulse applying terminal (104a)
The reset pulse is also applied to b) at the same time), and the MOS transistors (102a) and (102a) are the reset switches.
Is turned on, the floating diffusion layers (101a), (101a)
The potential of b) becomes equal to the power supply voltage (106). ON
In this state, the gate of the driver MOS transistor (109) is connected to the power supply voltage (106) and the load MOS transistor (11).
Since the potential V _B is applied to the gate of (0), the source follower circuit (1
The potential V _{C at} the output of 15) and the potential V _{B at} the output of the inverter circuit (105a) become equal. At this time, since the inverter circuits (105a), (105b) and the source follower circuit (115) have the same shape ratio, V _B , V _C and
The potential of V _D becomes equal and the output of the source follower circuit (115) can be put within the input dynamic range of the inverter circuit (105b). Therefore, the inverter circuit (10
If the input / output characteristic of 5b) is the characteristic shown in FIG. 3, since the input and output are the same, it takes a certain value in the linear region where the input and the output increase in proportion.

Next, the MOS transistor (102
Turn off a) and (102b). At this time the potential
V _B and V _C fluctuate by the amount of reset noise, but if this potential fluctuation is small, the operating points of the inverter circuits (105b) and (105c) can be set.

In the off state, the potential in the floating diffusion layer (101a) into which the signal charge has flown decreases with an increase in the amount of charge and is applied to the gate of the driver MOS transistor (109) of the source follower circuit (115). When the gate voltage of the driver MOS transistor (109) changes, the current flowing through the source follower circuit (115) changes and the potential of V _C changes. The potential of V _C is applied to the gate of the driver MOS transistor (112) of the inverter circuit (105b), changes the current flowing in the inverter circuit (105b), and changes the potential of V _D. The potential of V _E is V _D by the inverter circuit (105c).
Becomes the inverted potential, which is the output terminal (11
It is output to 6).

According to the above configuration, the inverter circuit (105b) can be provided as an amplification stage to perform high-gain charge detection. However, the potential of V _D , which is the output of the inverter circuit (105b), is the load MOS transistor (111). Supply voltage to the gate of (106)
, The potential of V _D fluctuates when the power supply voltage (106) fluctuates. However, an additional inverter circuit (105c) is added after the inverter circuit (105b).
By providing, the fluctuation of the potential of V _D is reversed. Since the same electrode as that of the inverter circuit (105b) is used for the voltage applied to the gate and drain of the load MOS transistor (113) of the additional inverter circuit (105c), the potential of V _E also changes.

Now, the voltage gain of the inverter circuit (105b) is G ₁ , the voltage gain of the additional inverter circuit (105c) is G ₂ , the ratio (modulation degree) to the applied voltage of the potential well under the gate of the MOS transistor is m, and the power supply voltage is V _Assuming that the thresholds of _OD and E-type MOS transistors are V _TH and the threshold of S-type MOS transistors is 0, the relationship in the characteristics of V _C , V _D and V _E as shown in FIG. 3 is linear. Within the operating range, it can be expressed as V _D = mV _OD −G ₁ (V _C −V _TH ) …… (1) V _E = mV _OD −G ₂ (V _D −V _TH ) …… (2) it can. Eliminating V _D from Eqs. (1) and (2), V _E = m (1-G ₂ ) V _OD + G ₁ G ₂ (V _C −V _TH ) + G ₂ V _TH ……
(3) Therefore, if the power supply voltage fluctuation is ΔV,
The variation is m (1-G ₂ ) ΔV, but the variation can be sufficiently reduced by setting the voltage gain G ₂ of the additional inverter circuit (105c) to a value close to 1.

Therefore, the fluctuation of the output due to the fluctuation of the power supply voltage can be reduced, and the high-gain charge detection can be stably performed. Moreover, it is not necessary to provide a separate power supply. MO
The threshold values V _TH of the S transistors (107), (109), (111), and (113) are the same, and the E transistors having an extremely small V _TH . MOS transistors (108), (110),
The thresholds V _TH of (112) and (114) are the same, and the E-transistor has an intermediate V _TH (2 to 3 V). The MOS transistors (102a) and (102b) are D transistors.

[Effects of the Invention] According to the present invention, the operating point of the amplification stage can be automatically set, and further, by providing an inverting amplifier in the subsequent stage of the amplification stage, the fluctuation of the output due to the fluctuation of the power supply voltage is reduced. Stable charge detection can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a charge detection circuit in an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional charge detection circuit, and FIG. 3 is a characteristic diagram of an inverter circuit for explaining the charge detection circuit. Is. Floating diffusion layers ... 101a, 101b, 201a, 201b, reset switch MOS transistors ... 102a, 102
b, 202a, 202b, reset drain voltage …… 103,203, reset pulse application terminal …… 104a, 104b, 204a, 204b, inverter circuit …… 105a, 105b, 205a, 205b, power supply voltage …… 106,206, MOS transistor …… 107,108,109,110,111,112,113 , 11
4,207,208,209,210,211,212, source follower circuit …… 115,215, output terminal …… 116,216.

Claims (1)

(57) [Claims] 1. A floating diffusion layer formed on a semiconductor substrate, a reset switch for resetting a potential of the floating diffusion layer, and a potential of the floating diffusion layer being input from a gate side of a first driver MOS transistor. A source follower circuit, a first inverting amplifier that receives the output of the source follower circuit from the gate side of a second driver MOS transistor, and an output of the first inverting amplifier that is a third driver MOS transistor.
A second inverting amplifier having an input from the gate side of the transistor; and a third inverting amplifier having an output connected to the gate of the load MOS transistor of the source follower circuit, the output of the third inverting amplifier The gate of the fourth driver MOS transistor of the third inverting amplifier is connected to the charge detection circuit.