JP2696519B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology which is effective when applied to a digital circuit, a driver for driving a capacitive load in a semiconductor integrated circuit device, and the like. (Emitter-coupled logic) Level-level logic signals are converted to CMOS (complementary logic).
The present invention relates to a technology effective for driving a logic circuit (MOS transistor) or a Bi-CMOS (bipolar CMOS composite) logic circuit.

[Prior Art] For example, "Nikkei Electronics No. 410, December 12, 1986," published by Nikkei McGraw-Hill, converts an ECL-level logic signal into a logic signal having a level compatible with a CMOS logic circuit or a bipolar CMOS logic circuit. A bipolar CMOS digital circuit for level conversion is described.

The inventor has developed a digital circuit as shown in FIG. 4 as this kind of digital circuit.

The digital circuit 10 shown in FIG. 4 is a Bi-CMOS type digital circuit that performs level conversion from ECL to CMOS or Bi-CMOS, and its output section 11 is configured using npn bipolar transistors Q1 and Q2. The driving unit 12 includes p-channel MOS transistors Mp1, Mp2, Mp3 and an n-channel MOS transistor.
It is configured using transistors Mn1, Mn2, Mn3, Mn4, and Mn5.

The bipolar transistors Q1 and Q2 constitute a push-pull output unit 11 by being connected in series between the positive power supply potential V _CC and the negative potential V _EE . Its output out is
It is derived from a connection point (node) of both transistors Q1 and Q2 and is connected to a capacitive load CL such as a CMOS logic circuit or a Bi-CMOS logic circuit.

In addition, MOS transistors (Mp1, Mn1, Mp2, Mn2) and (Mp3,
Mn3, Mn4, and Mn5) form level conversion circuits 13 and 14 using current mirrors, respectively. These level conversion circuits 13, 14
Transmits the pair of differential logic signals + X, -X output from the ECL 30 via the emitter follower / buffer section 20 to the output section 11 while level-converting them, thereby complementarily driving the bipolar transistors Q1, Q2. I do.

The digital circuit 10 described above is used for a semiconductor integrated circuit device IC.
By providing the inside, for example, while the inside is formed of CMOS or Bi-CMOS excellent in low power consumption,
Externally, a semiconductor integrated circuit device compatible with ECL can be configured.

[Problem to be Solved by the Invention] However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, for example, in the digital circuit 10 shown in FIG. 4, although the power consumption is reduced by the Bi-CMOS type circuit configuration, the logic level of the output out is “L” (low level). At this time, steady currents I1 and I2 flow through the input-side MOS transistors Mp1-Mn1 and Mp3-Mn3 of the level conversion circuits 13 and 14, respectively.

For this reason, if a large number of the digital circuits 10 are provided as, for example, a word line driver or an address buffer in a storage circuit, the logic level of the output out becomes “L”.
(Low level) digital circuit
Since I1 and I2 respectively flow, large power is consumed as a whole. In particular, when a large number of digital circuits 10 are used as word line drivers,
Only one out is set to "H" (high level), which is also limited only when selected. As a result, substantially all the outputs of the digital circuits are in the "L" (low level) state, and the currents I1 and I2 are wasted.

As described above, the digital circuit 10 described above has a problem that the current consumption increases when the output out is at a specific logic level.

An object of the present invention is to provide a technique capable of reducing current consumption of a digital circuit without impairing high-speed operation.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, it is detected whether the logic output level of the digital circuit connected to the capacitive load is a specific logic level that increases current consumption, and based on this detection, the digital circuit is controlled to the idling state with low current consumption. In addition, a holding means for holding the output of the digital circuit controlled to the idling state at the specific logic level is separately provided.

According to the above-described means, for example, when the specific logic level for increasing the current consumption of the digital circuit is “L” (low level), the output of the digital circuit changes from “H” (high level) to “L”. Immediately after being switched to "(low level)", it is controlled to an idling state in which no DC current is consumed, and its output is held at "L" (low level) by another holding means. The steady current consumption at the time of L "(low level) can be reduced.

This achieves the object of reducing the current consumption of the digital circuit without impairing the high-speed operation.

EXAMPLES Hereinafter, preferred examples of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a digital circuit to which the technology according to the present invention is applied.

The digital circuit 10 shown in FIG. 1 is configured as a circuit for performing level conversion from ECL to CMOS or Bi-CMOS in a semiconductor integrated circuit device IC. First, an output unit 11 of the digital circuit 10 is an npn bipolar transistor Q1. , Q2, and its driving unit 12 is a p-channel MOS transistor Mp
1, Mp2, Mp3 and n-channel MOS transistors Mn1, Mn2, Mn3,
It is configured using Mn4 and Mn5.

The bipolar transistors Q1 and Q2 constitute a push-pull output section 11 by being connected in series between the positive power supply potential V _CC and the negative power supply potential V _EE . Its output out
Is derived from a connection point (node) between the transistors Q1 and Q2, and is connected to a capacitive load CL such as a CMOS logic circuit or a Bi-CMOS logic circuit.

In addition, MOS transistors (Mp1, Mn1, Mp2, Mn2) and (Mp3,
Mn3, Mn4, and Mn5) form level conversion circuits 13 and 14 using current mirrors, respectively. These level conversion circuits 13, 14
Transmits the pair of differential logic signals + X, -X output from the ECL 30 via the emitter follower / buffer section 20 to the output section 11 while level-converting them, thereby complementarily driving the bipolar transistors Q1, Q2. I do. The emitter follower / buffer unit 20 is provided with two bipolar transistors Q3 and Q4, each of which forms an emitter follower.

Further, in addition to the above-described configuration, the digital circuit 10
Level detection means 40 for detecting whether or not the output out has reached a specific logic level for increasing the DC current consumption, ie, "L" (low level) here, and this level detection means 40 is "L"
(Low level), the control circuit 50 controls the digital circuit 10 to an idling state with low DC consumption.
And the digital circuit 10 controlled to an idling state
And a holding means 60 for holding the output out at “L” (low level).

Here, the level detecting means 40 is connected to the positive power supply potential V _CC.
That operates between the negative power supply potential V _TT (V _TT > V _EE )
It is composed of an inverter. Mp7 and Mn7 are the C
1 shows p-channel and n-channel MOS transistors forming a MOS inverter. This level detecting means 40
Means that the output out of the digital circuit 10 is “L” (low level)
Then, "H" (high level) is output as the detection output _VCO .

The control circuit 50 includes a bipolar transistor Q5. The bipolar transistor Q5 forms a kind of wired OR by being emitter-coupled to the bipolar transistor Q3 of the emitter follower / buffer unit 20. Then, the detection output _VCO becomes “H”
At the time of (high level), the MOS transistors Mp1 and Mp3 of the level conversion circuits 13 and 14 are forcibly turned off, respectively.

When the MOS transistors Mp1 and Mp3 are turned off, the output ou
DC current flowing through MOS transistors Mp1-Mn1 and Mp3-Mn3 when the logic level of t is "L" (low level)
I1 and I2 are cut off. As a result, the digital circuit 10 enters an idling state where no DC current is consumed. Accordingly, the bipolar transistors Q1 and Q2 of the output unit 11 are both turned off and the output out is in a floating state. At this time, the logic level of the output out is
By 0, it is kept at “L” (low level).

The holding circuit 60 is formed by the resistor R1, and holds the logic level of the floating output out at "L" (low level) by weakly pulling the output out to the negative power supply potential _VEE . In this case, the "L" (low level) holding force of the holding circuit 60 does not prevent the output out from being driven to "H" (high level) by increasing the resistance value of the resistor R1. Is set to weak.

FIG. 2 is a waveform chart showing an operation example of the digital circuit 10 shown in FIG.

In FIG. 1 and FIG. 2, first, the logic input signal IN given from the external ECL 70 via the terminal Pin is set to “L”.
(Low level), the input logic signals + X and -X of the digital circuit 10 are such that + X is "H" (high level) and -X is "L".
(Low level). At this time, the digital circuit 10
Since X is “H” (high level), Mp1 and Mp3
Are turned off. Accordingly, Mn2 and Mn4
Is also turned off.

On the other hand, since −X is “L” (low level), Mp
2 turns on. This allows Q1 to be on and Q2
Is turned off, and "H" (high level) appears at the output out.

Next, the logic input signal IN switches from “L” (low level) to “H” (high level), and + X changes to “L” (low level) and −X changes to “H” (high level). Then, Mp1 and M
Each of p3 is driven to the ON state. The currents I1 and I2 flowing due to the on-states of Mp1 and Mp3 are Mn1 and Mn3.
The current is transmitted to n2 and Mn4 by the current mirror, respectively. Thereby, Mn2 and Mn4 are driven to the ON state.

On the other hand, when −X becomes “H” (high level), Mp
2 turns off.

As a result, Q1 is turned off and Q2 is turned on, and the logic level of the output out is switched to “L” (low level).

Here, when the output out becomes “L” (low level), M
The currents I1 and I2 flowing through p1 and Mp3 cause a state where the current consumption of the digital circuit 10 increases. But the output
Once out goes "L" (low level), the output of the level detection circuit 40 goes "H" (high level), thereby turning on the bipolar transistor Q5 forming the control circuit 50. When Q5 is turned on, + X is raised from "L" (low level) to "H" (high level) by wired OR of Q5 and Q4, and both Mp1 and Mp3 are turned off. As a result, the current I1, which flows through Mp1 and Mp3,
I2 is cut off immediately after the output out switches to "L" (low level). Q1 and Q2 are both turned off. As a result, the output out is immediately set to “L” (low level) and immediately becomes in a floating state. The level of the output out in the floating state depends on the holding circuit 60.
Is pulled to the negative power supply potential V _EE, that is, “L” (low level) side, and is held at “L” (low level).

As described above, when the output out is switched from “H” (high level) to “L” (low level), the current consumption temporarily increases at the beginning of the switching, but
This state ends immediately and shifts to a state where the DC current consumption is small. Further, during a transition in which the logic level of the output out is switched, a large charge / discharge current can flow through the capacitive load CL by the bipolar transistors Q1 and Q2 of the output unit 11, so that the high-speed operation is not impaired at all.

As described above, the digital circuit 10 outputs its output out.
Is switched to “L” (low level), which increases the DC current consumption, and immediately after the output out is switched from “H” (high level) to “L” (low level), The output is controlled to a low idling state, and its output out is held at "L" (low level) by another holding means 60. Current consumption can be reduced.
This makes it possible to reduce the DC current consumption without impairing the high-speed operation. Therefore, if the digital circuit 10 constitutes, for example, a word line driver, it becomes possible to constitute a high-speed memory circuit with low power consumption by suppressing the DC current consumption of the majority of drivers in the non-selected state. .

 FIG. 3 shows another embodiment of the present invention.

The embodiment shown in FIG. 1 uses two digital circuits 10 each to generate complementary logical outputs + out and -out, and is used for an address buffer or the like in a storage circuit. In the embodiment shown in the figure, a latch circuit composed of two sets of CMOS inverters 61 and 62 is connected as a holding circuit 60 between both outputs + out and -out. The CMOS inverters 61 and 62 constituting this latch circuit have an output + o
It is formed in such a size that either ut or -out does not prevent it from becoming "H" (high level).

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, the output is “H”
In a digital circuit in which current consumption increases at the time of (high level), the digital circuit may be configured to be in an idling state when "H" (high level) is output. Further, the MOS transistor may be an MIS (metal-insulator-semiconductor) transistor other than the MOS.

In the above description, the case where the invention made by the present inventor is mainly applied to a level conversion circuit from ECL to CMOS or Bi-CMOS, which is the field of use, has been described, but the present invention is not limited thereto. For example, the present invention can be applied to a normal logic gate or a driver. At least, it can be applied to a digital circuit for driving a capacitive load.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, an effect is obtained that current consumption can be reduced without impairing high-speed operation.

[Brief description of the drawings]

1 is a diagram showing one embodiment of a digital circuit to which the present invention is applied, FIG. 2 is a waveform chart showing an operation example of the digital circuit shown in FIG. 1, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a circuit diagram showing an example of a digital circuit studied prior to the present invention. 10 ... Digital circuit, 11 ... Output unit, 12 ... Drive unit, 1
3, 14: Level conversion circuit, 20: Emitter follower / buffer section, 30: ECL (emitter coupling logic), 40: Level detection circuit, 50: Control circuit, 60: "L" (low level) ) Holding circuit, out …… Output, CL …… Capacitive load, IC…
... Semiconductor integrated circuit device.

Claims (2)

(57) [Claims] A digital circuit having a capacitive load connected to an output terminal, level detecting means for detecting a logical output level of the digital circuit, and the level detecting means detecting a specific logical level corresponding to an input signal. A control circuit for inverting the input signal to control the digital circuit to an idling state with low current consumption; and a holding unit for holding an output of the digital circuit controlled to the idling state at the specific logic level. And a semiconductor integrated circuit. 2. The digital circuit is connected in series with a pair of level conversion circuits for converting a pair of differential logic signals output from the emitter-coupled logic circuit to levels compatible with CMOS logic or bipolar CMOS logic, respectively. An output unit having the two bipolar transistors provided and the two bipolar transistors being complementarily driven by the pair of level conversion circuits. The control circuit is adapted so that the level detection means corresponds to an input signal. 2. The semiconductor integrated circuit according to claim 1, wherein when a specific logic level is detected, an input signal of the level conversion circuit is inverted to control an idling state with low current consumption.