JP2697254B2 - Real-time processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a real-time processing device having a high-speed interrupt request receiver.

2. Description of the Related Art Conventionally, when there is an instruction being executed at the time of occurrence of an interrupt, the interrupt is accepted after the instruction is completed.

Problems to be Solved by the Invention However, in the case of an instruction having a relatively short instruction cycle, the interrupt response time was short because the interrupt acceptance time was short, but in the case of an instruction having a long instruction cycle, the interrupt responsiveness was extremely poor. Had become. In system design, even if the frequency of an instruction having a long instruction cycle is low, the design is generally performed in a worst case. For this reason, even in a CISC machine, an instruction with a long instruction cycle was replaced with an instruction with a relatively short cycle number from the RISC perspective during software development. Although this certainly shortens the time until the instruction is accepted, the throughput of the operation content executed by the instruction having a long cycle number is deteriorated, and the system design is difficult.

The present invention solves the above-mentioned conventional problem. When it is necessary to wait for the end of an instruction being executed at the time of occurrence of an interrupt, the interrupt is accepted after the instruction is completed, and when it is not necessary to wait for the end of the instruction being executed. It is an object of the present invention to provide a real-time processing device that realizes high-speed response by stopping an instruction and immediately accepting an interrupt.

Means for Solving the Problems In order to achieve this object, a real-time processing device according to the present invention is a device in which whether or not to accept an interrupt after completion of a currently executing instruction can be selected by a flag, and can be selected by an additional bit of an instruction code. A device that can be selected according to the instruction execution cycle, a device that can be selected by an interrupt occurrence factor, a device that can be specified by a memory area, and a device that can specify execution of a specific register file.

Operation With this configuration, when it is necessary to perform high-speed interrupt processing when an interrupt occurs, high-speed response can be realized.

Examples Hereinafter, examples of the present invention will be described.

FIG. 1 is a block diagram of one embodiment of the present invention. Upon receiving the interrupt signal from the interrupt unit 3, the interrupt receiving operation determining unit 2
Is determined by instruction state information such as whether the operation of the currently executing instruction from the μROM 4 is in the final state or not, and a flag (not shown) indicating whether or not to accept an interrupt in the interrupt accepting operation judging unit 2. It is determined whether to stop the currently executing instruction and immediately accept the interrupt or wait until the end. When the interrupt is received, an interrupt reception signal is generated in the instruction execution unit 1 and the interrupt unit 3, and the CPU starts an interrupt operation. In this embodiment, the flag for determining whether to accept an interrupt is set and reset by an instruction. When high-speed interrupt processing is required, real-time processing can be realized by accepting an interrupt immediately with this function.

FIG. 2 is a diagram showing an instruction format for setting and resetting a flag as to whether or not to accept an interrupt by an additional bit of an instruction code. The instruction format is instruction code 5, instruction code additional bit 6, operand
7, 8 in this embodiment, and 3
Operand format and special format can be used. If the instruction can be stopped due to the occurrence of an interrupt, the additional bit 6 is set to 1 if not, otherwise it is set to 0 to control the processing when the interrupt occurs. When high-speed interrupt processing is required, real-time processing can be realized by accepting an interrupt immediately with this function.

FIG. 3 shows that when an interrupt occurs, (a) the read operation to the memory is being executed, and if there is no write operation at the time of the instruction execution, the interrupt is immediately received. (B) The write operation to the memory is being executed or once during the instruction execution. However, if there is a write operation, an interrupt is accepted after execution of the instruction. (C) In the case where there is no memory access, three kinds of processing of interrupt acceptance are performed immediately if the instruction cycle is half or within a certain amount. FIG. 4 is a diagram illustrating an example. The current cycle mode information and information as to whether or not a write cycle has existed in the past are input from the sequence control unit 12 for controlling the read cycle and the write cycle of the μROM 4 to the interrupt receiving operation determining unit 2. On the other hand, the comparator 11 compares the value of the counter 10 indicating the number of instruction execution cycles constituting the state counter in the μROM 4 with the total number of instruction cycles 9. Sequence controller 12 and comparator 11
According to the result of the judgment and comparison, it is possible to cope with the interrupt receiving operation in the above three cases. When an interrupt occurs, the conditions for stopping the instruction and immediately accepting the interrupt are (total number of instruction cycles)-(number of execution cycles) <(total number of instruction cycles) / 2, and the write mode has not been in the past and Not in write mode at present. Further, by comparing the execution cycle number 9 with a certain instruction execution cycle (not shown) by the comparator 11, an interrupt can be received with a certain number of cycles independent of the number of cycles inherent to the instruction. These processes can speed up the interrupt receiving operation and realize real-time processing.

FIG. 4 is a diagram showing an embodiment in which an instruction being executed is stopped when an interrupt occurs and an interrupt is immediately accepted or an interrupt is accepted after the instruction is completed, depending on an interrupt factor.
The register 13 specifies whether or not to stop the instruction when an interrupt factor occurs, and corresponds to each interrupt factor. The AND gate circuit group 14 receives as input the value of the register 13 and an interrupt generation signal for each interrupt factor, and outputs it to the interrupt receiving operation determining unit 2. When the setting of the register 13 matches the interrupt generation factor, that is, when the instruction is stopped and the interrupt is accepted, information on whether the write mode from the sequence control unit 12 was in the past or what the current mode is is integrated. Judgment, the light mode is past,
If not present, stop the instruction immediately and accept the interrupt. Those which need to be processed preferentially depending on the cause of the interruption can be processed in real time by the configuration of the present invention.

FIG. 5 shows an embodiment in which, when an interrupt occurs while accessing a specific memory area, the instruction being executed is stopped, the interrupt is immediately accepted, and in the other areas, the interrupt is accepted after the instruction is completed. FIG. If an interrupt occurs when there is an access to the area 17 in the memory space 16 by the register 15, the interrupt is accepted after the instruction is completed.If an interrupt occurs while accessing other than the area 17, the instruction is immediately stopped. To accept the interrupt. By arranging a polling program and data requiring high-speed processing (complex operation results, etc.) in the area 17, the instruction execution throughput can be increased. By arranging, interrupt processing can be sped up and higher real-time properties can be realized.

FIG. 6 is a diagram showing an embodiment in which, when an interrupt occurs, for each execution register file, whether to accept the interrupt immediately or after the execution of the instruction can be designated. The register 22 specifies which register file among the register files 18 to 21 requires high-speed interrupt processing during execution. Each bit of register 22 is a register file 18-21
High-speed interrupt processing, that is, by stopping the instruction when an interrupt occurs and specifying the register file that immediately receives the interrupt, gives priority to interrupts over programs and data with relatively low priority and low throughput. Can,
Interrupt processing with high importance can be processed in real time.

Effects of the Invention As described above, according to the present invention, for an interrupt factor requiring high-speed interrupt processing, an interrupt can be immediately received when an interrupt occurs, and high-speed response can be realized. Further, it is possible to raise the priority of the normal program processing over the cause of the interrupt, and it is possible to increase the throughput of the normal program.

[Brief description of the drawings]

FIG. 1 is a block diagram of a real-time processing apparatus according to one embodiment of the present invention, FIG. 2 is a diagram showing an instruction format of the present invention, and FIGS. FIG. 6 is a block diagram of another embodiment of the present invention. 1 ... instruction execution unit, 2 ... interrupt acceptance operation determination unit, 3 ... interrupt unit, 4 ... μROM, 5 ... instruction code, 6 ... instruction code additional bit, 7, 8 ... operand, 9 ... ... Number of instruction cycles, 10 ... Number of execution cycles, 11
...... Comparator, 12 ... Sequence control unit, 13 ... Interrupt cause designation register, 14 ... AND circuit unit, 15 ... Memory area designation register, 16 ... Memory, 17 ... Interrupt high-speed processing designation area, 18 ~ 21 ... register file, 22 ... register file designation register.

Claims (2)

(57) [Claims] A register for designating a specific memory area; and an interrupt immediately received when an interrupt occurs while accessing the memory area specified by the register;
On the other hand, a real-time processing device comprising: an interrupt receiving unit that receives an interrupt after an execution of an instruction being executed is completed when an interrupt occurs while accessing a memory area other than the memory area specified by the register. 2. A real-time processing device capable of executing a plurality of tasks by switching a register file, comprising: a register for designating a specific memory area for each of said register files; and a memory area designated by said register being accessed. When an interrupt occurs, the interrupt is immediately accepted,
On the other hand, a real-time processing device comprising: an interrupt receiving unit that receives an interrupt after an execution of an instruction being executed is completed when an interrupt occurs while accessing a memory area other than the memory area specified by the register.