JP2698147B2 - Method of forming SOI structure - Google Patents
Method of forming SOI structureInfo
- Publication number
- JP2698147B2 JP2698147B2 JP1032007A JP3200789A JP2698147B2 JP 2698147 B2 JP2698147 B2 JP 2698147B2 JP 1032007 A JP1032007 A JP 1032007A JP 3200789 A JP3200789 A JP 3200789A JP 2698147 B2 JP2698147 B2 JP 2698147B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- crystal
- single crystal
- substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 24
- 150000002500 ions Chemical class 0.000 claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 10
- 239000007790 solid phase Substances 0.000 description 13
- 239000012535 impurity Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 イ)産業上の利用分野 本発明はSOI(Silicon on lnsulator)構造の形成方
法に関し、特に固相成長法によりSi膜を形成するものに
関する。The present invention relates to a method for forming an SOI (Silicon on Insulator) structure, and more particularly to a method for forming a Si film by a solid phase growth method.
ロ)従来の技術 絶縁層(絶縁物の基板も含む)上に単結晶Si層を形成
したものは、SOI構造と称され、狭い領域で容易に素子
分離が行なえ、高集積化や高速化が可能なものとして知
られている。そして、従来のSi基板上に素子が作成され
る半導体集積回路(IC)に比べて、特性向上が図られる
ことから盛んに研究開発が行なわれている。B) Conventional technology A single-crystal Si layer formed on an insulating layer (including an insulating substrate) is called an SOI structure, which enables easy element isolation in a narrow area and high integration and high speed. Known as possible. Research and development are being vigorously conducted since the characteristics are improved as compared with a semiconductor integrated circuit (IC) in which elements are formed on a conventional Si substrate.
絶縁層上に単結晶Si膜を形成させるものとして、固相
成長法があり、これは、単結晶Si基板上に、Si基板面の
一部をシードとして絶縁膜上に露出させて絶縁膜を形成
し、シードと絶縁膜上に非晶質Si(以下a−Siと称す)
膜を堆積し、600℃程度の低温でアニールすることで、
横方向に固相成長させてa−Si膜を単結晶化させるもの
である。As a method of forming a single-crystal Si film on an insulating layer, there is a solid-phase growth method. In this method, a part of the surface of a Si substrate is exposed as a seed on a single-crystal Si substrate to form the insulating film. Formed and amorphous Si (hereinafter referred to as a-Si) on the seed and insulating film
By depositing a film and annealing at a low temperature of about 600 ° C,
The a-Si film is monocrystallized by solid phase growth in the lateral direction.
固相成長における横方向の成長距離を伸ばす方法とし
て、絶縁膜上のa−Si膜にP+イオンを高濃度に注入して
から、アニール処理を行なうものがある(Extended Abs
tracts of the 16th Conference on Solid State Devic
es and Materials,Kobe,1984,pp.507−510参照)。As a method of extending the lateral growth distance in solid phase growth, there is a method in which P + ions are implanted at a high concentration into an a-Si film on an insulating film and then annealing is performed (Extended Abs).
tracts of the 16th Conference on Solid State Devic
es and Materials, Kobe, 1984, pp. 507-510).
ハ)発明が解決しようとする課題 しかし、横方向の成長距離を伸ばすために、P+イオン
を3×1020cm-3という高濃度にドーピングするので、固
相成長した単結晶Si膜中の不純物(P)濃度が非常に高
くなってしまい、この固相成長した単結晶Si膜上での半
導体素子の作成は困難であった。C) Problems to be Solved by the Invention However, in order to extend the lateral growth distance, P + ions are doped at a high concentration of 3 × 10 20 cm −3 , so that the solid-phase grown single crystal Si film has Since the impurity (P) concentration becomes extremely high, it has been difficult to form a semiconductor device on the single crystal Si film grown by solid phase growth.
また、Pをドーピングして固相成長させた単結晶Si膜
上に、基板温度800℃ぐらいで、単結晶Si膜をエピタキ
シャル成長させて、不純物濃度の低いSi膜を形成するこ
とが考えられているが、エピタキシャル成長中のオート
ドーピングや素子作成のプロセス中の固相拡散により、
エピタキシャル成長させたSi膜の表面の不純物濃度は1
×1018cm-3以上となってしまい、やはり、半導体素子の
作成には不適当であった。半導体素子を作成する単結晶
Si膜(基盤)の不純物濃度は、1015cm-2ぐらいに低減す
る必要がある。It is also considered that a single crystal Si film is epitaxially grown at a substrate temperature of about 800 ° C. on a single crystal Si film solid-phase grown by doping with P to form a Si film having a low impurity concentration. However, due to auto-doping during epitaxial growth and solid-phase diffusion during the device fabrication process,
The impurity concentration on the surface of the epitaxially grown Si film is 1
× 10 18 cm -3 or more, which was again unsuitable for producing a semiconductor device. Single crystal to make semiconductor device
The impurity concentration of the Si film (base) needs to be reduced to about 10 15 cm -2 .
ニ)課題を解決するための手段 本発明のSOI構造の形成方法は、単結晶Si基台上に該
単結晶Si基台の一部表面が露出する開孔部を有する絶縁
層を形成する工程と、該開孔部において露出する単結晶
Si基台表面及び絶縁層上にPをドーピングした非晶質Si
膜を形成する工程と、該非晶質Si膜をアニールにより固
相成長させて単結晶Si膜とする工程と、該単結晶Si膜中
に、膜に対し不活性なイオンを注入する工程と、該不活
性イオンを注入した基板をアニールする工程と、アニー
ルを施した単結晶Si膜上に更に単結晶Si膜を形成する工
程とを備えたものである。D) Means for Solving the Problems A method for forming an SOI structure according to the present invention comprises a step of forming an insulating layer having an opening on a single crystal Si base, the opening being partially exposed on the single crystal Si base. And the single crystal exposed at the opening
Amorphous Si doped with P on Si base surface and insulating layer
A step of forming a film, a step of solid-phase growing the amorphous Si film by annealing to form a single-crystal Si film, and a step of implanting inert ions into the single-crystal Si film into the film; The method includes a step of annealing the substrate into which the inert ions have been implanted, and a step of further forming a single-crystal Si film on the annealed single-crystal Si film.
ホ)作用 Pをドーピングしたa−Si膜をアニールにより固相成
長させて単結晶Si膜とした後、この単結晶Si膜に不活性
イオンを注入することで、単結晶Si基台と単結晶Si膜の
界面にダメージ領域が形成され、アニールすることで、
このダメージ領域の欠陥にP原子がトラップされ、同時
に外方拡散が起きて、単結晶Si膜の表面のP濃度は低減
される。E) Action After the P-doped a-Si film is solid-phase grown by annealing to form a single-crystal Si film, inert ions are implanted into the single-crystal Si film to form a single-crystal Si base and a single-crystal Si film. A damaged region is formed at the interface of the Si film, and by annealing,
P atoms are trapped by the defects in the damaged region, and at the same time, outward diffusion occurs, so that the P concentration on the surface of the single crystal Si film is reduced.
ヘ)実施例 第1図A乃至Gに本発明の第1の実施例の概略工程図
を示す。尚、本実施例では単結晶Si基台として、単結晶
Si基板を用いているが、基板上に形成された単結晶Si膜
を用いてもよい。F) Embodiment FIGS. 1A to 1G show schematic process diagrams of a first embodiment of the present invention. In this embodiment, the single crystal Si base is used as a single crystal Si base.
Although a Si substrate is used, a single crystal Si film formed on the substrate may be used.
(1)は(100)面を主面とする単結晶Si基台として
の単結晶Si基板で、その表面に絶縁膜として膜厚1000Å
程のSiO2膜(2)をCVD法によって堆積させる(第1図
A)(SiO2膜は、Si基板を直接熱酸化して形成してもよ
い)。(1) is a single-crystal Si substrate serving as a single-crystal Si base having a (100) plane as a main surface.
Causing enough for the SiO 2 film (2) is deposited by CVD (Fig. 1 A) (SiO 2 film may be formed by directly thermally oxidizing the Si substrate).
そして、単結晶Si基板(1)の<100>方向にストラ
イプ形状の開孔部(2′)を、SiO2膜(2)にフォトリ
ソグラフィ技術によりパターン形成する(第1図B)。The opening of the <100> direction in a stripe shape of the single-crystal Si substrate (1) and (2 ') is patterned by photolithography in the SiO 2 film (2) (Figure 1 B).
次に表面全体にSi膜をCVD法により形成する。まず、S
i膜の形成面、特に、開孔部(2′)の部分で露出して
いる単結晶Si基板(1)部分(即ちシード、以下シード
(1′)という)の表面の清浄化を行なう。図示しない
減圧CVD装置内に基板を設置して、10-7Torr台の真空下
で基板温度を約550℃に昇温し、保持した状態で、反応
室内にArガスを導入(流量150cc/min、Ar分圧65mTorr)
し、RF発振器を用いて13.56MHzのRFを印加することによ
りArプラズマを発生させる。このときのRF出力は50W
(乃至70W)程度とする。そして、基板に50〜100V程度
の負電圧を印して、Ar+イオンを基板表面に衝突させて
スパッタ清浄を行なう。清浄化に要するスパッタ時間は
30分程度である。Next, a Si film is formed on the entire surface by a CVD method. First, S
The surface on which the i-film is to be formed, particularly the surface of the single crystal Si substrate (1) exposed at the opening (2 ') (that is, the seed, hereinafter referred to as seed (1')) is cleaned. The substrate was placed in a low-pressure CVD apparatus (not shown), and the temperature of the substrate was raised to about 550 ° C. under a vacuum of the order of 10 −7 Torr. , Ar partial pressure 65mTorr)
Then, Ar plasma is generated by applying RF of 13.56 MHz using an RF oscillator. RF output at this time is 50W
(About 70 W). Then, a negative voltage of about 50 to 100 V is applied to the substrate, and Ar + ions collide against the substrate surface to perform sputter cleaning. Sputtering time required for cleaning
About 30 minutes.
Ar+イオンによる清浄化が終了した時点で、Arガス、R
F出力、バイアス印加を停止し、SiH4ガスを流してa−S
i膜(3)の堆積を行なう(第1図C)。このときの基
板温度は550℃に保持された状態で、堆積速度約250Å/m
inで膜厚約3000Å堆積させる。When the cleaning with Ar + ions is completed, Ar gas, R
Stop F output and bias application, and flow SiH 4 gas to a-S
An i-film (3) is deposited (FIG. 1C). At this time, the substrate temperature was maintained at 550 ° C., and the deposition rate was about 250 ° / m.
Deposit about 3000mm in thickness.
その後、基板全面(注入するのはa−Si膜(3)内)
に加速エネルギー180keV、ドーズ量7×1015個/cm2と、
加速エネルギー100keV、ドーズ量3×1015個/cm2と、加
速エネルギー50keV、ドーズ量2×1015個/cm2の条件
で、3段階にP+イオンを注入する(第1図D)。After that, the whole surface of the substrate (the implantation is in the a-Si film (3))
With an acceleration energy of 180 keV and a dose of 7 × 10 15 particles / cm 2 ,
P + ions are implanted in three stages under the conditions of an acceleration energy of 100 keV and a dose of 3 × 10 15 / cm 2, and an acceleration energy of 50 keV and a dose of 2 × 10 15 / cm 2 (FIG. 1D).
そして、600℃に設定保持された窒素雰囲気の電気炉
内にて、12時間アニール処理を行なう。すると、シード
(1′)の結晶方位を継承しつつ、20μm以上の横方向
の固相成長が起こり、a−Si膜(3)が単結晶化して単
結晶Si膜(3′)となる(第1図E)。Then, an annealing treatment is performed for 12 hours in an electric furnace in a nitrogen atmosphere maintained at 600 ° C. Then, while inheriting the crystal orientation of the seed (1 ′), lateral solid phase growth of 20 μm or more occurs, and the a-Si film (3) is monocrystallized to become a single crystal Si film (3 ′) ( FIG. 1E).
この単結晶Si膜(3′)に、膜に対して不活性なイオ
ンとしてSiイオンを、加速エネルギー200keV、ドーズ量
2×1015個/cm2の条件で注入する。このイオン注入によ
り、SiO2膜(2)と単結晶Si膜(3′)界面付近に、高
濃度のダメージ領域(3a)が形成される(第1図F)。Into this single-crystal Si film (3 '), Si ions as ions inert to the film are implanted under the conditions of an acceleration energy of 200 keV and a dose of 2 × 10 15 / cm 2 . By this ion implantation, a high-concentration damaged region (3a) is formed near the interface between the SiO 2 film (2) and the single-crystal Si film (3 ′) (FIG. 1F).
この基板を、再び窒素雰囲気中で、基板温度900℃と
して60分のアニールする。このアニール処理により、単
結晶Si膜(3′)にドーピングされているPは、ダメー
ジ領域(3a)にタゲッタリングされ、同時に外方拡散さ
れる。This substrate is annealed again in a nitrogen atmosphere at a substrate temperature of 900 ° C. for 60 minutes. By this annealing treatment, P doped in the single-crystal Si film (3 ') is targeted to the damaged region (3a) and simultaneously diffused outward.
この結果、単結晶Si膜(3′)表面の不純物濃度は、
1019cm-3程度に低減される。As a result, the impurity concentration on the surface of the single crystal Si film (3 ') becomes
It is reduced to about 10 19 cm -3 .
最後に、この単結晶Si膜(3′)上に基板温度800℃
程度で、MBE(分子線エピタキシー)法(或いはCVD法
等)により、単結晶Si膜′3′)の結晶方位を継承した
単結晶Si膜(4)を、例えば1μmの厚さに、エピタキ
シャル成長させて(第1図G)、SOI構造が形成され
る。Finally, a substrate temperature of 800 ° C. is placed on this single crystal Si film (3 ′).
The MBE (Molecular Beam Epitaxy) method (or CVD method, etc.) is used to epitaxially grow a single crystal Si film (4) inheriting the crystal orientation of the single crystal Si film '3') to a thickness of, for example, 1 μm. (FIG. 1G), an SOI structure is formed.
このとき、単結晶Si膜(3′)の表面の不純物濃度が
1019cm-3程度に低減されているので、エピタキシャル成
長時にオートドーピング(或いは固相拡散)が起きて
も、単結晶Si膜(4)の表面付近の不純物濃度が1014cm
-3程度に抑えられる。At this time, the impurity concentration on the surface of the single crystal Si film (3 ') becomes
Since it is reduced to about 10 19 cm -3, the impurity concentration near the surface of the single crystal Si film (4) is 10 14 cm even if auto-doping (or solid phase diffusion) occurs during epitaxial growth.
-3 can be suppressed.
ト)発明の効果 本発明は、以上の説明から明らかな如く、Pをドーピ
ングして固相成長させた単結晶Si膜に、不活性イオンを
注入し、アニールすることで、単結晶Si膜の表面の不純
物濃度を1019cm-3程度に抑え、更にこの単結晶Si膜上に
単結晶Si膜をエピタキシャル成長させている。その結
果、表面付近の不純物濃度は1014cm-3程度に低減され、
半導体素子の作成に適したSOI構造の基板が提供でき、
半導体集積回路における高集積化や特性の向上に寄与で
ききる。G) Effects of the present invention As is apparent from the above description, the present invention provides a method for implanting an inert ion into a single crystal Si film which has been solid-phase grown by doping with P, and annealing the single crystal Si film. The impurity concentration on the surface is suppressed to about 10 19 cm −3 , and a single-crystal Si film is epitaxially grown on the single-crystal Si film. As a result, the impurity concentration near the surface is reduced to about 10 14 cm -3 ,
We can provide a substrate with SOI structure suitable for making semiconductor devices,
It can contribute to high integration and improvement of characteristics in a semiconductor integrated circuit.
第1図A乃至Gは本発明の一実施例の工程説明図であ
る。 (1)……単結晶Si基板(単結晶Si基台)、(1′)…
…シート、(2)……SiO2膜(絶縁膜)、(2′)……
開孔部、(3)……a−Si基膜、(3′)……単結晶Si
膜、(4)……単結晶Si膜。FIGS. 1A to 1G are process explanatory views of one embodiment of the present invention. (1) ... single crystal Si substrate (single crystal Si base), (1 ') ...
... sheet, (2) ...... SiO 2 film (insulating film), (2 ') ...
Opening, (3) ... a-Si base film, (3 ') ... single crystal Si
Film, (4) ... single crystal Si film.
Claims (1)
面が露出する開孔部を有する絶縁層を形成する工程と、 該開孔部において露出する単結晶Si基台表面及び絶縁層
上にPをドーピングした非晶質Si膜を形成する工程と、 該非晶質Si膜をアニールにより固相成長させて単結晶Si
膜とする工程と、 該単結晶Si膜中に、膜に対し不活性なイオンを注入する
工程と、 該不活性イオンを注入した基板をアニールする工程と、 アニールを施した単結晶Si膜上に更に単結晶Si膜を形成
する工程とを備えることを特徴とするSOI構造の形成方
法。A step of forming an insulating layer on a single crystal Si base having an opening exposing a partial surface of the single crystal Si base; and a step of exposing the single crystal Si base exposed at the opening. A step of forming a P-doped amorphous Si film on the surface and the insulating layer;
A step of forming a film; a step of implanting inactive ions into the single crystal Si film into the film; a step of annealing the substrate into which the inert ions are implanted; And forming a single crystal Si film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1032007A JP2698147B2 (en) | 1989-02-10 | 1989-02-10 | Method of forming SOI structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1032007A JP2698147B2 (en) | 1989-02-10 | 1989-02-10 | Method of forming SOI structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02211616A JPH02211616A (en) | 1990-08-22 |
| JP2698147B2 true JP2698147B2 (en) | 1998-01-19 |
Family
ID=12346821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1032007A Expired - Fee Related JP2698147B2 (en) | 1989-02-10 | 1989-02-10 | Method of forming SOI structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2698147B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007019170A (en) * | 2005-07-06 | 2007-01-25 | Fuji Electric Holdings Co Ltd | Partial SOI substrate, method for manufacturing partial SOI substrate, and SOI substrate |
| FR2897982B1 (en) * | 2006-02-27 | 2008-07-11 | Tracit Technologies Sa | METHOD FOR MANUFACTURING PARTIALLY-LIKE STRUCTURES, COMPRISING AREAS CONNECTING A SURFACE LAYER AND A SUBSTRATE |
| JP2007329200A (en) * | 2006-06-06 | 2007-12-20 | Toshiba Corp | Manufacturing method of semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5945996A (en) * | 1982-09-03 | 1984-03-15 | Nec Corp | Vapor growth of semiconductor |
| JPS6158879A (en) * | 1984-08-29 | 1986-03-26 | Nec Corp | Preparation of silicon thin film crystal |
| JPH0810669B2 (en) * | 1986-04-11 | 1996-01-31 | 日本電気株式会社 | Method of forming SOI film |
-
1989
- 1989-02-10 JP JP1032007A patent/JP2698147B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02211616A (en) | 1990-08-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5888297A (en) | Method of fabricating SOI substrate | |
| US4808546A (en) | SOI process for forming a thin film transistor using solid phase epitaxy | |
| JP2698147B2 (en) | Method of forming SOI structure | |
| JPS60140813A (en) | Manufacture of semiconductor device | |
| JPH021115A (en) | Formation of crystal | |
| JPS60152018A (en) | Manufacture of semiconductor thin film crystal layer | |
| JPH0491425A (en) | Manufacture of semiconductor device | |
| JP2872425B2 (en) | Method for forming semiconductor device | |
| JPH0464455B2 (en) | ||
| JP2994667B2 (en) | Method of forming SOI structure | |
| JPH04206932A (en) | Semiconductor device and manufacture thereof | |
| JP2755653B2 (en) | Method of forming SOI structure | |
| JPH0810669B2 (en) | Method of forming SOI film | |
| JP2737152B2 (en) | SOI forming method | |
| JPS6386565A (en) | Manufacture of semiconductor device | |
| JP2565192B2 (en) | Method for manufacturing semiconductor device | |
| JPH02208920A (en) | Soi structure forming method | |
| JPH02302024A (en) | Solid epitaxial growth | |
| JPH09115922A (en) | Method for manufacturing semiconductor device | |
| JPH03101121A (en) | Formation of soi structure | |
| JPH04242958A (en) | Manufacture of semiconductor device | |
| JP2793241B2 (en) | SOI formation method | |
| JPH0311618A (en) | Semiconductor manufacturing method | |
| JP2705374B2 (en) | Method for forming group IV element semiconductor on III-V compound semiconductor | |
| JPH08102532A (en) | Manufacture of ion implantation substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |