JP2702576B2 - Method for manufacturing field effect semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a field effect semiconductor device including a field effect transistor element for an integrated circuit. is there.

[Conventional technology]

In the field of an integrated circuit using a field effect element using a silicon semiconductor, for example, a so-called MOS transistor,
The miniaturization of constituent elements has been greatly advanced, and research and development are being performed in the submicron region. Various structures and manufacturing methods have been improved in order to miniaturize devices such as MOS. However, in contrast to the high performance and high function due to the miniaturization, short channel effect, hot carrier effect, etc. Deterioration of reliability due to the influence has been observed, and the power supply voltage of the device using the MOS has been forced to decrease.

Under such circumstances, research on a device having a new structure is being promoted. For example, as a report on an element structure capable of obtaining a large power supply voltage to be supplied to a MOS transistor and a method of manufacturing the same, a GOLD (gate-drain overlapped LLD) has been reported.
DD) [Izawa et al., 1987 International Electron Device Meeting Technical Digest of Papers, pp. 38-41].

To understand the background of conventional MOS technology, this GOLD
Will be described.

5 (a) to 5 (d) are process cross-sectional views illustrating a method for manufacturing a main part of a conventional MOS transistor. As shown in FIG. 5A, a semiconductor layer 10 of p-type silicon single crystal is formed.
On top of the above, a gate oxide film 112, a thin lower polysilicon film 120, a thick upper polysilicon film 150, and a silicon oxide film 160 are sequentially formed on a gate formation scheduled portion A of a multilayer film. A resist pattern 170 is formed by a normal photolithography process. At the interface between the thin polysilicon film 120 and the thick polysilicon film 150, a natural oxide film (not shown) having a thickness of 0.5 to 1 nm is formed.

Next, as shown in FIG.
After forming the silicon oxide film pattern 160A using 0 as a mask, the thick upper polysilicon film 150 is etched by dry etching having a high selectivity with respect to the silicon oxide film pattern 160A using the silicon oxide film pattern 160A as a mask. I do. At this time, the natural oxide film on the surface of the thin lower polysilicon film 120 is used as an etching stopper, and the polysilicon film 150 is etched in an isotropic shape to form a polysilicon film pattern 150B. Then, the silicon oxide film pattern 160
A, phosphorus is ion-implanted substantially perpendicularly (in the Z direction) to the semiconductor layer 100 using the polysilicon film pattern 150B as a mask, thereby forming the semiconductor layer 100 of p-type silicon single crystal.
N-type semiconductor region 200 serving as a source and a drain therein
X, 200Y is formed.

Next, as shown in FIG. 5C, the silicon oxide films 210X and 210Y are selectively left on the side surfaces of the silicon oxide film pattern 160A and the polysilicon film pattern 150B by anisotropic etching. Then, these silicon oxide films 210X, 210
Using the Y as a mask, the thin polysilicon film 120 is etched to form a polysilicon film pattern substantially serving as a gate electrode.
Form 120B. Finally, as shown in FIG. 5D, high-concentration arsenic is ion-implanted substantially perpendicularly (in the Z direction) to the semiconductor layer 100 using the remaining silicon oxide films 210X and 210Y as a mask. As a result, n-type semiconductor regions 220X and 220Y serving as part of the source and part of the drain are formed in the semiconductor layer 100 of the p-type silicon single crystal.

The characteristics of the conventional MOS transistor manufactured in such a process include the following.

The n-type semiconductor region 200Y at the end of the drain overlaps the polysilicon film pattern 120B for the gate electrode (0.2 μm or more), and the electric field applied to the end of the drain is reduced due to this overlap. MOS devices formed by a usual method (for example, LDD [lightly
doped drain] structure MOS).
The generation of hot carriers at the drain end of
Excellent reliability has been obtained. Further, as the channel length is reduced, the threshold voltage (Vt) is reduced, that is, the so-called short channel effect is small. Therefore, a MOS having an effective channel length smaller than that of a conventional MOS can be realized.
Since the channel length can be reduced in this way, a MOS transistor having a large transconductance (gm) and a driving force is obtained.

[Problems to be solved by the invention]

However, MO of GOLD manufactured in this way
The S transistor has the following problems.

(1) The gate length of the polysilicon film pattern 120B serving as the gate electrode shown in FIGS. 5 (c) and 5 (d) is left longer than the length of the silicon oxide film pattern 160A normally processed with the minimum dimension. Since the length is increased by the shape, that is, the thickness of the silicon oxide films 210X and 210Y called side walls, it becomes larger than the gate length of the conventional MOS, and the degree of integration is reduced.

(2) In the step shown in FIG. 5B, when the polysilicon film 150 is etched, a very thin natural oxide film is used as an etching stopper, so that the thick upper polysilicon film 150 is etched. Requires a special dry etching etchant having a large (several hundred times or more) etching selectivity, but at present, the polysilicon film 150 has a large selectivity several hundred times higher than that of a native oxide film or the like. Some etches are prone to isotropic etching, so the upper polysilicon film pattern
Thinning occurs in 150B, resulting in increased wiring resistance,
High-speed signal input response to the gate is poor.

Also, if the upper polysilicon film pattern 150B becomes thinner, the oxide film pattern 160A overhangs, and the coverage shape of the silicon oxide films 210X and 210Y left on the side surfaces of the polysilicon film pattern 150B deteriorates.
Further, since the silicon oxide films 210X and 210Y are used as an etching mask for the lower polysilicon film 120A serving as a gate electrode, it is likely to cause a variation in gate width.

When a thick oxide film of 3 nm or more is used instead of a thin native oxide film of about 1 nm, it becomes difficult to electrically connect the upper polysilicon film 150 to the lower polysilicon film 120.

In view of the above problems, an object of the present invention is to provide a method of manufacturing a field-effect semiconductor device capable of achieving high performance and high integration by reducing and miniaturizing the wiring resistance of a gate electrode. Things.

[Means for solving the problem]

The method of manufacturing a field-effect semiconductor device according to claim 1, wherein a first insulating film for a gate is formed on the semiconductor layer of the first conductivity type, and the first insulating film for the gate is formed. Forming a first conductive film serving as a gate electrode thereon, forming a second conductive film on the first conductive film, and etching the second conductive film into a wiring shape; An oblique ion implantation method using the wiring-shaped second conductive film as a mask to allow the second conductive type impurity to pass through the first conductive film so that the impurity in the first conductive type semiconductor layer is removed. A step of forming a second conductive type first semiconductor region serving as a source and a second conductive type second semiconductor region serving as a drain by injecting the semiconductor layer directly below a portion where a gate electrode is to be formed on the source side and the drain side; And leaving a second insulating film on a side surface of the second conductive film having the wiring shape. A step of, second obtained by the leaving
Forming the first conductive film in a wiring shape using the insulating film and the second conductive film in the wiring shape as a mask; and forming the remaining second insulating film and the second conductive film in the wiring shape.
An impurity of the second conductivity type is implanted into the source side and the drain side in the semiconductor layer of the first conductivity type by an ion implantation method using the conductive film as a mask, and the second conductivity type impurity serving as a part of the source is implanted. Forming a third semiconductor region and a fourth semiconductor region of the second conductivity type that becomes a part of the drain.

The method of manufacturing a field-effect semiconductor device according to claim 2, wherein a first insulating film for a gate is formed on the semiconductor layer of the first conductivity type, and the first insulating film for the gate is formed. Forming a first conductive film serving as a gate electrode on the first conductive film, forming a second conductive film on the first conductive film,
Etching the second conductive film into a wiring shape;
An impurity of a second conductivity type is transmitted through the first conductive film by a nearly vertical ion implantation method using the wiring-shaped second conductive film as a mask, so that the first conductive type semiconductor layer is formed. Forming a first semiconductor region of the second conductivity type serving as a source by injecting directly below a portion where a gate electrode is to be formed on the source side, and obliquely using the wiring-shaped second conductive film as a mask. An impurity of the second conductivity type is transmitted through the first conductive film by an ion implantation method, and is implanted into the semiconductor layer of the first conductivity type immediately below a portion where a gate electrode is to be formed on the drain side. Forming a second semiconductor region of a second conductivity type, forming a second insulating film on a side surface of the wiring-shaped second conductive film, and forming the remaining second insulating film. And the second conductive film having the wiring shape as a mask. Forming the first conductive film into a wiring shape by ion implantation using the remaining second insulating film and the second conductive film having the wiring shape as masks. Impurities are implanted into the source and drain sides of the semiconductor layer of the first conductivity type to form a third semiconductor region of the second conductivity type that becomes part of the source and a second conductivity type that becomes part of the drain. And forming a fourth semiconductor region.

The method for manufacturing a field-effect semiconductor device according to claim 3, wherein a first insulating film for a gate is formed on the semiconductor layer of the first conductivity type, and the first insulating film for the gate is formed. Forming a first conductive film serving as a gate electrode on the first conductive film, forming a second conductive film on the first conductive film,
Etching the second conductive film into a wiring shape;
The oblique ion implantation method using the wiring-shaped second conductive film as a mask is used to remove the second conductive type impurity from the first conductive type.
Through the conductive film, and selectively implanted immediately below the portion where the gate electrode is to be formed on the drain side in the semiconductor layer of the first conductive type, thereby forming a second semiconductor region of the second conductive type serving as a drain. Forming, forming a second conductive film on the side surface of the wiring-shaped second conductive film, forming the remaining second insulating film and the wiring-shaped second conductive film. A step of forming the first conductive film into a wiring shape using the mask as a mask, and a second ion implantation method using the remaining second insulating film and the second conductive film having the wiring shape as a mask. A conductivity type impurity is implanted into the source side and the drain side in the first conductivity type semiconductor layer, and a second conductivity type third semiconductor region serving as a source and a second conductivity type serving as a part of the drain are provided. And forming a fourth semiconductor region.

The method for manufacturing a field-effect semiconductor device according to claim 4 is the method for manufacturing a field-effect semiconductor device according to claim 1, 2, or 3, wherein the first conductive film is non-single-layered. It is characterized by using a crystalline semiconductor film.

The method of manufacturing a field-effect semiconductor device according to claim 5 is the method of manufacturing a field-effect semiconductor device according to claim 1, 2, 3, or 4. It is characterized in that a metal or a metal compound is used as the film.

[Action]

According to the method for manufacturing a field-effect semiconductor device of the present invention, the second semiconductor region of the second conductivity type serving as the drain is formed by oblique ion implantation, so that the gate and the drain are likely to overlap. Therefore, the shape of the second insulating film (sidewall) left to control the amount of overlap can be reduced.

According to the method of manufacturing a field-effect semiconductor device described in claims (2) and (3), the second semiconductor region of the second conductivity type serving as the drain is formed by oblique ion implantation, and the second semiconductor region serving as the source is formed. Since the two-conductivity-type first semiconductor region is formed by a nearly vertical ion implantation method, the second semiconductor region serving as a drain is formed.
The conductive second semiconductor region can sufficiently overlap the gate electrode, and the source first semiconductor region can be formed with a small size.

According to the method of manufacturing a field-effect semiconductor device according to claims (4) and (5), by arbitrarily selecting a combination of the first conductive film and the second conductive film, an anisotropic material having a poor etching selectivity can be obtained. Even in the case of dry etching, it is easy to etch the upper second conductive film.

According to the method of manufacturing a field-effect semiconductor device according to claim (5), by arbitrarily selecting a combination of the first conductive film and the second conductive film, the upper conductive film can be made of poly-silicon. By using a metal film such as tungsten or molybdenum or a metal compound such as tungsten silicide or molybdenum silicide in addition to a non-single crystalline semiconductor film such as silicon or amorphous silicon, the wiring resistance of the gate can be sufficiently reduced.

〔Example〕

1 (a), (b), (c), (d), (e),
FIGS. 7F and 7G are cross-sectional views illustrating a method of manufacturing a main part of the N-channel MOS transistor according to the first embodiment of the present invention.

As shown in FIG. 1A, a film thickness 500 for element isolation is formed on a semiconductor layer 100 (or substrate) of p-type silicon single crystal.
oxide film 110 having a thickness of about 10 to 30 nm as a first insulating film.
Gate oxide film 112 and a film thickness of 50 to 150 to be the first conductive film.
nm polysilicon film 120 and a second conductive film thickness of 200
After a polysilicon film 150 having a thickness of about 300 nm and a silicon oxide film 160 having a thickness of about 200 nm are sequentially formed, a resist pattern 170 having a wiring shape having a width of 0.5 to 0.8 μm is formed on a gate formation scheduled portion A.

Next, as shown in FIG.
The silicon oxide film 160 is etched by anisotropic reactive ion etching using 0 as a mask to form a wiring-shaped silicon oxide film pattern 160A, and is selectively etched by isotropic etching. The non-single-crystal polysilicon film 150 serving as a conductive film is etched to form a wiring-shaped polysilicon film pattern 150A. At this time, a very thin natural oxide film (not shown) was used as an etching stopper. And furthermore, the resist pattern 17
After removing 0, for example, when a plane perpendicular to the main plane of the semiconductor layer 100 is set as a 0-degree reference plane, an injection angle of 10 degrees or more (20 to 40 degrees) from the reference plane and the drain side (X direction)
Oblique ion implantation of phosphorus at a dose of 5 × 10 ¹² to 1 × 10 ¹⁵ cm ^{-2 from} the n-type semiconductor region 200A to be a part of the source and the drain in the p-type silicon single crystal semiconductor layer 100 An n-type semiconductor region 200B is formed. Note that the resist pattern 170 does not necessarily need to be removed when phosphorus ions are implanted.

Next, as shown in FIG. 1C, similarly to FIG. 1B, the dose amount is 5 × 10 ¹² to 1 × 10 2 from the source side (Y direction).
An oblique ion implantation of phosphorus of ¹⁵ cm ^-2 is performed, and an n-type semiconductor region 200E (first semiconductor region) serving as a part of a source and an n-type semiconductor serving as a drain are introduced into the p-type silicon single crystal semiconductor layer 100. A type semiconductor region 200F (second semiconductor region) is formed.

Next, as shown in FIG.
A silicon oxide film 210 of nm is deposited.

Next, as shown in FIG. 1E, the silicon oxide film 210 is formed.
Is etched over the entire surface by anisotropic reactive ion etching to form silicon oxide film patterns 160A and 150A.
Silicon oxide films 210A and 21 to be sidewalls on the side of A
0B (second insulating film) is left. Further, the polysilicon film 120 is etched using the silicon oxide films 210A, 210B and the like as a mask to form a wiring-shaped polysilicon film pattern 120A substantially serving as a gate electrode.

Next, as shown in FIG.
Direction, for example by less than 10 degrees angle of implantation) ion implantation to the main plane of the semiconductor layer 100, a dose of 2 to 9 × 10 ¹⁵
By implanting arsenic of cm ^−2, an n-type semiconductor region 220A serving as a part of the source is formed in the p-type silicon single crystal semiconductor layer 100.
(Third semiconductor region) and an n-type semiconductor region 220B (Fourth semiconductor region) to be a part of the drain are formed. At this time, an n-type semiconductor region 200F substantially serving as a drain is left at the end of the drain, and an n-type semiconductor region 200E serving as a source is left.

Next, as shown in FIG. 1 (g), after an insulating silicon oxide film 300 is deposited on the entire surface, contact openings such as a source and a drain are formed according to a normal manufacturing method.
Further, a source aluminum metal electrode 310A, a drain aluminum metal electrode 310B, and the like are formed.

In the MOS transistor manufactured by such a method, the n-type semiconductor region 200D at the end of the drain sufficiently overlaps (0.2 μm or more) with the polysilicon film pattern 120A for the gate electrode. Due to this overlap, the electric field applied to the drain end is smaller than that of a MOS element formed by a normal method, so that the generation of hot carriers at the drain end is suppressed, and excellent reliability is achieved. can get. Another major feature of the manufacturing method is that the drain is formed by oblique ion implantation, so that the overlap of the drain with the gate can be increased as compared with the normal GOLD manufacturing method. Silicon oxide film 210A, 2
The film thickness of 10B was reduced by about 0.2 μm in total on both sides as compared with the conventional one, the size of the transistor could be reduced, and the integration degree could be improved.

In the first embodiment, various manufacturing extensions,
Change is possible. For example, the p-type silicon single crystal semiconductor layer 100 may be a p-type well region in addition to the p-type silicon substrate. Further, in the first embodiment, the ion implantation into the p-type silicon single crystal semiconductor layer 100 for controlling the inversion (threshold) voltage of the MOS gate is omitted, but it can be adopted if necessary. The silicon oxide film pattern 16
In the case of 0A, since the step of the gate portion is increased, it is not always necessary to perform the oblique ion implantation of phosphorus as shown in FIGS. 1 (b) and 1 (c). Since there is a possibility that the polysilicon film pattern 150A may penetrate due to a so-called channeling phenomenon, it is preferable to form the silicon oxide film pattern 160A. Also, the first
In the step shown in FIG. 2F, the n-type semiconductor region 220A (third semiconductor region) and the n-type semiconductor region 220B (fourth semiconductor region), which become part of the source and the drain, are implanted with arsenic ions. When forming, the polysilicon film 120
The (first conductive film) is implanted after etching, but in some cases, a silicon oxide film serving as a sidewall
Before the formation of 210A and 210B and etching of the polysilicon film 120, the n-type semiconductor region 220A (third semiconductor region) and the n-type semiconductor region 220B (fourth Semiconductor region) may be formed.

2 (a), (b), (c), (d), (e),
(F), (g) is a process sectional view for explaining a method of manufacturing the main part of the N-channel MOS transistor according to the second embodiment of the present invention.

As shown in FIG. 2A, a film thickness of about 500 for element isolation is formed on a p-type silicon single crystal semiconductor layer 100 (or substrate).
oxide film 110 having a thickness of about 10 to 30 nm as a first insulating film.
Gate oxide film 112 and a film thickness of 50 to 150 to be the first conductive film.
nm polysilicon film 120 and a second conductive film thickness of 200
After sequentially forming a tungsten silicide (WSi ₂ ) film 152 having a thickness of about 300 nm and a silicon oxide film 160 having a thickness of about 200 nm, a resist pattern 170 having a wiring shape having a width of 0.5 to 0.8 μm is formed on a gate formation expected portion A. Form.

Next, as shown in FIG.
The silicon oxide film 160 is anisotropically etched using 0 as a mask to form a wiring-shaped silicon oxide film pattern.
160A is formed, and the tungsten silicide film 152 to be a second conductive film is selectively etched by anisotropic etching to form a wiring-shaped tungsten silicide film pattern 152A. Further, after the resist pattern 170 is further removed, oblique ion implantation of phosphorus at a dose of 5 × 10 ¹² to 1 × 10 ¹⁵ cm ⁻² from the drain side (X direction) (for example, in the main plane of the semiconductor layer 100). 0 perpendicular to the plane
10 degrees or more from the reference plane (20-40 degrees)
Implantation angle) to form a semiconductor layer 10 of p-type silicon single crystal.
An n-type semiconductor region 200A serving as a part of the source and an n-type semiconductor region 200B serving as the drain are formed in 0. When obliquely implanting phosphorus, the resist pattern 170
Need not necessarily be removed.

Next, as shown in FIG. 2 (c), similarly to FIG. 2 (b), the dose amount is 5 × 10 ¹² to 1 × 10 2 from the source side (Y direction).
An oblique ion implantation of phosphorus of ¹⁵ cm ^-2 is performed, and an n-type semiconductor region 200E (first semiconductor region) serving as a source and an n-type semiconductor serving as a drain are introduced into the p-type silicon single crystal semiconductor layer 100. A region 200F (second semiconductor region) is formed.

Next, as shown in FIG.
A silicon oxide film 210 of nm is deposited.

Next, as shown in FIG.
Is etched over the entire surface by anisotropic reactive ion etching.
160A, and silicon oxide films 210A and 210B serving as sidewalls on the side surfaces of the tungsten silicide film pattern 152A.
(The second insulating film) is left. Further, the polysilicon film 120 is etched using the silicon oxide films 210A, 210B and the like as a mask to form a wiring-shaped polysilicon film pattern 120A substantially serving as a gate electrode.

Next, as shown in FIG.
Direction, for example by less than 10 degrees angle of implantation) ion implantation to the main plane of the semiconductor layer 100, a dose of 2 to 9 × 10 ¹⁵
By implanting arsenic of cm ^−2, an n-type semiconductor region 220A serving as a part of the source is formed in the p-type silicon single crystal semiconductor layer 100.
(Third semiconductor region) and an n-type semiconductor region 220B (Fourth semiconductor region) to be a part of the drain are formed. At this time, an n-type semiconductor region 220F substantially serving as a drain is left at the end of the drain, and an n-type semiconductor region 200E serving as a source is left.

Next, as shown in FIG. 2 (g), after an insulating silicon oxide film 300 is deposited on the entire surface, contact openings such as a source and a drain are formed in accordance with a normal manufacturing method.
Further, a source aluminum metal electrode 310A, a drain aluminum metal electrode 310B, and the like are formed.

In the MOS transistor manufactured by such a method, the end of the drain is sufficiently overlapped (0.2 μm or more) with the polysilicon film pattern 120A for the gate electrode. The electric field applied to the edge was formed by the usual method
Since the size is smaller than that of the MOS element, generation of hot carriers at the end of the drain is suppressed, and excellent reliability is obtained. In addition, since the tungsten silicide film 152 (second conductive film) having a small electric resistance can be etched by anisotropic dry etching, a gate having a good coverage shape and a very small wiring electric resistance without a thin pattern can be obtained. An electrode is obtained. 2 (b) and 2 (c), oblique ion implantation of phosphorus is performed, but instead of the polysilicon film 120 (first conductive film) through which ions pass, amorphous silicon is used. With,
This is preferable because a so-called channeling phenomenon can be further prevented.

The silicon oxide film pattern 160A is not always necessary, but it is preferable to form the silicon oxide film pattern 160A because phosphorus ions may penetrate the tungsten silicide film pattern 152A due to a so-called channeling phenomenon.

3 (a), (b), (c), (d), (e),
(F), (g) is a process sectional view for explaining a method of manufacturing the main part of the N-channel MOS transistor according to the third embodiment of the present invention.

As shown in FIG. 3A, a film thickness of about 500 for element isolation is formed on a semiconductor layer 100 (or substrate) of p-type silicon single crystal.
oxide film 110 having a thickness of about 10 to 30 nm as a first insulating film.
Gate oxide film 112 and a film thickness of 50 to 150 to be the first conductive film.
nm polysilicon film 120 and a second conductive film thickness of 200
After sequentially forming a tungsten silicide (WSi ₂ ) film 152 having a thickness of about 300 nm and a silicon oxide film 160 having a thickness of about 200 nm, a resist pattern 170 having a wiring shape having a width of 0.5 to 0.8 μm is formed on a gate formation expected portion A. Form.

Next, as shown in FIG.
The silicon oxide film 160 is anisotropically etched using 0 as a mask to form a wiring-shaped silicon oxide film pattern.
160A is formed, and the tungsten silicide film 152 serving as the second conductive film is selectively etched to form a wiring-shaped tungsten silicide film pattern 152A.
And further, after removing the resist pattern 170,
Dose amount 5 × 10 ¹² -1 × 10 ¹⁵ from drain side (X direction)
Oblique ion implantation of phosphorus of cm ^-2 (for example, when a plane perpendicular to the main plane of the silicon single crystal semiconductor layer 100 is set as a reference plane of 0 degree, implantation of 10 degrees or more (20 to 40 degrees) from the reference plane) Angle) is performed to form an n-type semiconductor region 200A serving as a part of the source and an n-type semiconductor region 200B serving as the drain in the p-type silicon single crystal semiconductor layer 100. Note that, when phosphorus is ion-implanted in the oblique direction, the resist pattern 170 does not necessarily have to be removed.

Next, as shown in FIG. 3 (c), phosphorus ion implantation at a dose of 5 × 10 ¹² to 1 × 10 ¹⁵ cm ⁻² is performed at an implantation angle (Z direction) almost perpendicular to the p-type. An n-type semiconductor region 200G (body 1) serving as a source is formed in a silicon single crystal semiconductor layer 100.
Semiconductor region 200F), n-type semiconductor region 200F serving as a drain
(A second semiconductor region) is formed.

After forming an n-type semiconductor region 200G (first semiconductor region) serving as a source and an n-type semiconductor region 200F (second semiconductor region) serving as a drain shown in FIG.
An n-type semiconductor region 200A serving as a part of the source and an n-type semiconductor region 200B serving as the drain shown in FIG. 3B may be formed.

Next, as shown in FIG. 3D, a silicon oxide film 210 of 100 to 200 nm is deposited on the entire surface.

Next, as shown in FIG.
Is etched over the entire surface by anisotropic reactive ion etching to form a wiring-shaped silicon oxide film pattern 160.
A, Silicon oxide films 210A and 210B (second insulating films) serving as sidewalls are left on the side surfaces of the tungsten silicide film pattern 152A. Furthermore, this silicon oxide film 210A, 2
The polysilicon film 120 is etched using 10B or the like as a mask to form a wiring-shaped polysilicon film pattern 120A substantially serving as a gate electrode.

Next, as shown in FIG. 3 (f), almost vertical (Z direction)
Dose of 2 to 9 depending on the ion implantation method at an implantation angle close to
By implanting arsenic of × 10 ¹⁵ cm ^−2, the n-type semiconductor region 2 serving as a part of the source is introduced into the p-type silicon single crystal semiconductor layer 100.
20A (third semiconductor region) and an n-type semiconductor region 220B (fourth semiconductor region) to be a part of the drain are formed. At this time, the end of the drain is substantially n
The semiconductor region 200F of the type is left to sufficiently overlap with the polysilicon film pattern 120A serving as the gate electrode, and the n-type semiconductor region 200G serving as the source is slightly left.

Next, as shown in FIG. 3 (g), after an insulating silicon oxide film 300 is deposited on the entire surface, openings for contacts such as a source and a drain are formed in accordance with a normal manufacturing method. An aluminum metal electrode 310A, a drain aluminum metal electrode 310B, and the like are formed.

In the MOS transistor manufactured by such a method, the end of the drain (semiconductor region 200F) sufficiently overlaps with the polysilicon film pattern 120A for the gate electrode. The electric field applied to the edge is the MO formed by the usual method.
Since the size is smaller than that of the S element, generation of hot carriers at the end of the drain is suppressed, and excellent reliability is obtained. The second layer of the upper layer is formed by anisotropic dry etching.
Tungsten silicide film with low resistance, which is a conductive film
Since 152 can be etched, a gate electrode having a good coverage shape and a very small wiring electric resistance without a narrow pattern can be obtained. Further, by forming the semiconductor region 200G (first semiconductor region) serving as a source by an ion implantation method at an implantation angle nearly perpendicular to the n-type, the source region shown in FIGS. 3 (f) and 3 (g) is formed. Semiconductor area 20
Since 0G (first semiconductor region) can be formed with a small size, a good MOS transistor having a small source resistance can be obtained. In FIG. 3C, phosphorus ions are implanted, but the polysilicon film 120 through which the ions pass is used.
It is preferable to use an amorphous silicon film instead of the (first conductive film) because a so-called channeling phenomenon can be prevented.

The silicon oxide film pattern 160A is not always necessary, but it is preferable to form the silicon oxide film pattern 160A because phosphorus ions may penetrate the tungsten silicide film pattern 152A due to a so-called channeling phenomenon.

4 (a), (b), (c), (d), (e),
(F) is a process sectional view illustrating a method for manufacturing the main part of the N-channel MOS transistor according to the fourth embodiment of the present invention.

As shown in FIG. 4A, an oxide film 110 having a thickness of about 500 nm for element isolation, a first insulating film, and a semiconductor layer 100 (or substrate) of p-type silicon single crystal are formed. About film thickness
A gate oxide film 112 having a thickness of 10 to 30 nm, a polysilicon film 120 having a thickness of 50 to 150 nm serving as a first conductive film, and a tungsten silicide (WSi ₂ ) film having a thickness of 200 to 300 nm serving as a second conductive film
After sequentially forming a silicon oxide film 160 and a silicon oxide film 160 having a thickness of about 200 nm, a resist pattern 170 in the form of a wiring having a width of 0.5 to 0.8 μm is formed on the portion A where the gate is to be formed.

Next, as shown in FIG.
The silicon oxide film 160 is anisotropically etched using 0 as a mask to form a wiring-shaped silicon oxide film pattern.
160A is formed, and the tungsten silicide film 152 serving as the second conductive film is selectively etched to form a wiring-shaped tungsten silicide film pattern 152A.
Further, after the resist pattern 170 is removed, a resist pattern 180 is formed on the source electrode formation scheduled portion B side by a normal photolithography process, and for example, a plane perpendicular to the main plane of the semiconductor layer 100 is set to 0 degree. As a reference plane, at an implantation angle of 10 degrees or more (20 to 40 degrees) from the reference plane, an oblique ion of phosphorus with a dose of 5 × 10 ¹² to 1 × 10 ¹⁵ cm ^-2 from the drain side (X direction). Implantation is performed to form an n-type semiconductor region 200B serving as a drain in the p-type silicon single crystal semiconductor layer 100.
(A second semiconductor region) is formed. By such oblique ion implantation, an n-type semiconductor region serving as a drain which is greatly overlapped with the gate electrode is provided immediately below the drain-side gate electrode end of the tungsten silicide film pattern 152A which becomes a part of the gate electrode. 200B (second semiconductor region) is formed.

Next, as shown in FIG.
After removing 0, a silicon oxide film 210 having a thickness of 100 to 200 nm is deposited on the entire surface.

Next, as shown in FIG. 4D, the silicon oxide film 210 is formed.
Is etched over the entire surface by anisotropic reactive ion etching.
160A, the silicon oxide films 210A and 210B (second
Is left behind. Furthermore, this silicon oxide film 21
The polysilicon film 120 is etched using the masks 0A, 210B and the like to form a wiring-shaped polysilicon film pattern 120A substantially serving as a gate electrode.

Next, as shown in FIG. 4 (e), almost vertical (Z direction)
Dose of 2 to 9 depending on the ion implantation method at an implantation angle close to
By implanting arsenic of × 10 ¹⁵ cm ⁻² , an n-type semiconductor region 220A (third semiconductor region) serving as a source and an n-type semiconductor region serving as a part of a drain are introduced into the p-type silicon single crystal semiconductor layer 100. A semiconductor region 220B (fourth semiconductor region) is formed. At this time,
At the end of the drain, an n-type semiconductor region 200B substantially serving as a drain is left sufficiently overlapping with the polysilicon film pattern 120A serving as a gate electrode.

Next, as shown in FIG. 4 (f), after an insulating silicon oxide film 300 is deposited on the entire surface, openings for contacts such as a source and a drain are formed according to a normal manufacturing method.
Further, a source aluminum metal electrode 310A, a drain aluminum metal electrode 310B, and the like are formed.

A MOS transistor manufactured by such a method has a channel between an n-type semiconductor region 200B (second semiconductor region) serving as a drain and an n-type semiconductor region 220A (third semiconductor region) serving as a source. The end of the drain (the n-type semiconductor region 200B) sufficiently overlaps the polysilicon film pattern 120A for the gate electrode. Generation of hot carriers in the part is suppressed, and excellent reliability is obtained. In the fourth embodiment, the n-type semiconductor region 200B serving as a substantial drain is left at the end of the drain.
N-type semiconductor region 20 serving as a source as in the third to third embodiments.
Since the 0E and n-type semiconductor regions 200G (first semiconductor regions) were not formed, a good MOS transistor having a small source resistance and therefore a power supply driving capability can be formed. The silicon oxide film pattern 160A is not necessarily required, but it is preferable to form the silicon oxide film pattern 160A because phosphorus ions may penetrate the tungsten silicide film pattern 152A due to a so-called channeling phenomenon.

In the embodiment of the present invention, a method of manufacturing an N-channel MOS transistor has been described. However, the present invention can be applied to a p-channel MOS by exchanging p and n impurities, and further to a C-MOS or the like.

〔The invention's effect〕

According to the method for manufacturing a field-effect semiconductor device of the present invention, the second semiconductor region of the second conductivity type serving as the drain is formed by oblique ion implantation, so that the gate and the drain are likely to overlap. Therefore, the thickness of the second insulating film (sidewall) left to control the amount of overlap can be reduced. As a result, the gate length of the gate electrode (the first conductive film having a wiring shape) can be reduced, and the degree of integration of the field-effect semiconductor device can be improved.

According to the method of manufacturing a field-effect semiconductor device described in claims (2) and (3), the second semiconductor region of the second conductivity type serving as the drain is formed by oblique ion implantation, and the second semiconductor region serving as the source is formed. Since the two-conductivity-type first semiconductor region is formed by a nearly vertical ion implantation method, the second semiconductor region serving as a drain is formed.
The conductive second semiconductor region can sufficiently overlap the gate electrode, and the first semiconductor region serving as a source can be formed with a small size. as a result,
Since a gate electrode with a small gate length can be formed, the degree of integration of a field-effect transistor can be improved, and a favorable field-effect semiconductor device with a small source resistance can be manufactured.

According to the method of manufacturing a field-effect semiconductor device according to claims (3) and (4), by arbitrarily selecting a combination of the first conductive film and the second conductive film, an anisotropic material having a poor etching selectivity can be obtained. Even in the dry etching, the upper layer of the second conductive film can be easily etched, so that a gate electrode having a good coverage shape and a small wiring electric resistance without a narrow pattern can be formed.

According to the method of manufacturing a field-effect semiconductor device according to claim (5), by arbitrarily selecting a combination of the first conductive film and the second conductive film, the upper conductive film can be made of poly-silicon. A field-effect semiconductor in which gate wiring resistance is sufficiently reduced by using a metal film such as tungsten or molybdenum or a metal compound such as tungsten silicide or molybdenum silicide in addition to a non-single-crystal semiconductor film such as silicon or amorphous silicon. The device can be manufactured.

[Brief description of the drawings]

1 (a), (b), (c), (d), (e),
FIGS. 2 (f) and 2 (g) are process cross-sectional views for explaining a method of manufacturing a main part of the N-channel MOS transistor according to the first embodiment of the present invention, and FIGS. 2 (a), 2 (b) and 2 (c). ,
(D), (e), (f), and (g) are process cross-sectional views for explaining a method of manufacturing a main part of the N-channel MOS transistor according to the second embodiment of the present invention, and FIG. ,
(B), (c), (d), (e), (f), and (g) are process cross-sections for explaining a method of manufacturing a main part of the N-channel MOS transistor according to the third embodiment of the present invention. Figure, 4th
FIGS. 7A, 7B, 7C, 7D, 7E, and 7F are views for explaining a method of manufacturing a main part of an N-channel MOS transistor according to a fourth embodiment of the present invention. 5 (a), 5 (b), 5 (c) and 5 (d) are cross-sectional views for explaining steps in a method for manufacturing a main part of a conventional MOS transistor. 100 semiconductor layer, 112 gate oxide film (first insulating film), 120 polysilicon film (first conductive film), 150
... Polysilicon film (second conductive film), 200E, 200G ... n
... N-type semiconductor region (second semiconductor region), 200A... N-type semiconductor region (second semiconductor region), 200B... N-type semiconductor region (first semiconductor region) Semiconductor region (second semiconductor region), 210A, 210B ... silicon oxide film (second insulating film), 300 ... silicon oxide film, A ...
Planned gate electrode formation

Claims (5)

(57) [Claims] A step of forming a first insulating film for a gate on a semiconductor layer of a first conductivity type; and forming a first conductive film serving as a gate electrode on the first insulating film for a gate. Forming, forming a second conductive film on the first conductive film, etching the second conductive film into a wiring shape, and masking the wiring-shaped second conductive film as a mask The second conductive type impurity is transmitted through the first conductive film by the oblique ion implantation method used as the gate electrode, so that the gate electrode forming portions on the source side and the drain side in the first conductive type semiconductor layer are formed. Implanting directly below to form a first semiconductor region of the second conductivity type serving as a source and a second semiconductor region of the second conductivity type serving as a drain; Leaving a second insulating film on a side surface, and leaving the second insulating film Forming the first conductive film in a wiring shape using the wiring-shaped second conductive film as a mask; and forming the remaining second insulating film and the wiring-shaped second conductive film in the wiring shape. An impurity of the second conductivity type is implanted into the source and drain sides of the semiconductor layer of the first conductivity type by an ion implantation method used as a mask, so that a third semiconductor of the second conductivity type which becomes a part of the source is formed. Forming a region and a second conductive type fourth semiconductor region to be a part of the drain. 2. A step of forming a first insulating film for a gate on a semiconductor layer of a first conductivity type, and a first conductive film serving as a gate electrode on the first insulating film for a gate. Forming, forming a second conductive film on the first conductive film, etching the second conductive film into a wiring shape, and forming the wiring-shaped second conductive film A second conductivity type impurity is transmitted through the first conductive film by a nearly vertical ion implantation method using a mask as a mask, and a source-side gate electrode formation portion in the first conductivity type semiconductor layer is formed. A first semiconductor region of the second conductivity type serving as a source by implanting the second conductive film as a source, and oblique ion implantation using the second conductive film having the wiring shape as a mask.
An impurity of a conductivity type is transmitted through the first conductive film and is implanted into the semiconductor layer of the first conductivity type immediately below a portion where a gate electrode is to be formed on a drain side, and a second conductivity type of a drain is formed. Forming a second semiconductor region; leaving a second insulating film on a side surface of the wiring-shaped second conductive film;
Forming the first conductive film into a wiring shape by using the conductive film as a mask, and ion implantation using the remaining second insulating film and the second conductive film in the wiring shape as a mask A second conductivity type impurity is implanted into the source side and the drain side in the first conductivity type semiconductor layer by a method, and the second conductivity type third semiconductor region, which is a part of the source, and one of the drains. Forming a fourth semiconductor region of the second conductivity type, which is a part of the semiconductor device. 3. A step of forming a first insulating film for a gate on a semiconductor layer of a first conductivity type, and a first conductive film serving as a gate electrode on the first insulating film for a gate. Forming, forming a second conductive film on the first conductive film, etching the second conductive film into a wiring shape, and forming the wiring-shaped second conductive film A second conductive type impurity is transmitted through the first conductive film by an oblique ion implantation method using a mask as a mask, and a portion of the semiconductor layer of the first conductive type immediately below a portion where a gate electrode is to be formed on the drain side is formed. Forming a second semiconductor region of a second conductivity type to be a drain, leaving a second conductive film on a side surface of the second conductive film having the wiring shape, The remaining second insulating film and the second conductive film having the wiring shape are used as masks. A step of forming the first conductive film into a wiring shape and an ion implantation method using the remaining second insulating film and the wiring-shaped second conductive film as masks to form a second conductive impurity. Is implanted into the source and drain sides of the semiconductor layer of the first conductivity type, and the third semiconductor region of the second conductivity type as the source and the fourth semiconductor of the second conductivity type as a part of the drain Forming a region and a step of forming a region. 4. A method for manufacturing a field-effect semiconductor device according to claim 1, wherein a non-single-crystal semiconductor film is used as the first conductive film. 5. The method according to claim 1, wherein a metal or a metal compound is used as the second conductive film.
(3) The method for manufacturing a field-effect semiconductor device according to (4).