JP2703246B2 - Compound semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to the improvement of compound semiconductor devices, and more particularly to GaAs.
The present invention relates to a compound semiconductor device including a field-effect transistor and having a structure for suppressing a short channel effect.

(Prior Art) In recent years, research on LSI using GaAs has been actively conducted, and operation of 16 kbit SRAM has been confirmed.
Metal-Semicon-ductor-FET (MESFET) constituting LSI
In order to reduce the series resistance due to the surface depletion layer, a self-aligned structure in which n-type high-concentration layers (n ⁺ layers) of source and drain are formed in a self-alignment manner with the gate is mainly used.

To improve the performance of LSI FETs, it is important to reduce the capacitance between the source, drain and gate by shortening the gate length. However, when the gate length is shortened, the short channel effect that the gate threshold voltage fluctuates and the current cutoff characteristic deteriorates cannot be ignored.
This short channel effect is caused by the self-aligned FE
This was particularly noticeable at T, which hindered gate length reduction.

One of the causes of the short-channel effect is the occurrence of a substrate leak current flowing between the respective n ⁺ layers via the semi-insulating substrate between the source and the drain arranged close to each other. A structure has been proposed in which the substrate leakage current is reduced to suppress the short channel effect (IEICE ED84).
-85). In the proposed structure, as shown in FIG. 2, the n-type high concentration layers 3 and 4 of the source 1 and the drain 2
A p-type layer is buried between the semi-insulating substrate 5 and a well 6 is formed. Note that reference numeral 7 denotes a gate electrode.

In the above structure, the p-type well 6 functions as an electrical barrier, thereby reducing substrate leakage current. Therefore, it is said that the speed of the LSI can be increased by miniaturizing the gate length while suppressing the short channel effect.

The effect of suppressing the short-channel effect increases as the height of the electric barrier formed by the p-type well 6 increases (that is, as the concentration of the well 6 increases). However, if the concentration of the p-type is too high, the parasitic capacitance generated at the pn junction increases, which hinders speeding up of the LSI. Therefore, in this example, the concentration of the p-type well 6 is set to a concentration at which the well 6 is completely depleted by the built-in voltage between the n-type active layer and the well 6, thereby suppressing an increase in parasitic capacitance. ing.

(Problems to be Solved by the Invention) However, this structure has the following problems.

(A) The suppression of the short channel effect is larger as the concentration of the p well 6 is higher, but as described above, the concentration of the p well 6 is n
It is suppressed to such an extent that the active layer is completely depleted.
Therefore, the suppression of the short channel effect is not sufficient.

(B) In order to completely deplete the p-type well 6, a dopant (eg, Si) for forming an n-type layer and p-type well 6 are used.
A dopant for forming the mold well 6 (for example, B
e) The activation process must be completely controlled to ensure sufficient reproducibility and uniformity. However,
Such control is extremely difficult, and in reality, a part of the p-type well 6 that is completely depleted or a part that is not completely depleted is mixed in the same substrate. Therefore, a parasitic capacitance is generated in a portion where the depletion is insufficient, so that the switching speed is reduced and the characteristics of the LSI are reduced.

(C) When the FET performs a switching operation, charges are also accumulated in a portion having a parasitic capacitance. However, since the p-type well 6 is in an electrically floating state, the accumulated charges (especially positive charges) do not easily escape to the outside of the FET, and as a result, malfunction of the LSI such as rewriting of the memory contents occurs. It will be.

The present invention has been made in view of such circumstances, and aims at the short channel effect and pn.
An object of the present invention is to provide a compound semiconductor device having a structure capable of effectively suppressing an increase in parasitic capacitance at a junction and easily controlling a process in an activation step.

(Means for Solving the Problems) A compound semiconductor device of the present invention is formed so as to surround a first conductivity type layer constituting a field effect transistor and at least a part of the first conductivity type layer. And the second layer which is not completely depleted by the layer of the first conductivity type.
A well of the second conductivity type, a well extension part in which a part of the well of the second conductivity type is projected outside the layer of the first conductivity type, and a potential applied to the well of the second conductivity type from outside. And an electrode electrically connected to the well extension to achieve the above objectives.

Further, a ground potential or another appropriate potential may be applied to the second conductivity type well by the electrode.

Further, the concentration of the second conductivity type of the well extension may be relatively higher than that of the other wells of the second conductivity type.

(Function) In the present invention, an electric barrier is formed between a substrate and an active layer by a well of the second conductivity type to suppress a substrate leak current and to provide an electrode electrically connected to the well. As a result, it is possible to apply an appropriate potential to the well from the outside, and to discharge the charge accumulated in the pn junction outside the FET. Also, by not completely depleting the well of the second conductivity type, the activation process can be easily controlled and the concentration of the second conductivity type can be sufficiently increased to effectively suppress the short channel effect. Things. In addition, an electrode is provided on a well extension part in which a part of the well of the second conductivity type is projected outside the layer of the first conductivity type, and a potential is applied to the well of the second conductivity type therefrom. Therefore, the well area is reduced, the parasitic capacitance is reduced, and the speed of the LSI can be increased.

(Example) Hereinafter, the present invention will be described with reference to examples.

In the following, the manufacturing process of one embodiment of the present invention will be described and the configuration thereof will be described. However, for the sake of easy understanding, the manufacturing process in the prior art shown in FIG. To

FIG. 1 (a) shows a state where the n-type implantation for forming the n-type active layer and the p-type implantation for forming the p-type well are completed in the manufacture of this embodiment. It is a top view which shows typically. Here, the n-type active layer 11 is indicated by a broken line, and the p-type well 12 is indicated by a chain line.

For comparison, in manufacturing the conventional example shown in FIG.
FIG. 3A schematically shows a state where the n-type implantation for forming the active layer 11 and the p-type implantation for forming the well 12 are completed.

1 (a) and 3 (a), the p-well 12 is drawn so as to surround the n-type active layer 11, but FIG.
This is for the convenience of illustration, and the two are actually formed in the same place because the same implantation mask is used.
However, in the case of this embodiment, the extension well portion 12 described later is used.
For b this is not the case.

As is clear from the comparison of FIG. 1A with FIG. 3A, in the present embodiment, when implanting for forming the p-type well 12, a part of the implant is used for the n-type implanted portion. The injection is performed to extend to the outside, and the extended well portion 12
It can be seen that b is formed. This is because a p-type well is formed up to the outside of the region where the FET is formed.

Next, through a generally performed FET manufacturing process including various self-alignment processes, FIG.
As shown in FIG. 2B, the present embodiment and the prior art
FET is formed. In the figure, 13 indicates a source electrode 14, a drain electrode, and 15 indicates a gate electrode. Fig. 1 (b)
As shown in FIG. 5, in this embodiment, an electrode 16 is formed on an extended portion 12b of the p-type well 12. This electrode 16
Thus, an appropriate potential can be applied to the p-type well 12.

The electrode 16 is most preferably made of, for example, an Au-Zn alloy in order to obtain ohmic contact.
Ohmic contact may be formed as a result by devising heat treatment conditions using a normal gate metal such as an i-type metal. It should be pointed out that in the latter case, there is no increase in the number of steps from the prior art.

As described above, in this embodiment, the electrode 16 is electrically connected to the p-type well portion 12b extending to the outside of the region where the FET is formed. Therefore, when the electrode 16 is connected to, for example, the source electrode 13 and the p-type well 12 is grounded, the electric charge accumulated in the pn junction is discharged out of the FET, and a switching malfunction can be prevented.

Further, since the potentials at both ends of the pn junction are equal, the increase in capacitance is extremely small, and therefore, the high-speed operation of the element is not hindered. Also in this case, an electrical barrier is formed at the pn junction by a built-in voltage without reducing the height.

Further, since the increase in the capacity is small, the concentration of the p-type well 12 can be increased as compared with the case of the prior art, so that the short channel effect can be sufficiently suppressed.

If an appropriate positive potential is applied to the electrode 16, the suppression of the short-channel effect can be further increased by increasing the electric barrier. However, in this case, the increase in the capacitance of the pn junction becomes large. Therefore, the concentration of the p-type well 12 and the value of the positive potential should be optimized. It is necessary to comprehensively determine while taking into account the element performance such as.

In general, the amount of p-type implantation required for forming the p-type well 12 is not so large, and is 10 ¹¹ cm ^-2 or less in the conventional example.
It is about 10 ¹² cm ^-2 , but it is almost the same in this embodiment. At this time, the resistance of the p-layer portion of the pn junction increases, and the junction is easily damaged by an external surge. In this case, however, the n-type active layer in the p-type well 12 is removed.
The concentration of the well portion 12b on which the electrode 16 is formed may be higher than that of the well portion 12a surrounding the eleventh portion. For example, as shown in FIG. 1C, if the p-type high-concentration layer 17 is formed by adding high-concentration p-type implantation to the region surrounded by the two-dot chain line in the drawing, the electric resistance of the well portion 12b is reduced. Thus, the surge resistance can be improved.

Note that the concentration of the p-type well 12 is not limited by the depletion condition by the n-type driving layer, and thus the concentration of the p-type well 12 can be freely set. Therefore, the short channel suppression effect can be increased by increasing the concentration of the p-type well 12.

Further, since the p-type well 12 does not completely deplete the depletion, the process control in the above-described activation step does not need to be performed completely as in the prior art, so that the process margin becomes extremely large.

In the above embodiment, the description has been given of the case where the n-type active layer is formed as the first conductivity type layer and the p-type well is formed as the second conductivity type well. It goes without saying that the same effect can be obtained even if the mold is reversed.

(Effects of the Invention) As described above, according to the present invention, the well of the conductivity type shown in FIG. 2 is not completely depleted, so that the process margin in the activation step is greatly increased and the second conductivity is reduced. Since the concentration of the mold can be increased without being restricted by the depletion conditions, the short channel effect can be sufficiently suppressed. Further, since the electric charge accumulated in the pn junction can be discharged to the outside of the FET by the electrode electrically connected to the well of the second conductivity type, malfunction of the device can be prevented.

In particular, an electrode is provided on a well extension part in which a part of the well of the second conductivity type is projected outside the layer of the first conductivity type, and a potential is applied to the well of the second conductivity type therefrom. Therefore, the well area can be reduced, the parasitic capacitance can be reduced, and the LSI
Can be speeded up. Also, it is possible to reduce the malfunction of the LSI.

[Brief description of the drawings]

1 (a) and 1 (b) are schematic plan views for explaining a manufacturing process of an embodiment of the present invention, and FIG. 1 (c) illustrates a modification of the embodiment of the present invention. FIG. 2 is a cross-sectional view of a conventional compound semiconductor device, and FIGS. 3 (a) and 3 (b) are schematic plan views for explaining the manufacturing process of the conventional example of FIG. is there. 11 ... n-type active layer, 12 ... p-type well, 16 ... electrode, 1
7 ... p-type high concentration layer.

Claims (1)

(57) [Claims] A first conductivity type layer constituting a field effect transistor; and a first conductivity type layer formed so as to surround at least a part of the first conductivity type layer. A well of the second conductivity type that is not completely depleted; a well extension part in which a part of the well of the second conductivity type projects outside the layer of the first conductivity type; And an electrode electrically connected to the well extension to apply a potential to the well of the second conductivity type from the outside.