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JP2709484B2 - Method for manufacturing semiconductor device - Google Patents
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JP2709484B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2709484B2
JP2709484B2 JP63233316A JP23331688A JP2709484B2 JP 2709484 B2 JP2709484 B2 JP 2709484B2 JP 63233316 A JP63233316 A JP 63233316A JP 23331688 A JP23331688 A JP 23331688A JP 2709484 B2 JP2709484 B2 JP 2709484B2
Authority
JP
Japan
Prior art keywords
lead
lead electrode
forming
electrode
forming member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63233316A
Other languages
Japanese (ja)
Other versions
JPH0281464A (en
Inventor
稔 平井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP63233316A priority Critical patent/JP2709484B2/en
Publication of JPH0281464A publication Critical patent/JPH0281464A/en
Application granted granted Critical
Publication of JP2709484B2 publication Critical patent/JP2709484B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/701Tape-automated bond [TAB] connectors

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明はリード電極付きIC等の半導体装置の製造方法
に関する。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device such as an IC with a lead electrode.

従来の技術 従来からIC等の半導体装置の実装方式としてペデスタ
ル方式やテープキャリヤ方式が知られている。ペデスタ
ル方式では、ICを実装しようとする回路基板に形成した
配線パターン上に、ICの電極数と同数のペデスタルを形
成しなければならないので、一枚の回路基板に多数のIC
を実装する場合には、IC一個分のペデスタルの歩留り率
が高率であっても、回路基板全体では各ICの歩留り率が
積算されることになって、全体としての歩留り率は大幅
に低下するという問題点があった。また、実装されたIC
の中に不良品があった場合でも、そのICの電極とペデス
タルとが直接的に接続されているので取り外すことがで
きず、ICを交換することができなかった。
2. Description of the Related Art Conventionally, a pedestal system and a tape carrier system have been known as a mounting system of a semiconductor device such as an IC. In the pedestal system, the same number of pedestals as the number of IC electrodes must be formed on the wiring pattern formed on the circuit board on which the IC is to be mounted.
When mounting ICs, even if the yield rate of one pedestal for one IC is high, the yield rate of each IC will be integrated on the entire circuit board, and the overall yield rate will drop significantly There was a problem of doing. Also, the mounted IC
Even if there was a defective product inside, the IC electrode could not be removed because the electrode of the IC was directly connected to the pedestal, and the IC could not be replaced.

一方、テープキャリヤ方式では、ICの各電極に対応す
るリード電極がベースフィルム上に形成されている。と
ころが、このベースフィルムが温度条件などによって収
縮することによりリード電極間のピッチが変化するの
で、いわゆる寸法安定性が悪い。また、ベースフィルム
自体が高価であることから、製造コストが高くなるとい
う問題点もあった。
On the other hand, in the tape carrier method, lead electrodes corresponding to each electrode of the IC are formed on a base film. However, since the pitch between the lead electrodes changes when the base film shrinks due to temperature conditions or the like, so-called dimensional stability is poor. Further, since the base film itself is expensive, there is also a problem that the manufacturing cost is increased.

このような問題点を克服するために、例えば、特開昭
63-34935号公報に示すようなICの実装方法が提案されて
いる。この方法の特徴とするところは、リード形成用基
板上にリード電極を剥離可能に形成するとともに、この
リード電極上の所定位置にバンプを形成し、かつこのバ
ンプを介してICの電極とリード電極とを接続してリード
電極付きICとしたのち、リード電極付きICをリード形成
用基板から分離し、このリード電極付きICを回路基板に
おける所要位置に配置して各リード電極を対応する配線
パターンに接続することにある。
In order to overcome such problems, for example,
An IC mounting method as disclosed in JP-A-63-34935 has been proposed. The feature of this method is that a lead electrode is formed on a lead forming substrate so as to be peelable, a bump is formed at a predetermined position on the lead electrode, and an IC electrode and a lead electrode are formed through the bump. After connecting the IC with the lead electrode, the IC with the lead electrode is separated from the lead forming substrate, and the IC with the lead electrode is arranged at a required position on the circuit board, and each lead electrode is formed into a corresponding wiring pattern. To connect.

発明が解決しようとする課題 しかしながら、特開昭63-34935号公報に記載のICの実
装方法においても、以下に述べるような問題点がある。
第2図に示した半導体装置は、IC10aの電極11a上にバン
プ12aおよびリード電極13aを形成したリード電極付きIC
20aを、ガラス製の回路基板30aの配線パターン31a上に
半田32aによって取り付けたものである。このような半
導体装置が電子機器等に組み込まれて使用されるとき、
この半導体装置の周囲温度の変化が生じると、IC10a、
リード電極13aの材料である銅および回路基板30aの材料
であるガラスのそれぞれの線膨張率の違いによってリー
ド電極13aに応力が発生し、バンプ12aや半田32aの部分
に損傷が発生する。この損傷の発生をなくするために
は、IC10a、リード電極13aの銅および回路基板30aのガ
ラスの線膨張率が、それぞれ3.5×10-6、17×10-6およ
び8.5×10-6であることを考慮すると、IC10aのチップサ
イズが10mmであるとき、リード電極13aの全長は、半田
付け領域dの長さを0.5mmとすると、この半田付け領域
以外の領域lの長さとして2.94mmを必要とし、リード電
極13aの長さは3.44mmとなる。
Problems to be Solved by the Invention However, the IC mounting method described in Japanese Patent Application Laid-Open No. 63-34935 also has the following problems.
The semiconductor device shown in FIG. 2 is an IC with a lead electrode in which a bump 12a and a lead electrode 13a are formed on an electrode 11a of an IC 10a.
20a is mounted on a wiring pattern 31a of a glass circuit board 30a by solder 32a. When such a semiconductor device is used by being incorporated into an electronic device or the like,
When the ambient temperature of the semiconductor device changes, IC 10a,
Stress is generated in the lead electrode 13a due to a difference in linear expansion coefficient between copper as the material of the lead electrode 13a and glass as the material of the circuit board 30a, and damage is caused to the bump 12a and the solder 32a. In order to eliminate the occurrence of this damage, the linear expansion coefficients of the IC 10a, the copper of the lead electrode 13a and the glass of the circuit board 30a are 3.5 × 10 −6 , 17 × 10 −6 and 8.5 × 10 −6 , respectively. Considering that, when the chip size of the IC 10a is 10 mm, the total length of the lead electrode 13a is 2.94 mm as the length of the region l other than the soldering region, assuming that the length of the soldering region d is 0.5 mm. It is necessary, and the length of the lead electrode 13a is 3.44 mm.

このように長いリード電極を有するリード電極付きIC
を基板等に実装した場合には、実装密度が小さくなる。
また、このようなリード電極付きICをリード形成用基板
から分離する場合、リード電極電極が、リード形成用基
板表面に形成されている金属との親和性が低いITO(イ
ンジウム・錫酸化物)蒸着膜等から剥離するときに、リ
ード電極13aに曲がりが発生することが多く、リード電
極付きICの歩留りが低くなる。
IC with lead electrode having such long lead electrode
Is mounted on a substrate or the like, the mounting density is reduced.
Also, when such an IC with lead electrodes is separated from the lead forming substrate, the lead electrode electrodes are deposited by ITO (indium tin oxide), which has low affinity with the metal formed on the surface of the lead forming substrate. When the lead electrode 13a is peeled off from a film or the like, bending often occurs in the lead electrode 13a, and the yield of the IC with the lead electrode is lowered.

本発明は上記事情に鑑みて創案されたものであって、
リード電極を短くしてリード形成用基板からリード電極
付きICを剥離するときにリード電極に曲がりが生じるこ
とがなく、またリード電極が短くても周囲温度の変化に
よる応力によってリード電極のバンプや半田付けの部分
に損傷を生じることがなく、そして、リード電極付きIC
の基板への実装密度も大きくすることが出来るリード電
極付きIC等の半導体装置の製造方法を提供することを目
的としている。
The present invention has been made in view of the above circumstances,
When the lead electrode is shortened and the IC with the lead electrode is peeled off from the lead forming substrate, the lead electrode does not bend, and even if the lead electrode is short, bumps or solder on the lead electrode due to stress due to changes in ambient temperature No damage to the attached part, and IC with lead electrode
It is an object of the present invention to provide a method of manufacturing a semiconductor device such as an IC with a lead electrode, which can increase the mounting density of the semiconductor device on a substrate.

課題を解決するための手段 以上の課題を解決するために本発明の半導体装置の製
造方法は、リード形成用基板上に剥離可能に形成された
リード電極とこのリード電極に接続されたICとを有する
リード電極付きICを前記リード形成用基板から分離後、
段差を有するフォーミングステージ上に載置し、次いで
吸着手段と加熱手段とを有するフォーミング部材を下降
させ、前記フォーミング部材の下端に設けられた加熱押
圧体を前記段差に押圧することにより前記ICのリード電
極を屈曲形成した後、前記フォーミング部材により前記
ICを吸着保持させ、この状態で前記フォーミング部材を
移動させて前記ICを回路基板上の所定位置に載置し、そ
の後、前記フォーミング部材の加熱押圧体の熱により前
記リード電極と前記回路基板上の配線パターンとの間を
ハンダ付けするようにした。
Means for Solving the Problems In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a method of forming a lead electrode releasably formed on a lead forming substrate and an IC connected to the lead electrode. After separating the IC with lead electrodes from the lead forming substrate,
The IC lead is placed on a forming stage having a step, and then a forming member having a suction means and a heating means is lowered, and a heating pressing body provided at a lower end of the forming member is pressed against the step. After bending the electrode, the forming member
The IC is sucked and held, and in this state, the forming member is moved to place the IC at a predetermined position on the circuit board, and then the lead electrode and the circuit board are heated by the heat of the heating member of the forming member. And the wiring pattern is soldered.

作用 リード形成用基板からリード電極付きICが分離されて
フォーミングステージ上に載置され、その後、吸着手段
と加熱手段とを有するフォーミング部材を下降させ、フ
ォーミング部材の下端に設けられた加熱押圧体を前記段
差を押圧することによりICのリード電極を屈曲形成し、
吸着手段でリード電極付きICを吸着し、フォーミング部
材を移動してリード電極付きICを回路基板上に配置し、
加熱押圧体の熱によってリード電極と基板上の配線パタ
ーン間に設けた半田が溶かされてリード電極と配線パタ
ーンとが接続される。
The IC with the lead electrode is separated from the lead forming substrate and placed on the forming stage. Thereafter, the forming member having the suction unit and the heating unit is lowered, and the heating press body provided at the lower end of the forming member is moved. By pressing the step, the lead electrode of the IC is bent and formed,
The IC with the lead electrode is sucked by the suction means, the forming member is moved, and the IC with the lead electrode is arranged on the circuit board.
The solder provided between the lead electrode and the wiring pattern on the substrate is melted by the heat of the heating press body, and the lead electrode and the wiring pattern are connected.

実施例 以下、本発明の一実施例を図面を参照して説明する。
第1図は本発明の一実施例に係る各工程を示す説明図で
あって、第1図(a)はリード形成用基板上にリード電
極付きICを設けた状態を、第1図(b)はリード電極付
きICをフォーミングステージ上に載置した状態を、第1
図(c)はフォーミング部材とフォーミングステージと
によってリード電極付きICのリード電極を折り曲げた状
態を、第1図(d)はフォーミング部材によってリード
電極付きICを回路基板上に取り付けた状態をそれぞれ示
す。
Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is an explanatory view showing each step according to one embodiment of the present invention. FIG. 1 (a) shows a state in which an IC with lead electrodes is provided on a lead forming substrate, and FIG. ) Shows the state where the IC with lead electrodes is placed on the forming stage.
FIG. 1C shows a state in which the lead electrode of the IC with lead electrodes is bent by the forming member and the forming stage, and FIG. 1D shows a state in which the IC with lead electrodes is mounted on the circuit board by the forming member. .

第1図(a)において、40はリード形成用基板であっ
て、ガラス基板41の表面全面にわたって、金属との親和
性が低いITO(インジウム・錫酸化物)を蒸着してITO蒸
着膜42を形成したものである。このようなリード形成用
基板40の表面全面に、厚みが30μm程度で銅からなるメ
ッキ層を形成し、このメッキ層をフォトリソグアフィや
フォトエッチングによってエッチングして、長さが例え
ば1〜2mmのリード電極13を形成する。このようにリー
ド電極13が形成されたリード形成用基板40の表面全面に
レジスト膜を形成し、リード電極13上でIC10の電極11が
接続される所定位置のレジスト膜を除去し、その箇所に
金もしくは銅からなる突起部、いわゆるバンプ12をメッ
キにより形成する。このバンプ12の高さは30μm程度と
する。次に前記レジスト膜を全面的に除去したのち、IC
10の電極13とバンプ12とが互いに当接するようにしてリ
ード電極13上にIC10が載置する。更にこれらの両者を熱
圧着することにより、IC10の電極11とリード電極13とを
バンプ12を介して接続する。このことによりIC10はリー
ド電極付きIC20となる。
In FIG. 1A, reference numeral 40 denotes a lead forming substrate, which is formed by depositing ITO (indium tin oxide) having low affinity for metal over the entire surface of a glass substrate 41 to form an ITO deposited film. It is formed. A plating layer made of copper with a thickness of about 30 μm is formed on the entire surface of the lead forming substrate 40, and the plating layer is etched by photolithography or photoetching to have a length of, for example, 1 to 2 mm. The lead electrode 13 is formed. A resist film is formed on the entire surface of the lead forming substrate 40 on which the lead electrodes 13 are formed as described above, and the resist film at a predetermined position where the electrode 11 of the IC 10 is connected on the lead electrodes 13 is removed. A protrusion made of gold or copper, a so-called bump 12, is formed by plating. The height of the bump 12 is about 30 μm. Next, after completely removing the resist film, the IC
The IC 10 is mounted on the lead electrode 13 such that the ten electrodes 13 and the bumps 12 are in contact with each other. Further, the electrodes 11 and the lead electrodes 13 of the IC 10 are connected via the bumps 12 by thermocompression bonding of both. Thus, the IC 10 becomes the IC 20 with the lead electrode.

そして、リード電極付きIC20を真空吸着等で引っ張る
ことにより、リード形成用基板40を構成するITO蒸着膜4
2からリード電極13が剥離し、リード電極付きIC20がリ
ード形成用基板40から分離する。
Then, by pulling the IC 20 with lead electrodes by vacuum suction or the like, the ITO deposited film 4 constituting the lead forming substrate 40 is formed.
The lead electrode 13 is peeled off from 2, and the IC 20 with the lead electrode is separated from the lead forming substrate 40.

このようなリード電極付きIC20を、図示しない移送手
段によって、第1図(b)に示すようにフォーミングス
テージ51の上に載置する。フォーミングステージ51の上
面には一対の段差511が形成されている。フォーミング
ステージ51の上方には、フォーミング部材52が設けられ
ている。フォーミング部材52は吸着手段として吸着コレ
ット521とこの吸着コレット521の両側に配置した一対の
加熱押圧体522とを具備している。加熱押圧体522の下端
にはモリブデン、ニクロム或いはインコネル等からなる
サーモードツール(加熱手段に相当する)が設けられて
いる。このサーモードツールに200〜300Aの電流を流す
と、発生するジュール熱でサーモードツールはほぼ瞬間
的に400〜500℃の温度になる。なお、第1図(b)〜
(d)では吸着コレット521と加熱押圧体522の下端部分
のみを示している。
Such an IC 20 with lead electrodes is mounted on a forming stage 51 by a transfer means (not shown) as shown in FIG. 1 (b). A pair of steps 511 is formed on the upper surface of the forming stage 51. Above the forming stage 51, a forming member 52 is provided. The forming member 52 includes a suction collet 521 as a suction means and a pair of heating and pressing members 522 disposed on both sides of the suction collet 521. A thermode tool (corresponding to a heating means) made of molybdenum, nichrome, inconel, or the like is provided at the lower end of the heating press body 522. When a current of 200 to 300 A is applied to this thermode tool, the temperature of the thermode tool becomes almost instantaneously 400 to 500 ° C. due to the generated Joule heat. In addition, FIG.
(D) shows only the lower end portions of the suction collet 521 and the heating press body 522.

次に、第1図(c)に示すように、フォーミング部材
52を降下させて吸着コレット521をIC10に当接させると
ともに、常温状態に保たれている加熱押圧体522の下端
をフォーミングステージ51の段差511に圧接させる。す
ると、リード電極13は加熱押圧体522の下端部分によっ
て段差511に圧接されて、2個所でほぼ90°屈曲してい
るように形成される。
Next, as shown in FIG.
The suction collet 521 is brought into contact with the IC 10 by descending 52, and the lower end of the heating press body 522 kept at a normal temperature is pressed against the step 511 of the forming stage 51. Then, the lead electrode 13 is pressed against the step 511 by the lower end portion of the heating / pressing body 522, and is formed so as to be bent substantially 90 ° at two places.

この状態で吸着コレット521でリード電極付きIC20を
吸着し、フォーミング部材52にリード電極付きIC20を保
持させる。次いで、この状態のフォーミング部材52を、
図示しない移動手段によって移動させることにより、リ
ード電極付きI20を回路基板30上に載置する。即ち、リ
ード電極付きIC20のリード電極13の先端部分の下面が、
回路基板30上に形成した配線パターン31上の所定個所に
設けた半田32に当接するように載置する。そして、加熱
押圧体522の前記サーモードツールが通電されて熱せら
れる。この熱はリード電極13を経て半田32に伝えられて
半田32が融け、リード電極13と配線パターン31との接続
が完了する。この後、吸着コレット521の吸引を中止
し、フォーミング部材52を引き上げる。このようにし
て、リード電極付きIC20を回路基板30上へ搭載する半導
体装置の製造が完了する。
In this state, the IC 20 with a lead electrode is sucked by the suction collet 521 and the forming member 52 holds the IC 20 with the lead electrode. Next, the forming member 52 in this state is
The I20 with the lead electrode is placed on the circuit board 30 by being moved by a moving means (not shown). That is, the lower surface of the tip portion of the lead electrode 13 of the IC 20 with a lead electrode is
It is placed so as to be in contact with the solder 32 provided at a predetermined position on the wiring pattern 31 formed on the circuit board 30. Then, the thermode tool of the heating press body 522 is energized and heated. This heat is transmitted to the solder 32 via the lead electrode 13 and the solder 32 is melted, and the connection between the lead electrode 13 and the wiring pattern 31 is completed. Thereafter, the suction of the suction collet 521 is stopped, and the forming member 52 is pulled up. Thus, the manufacture of the semiconductor device in which the IC 20 with the lead electrode is mounted on the circuit board 30 is completed.

発明の効果 従って、本発明の半導体装置の製造方法によれば、リ
ード電極を短くしてリード形成用基板からリード電極付
きICを剥離するときにリード電極に曲がりが生じること
がなく、またリード電極が短くても周囲温度の変化によ
る応力によってリード電極のバンプや半田付けの部分に
損傷を生じることがなく、そして、リード電極付きICの
基板への実装密度も大きくすることが出来るリード電極
付きIC等の半導体装置の製造方法を提供することができ
る利点がある。しかもフォーミング部材は単にICのリー
ド電極を屈曲形成し、当該ICを回路基板上の所定位置に
まで移動させる機能だけでなく、回路基板上に載置され
たICのリード電極と回路基板上の配線パターンとの間を
ハンダ付けする機能を有しており、リードフォーミン
グ、回路基板へのICの搭載及び半田付けを一連の動作で
行うことができることから、製造工程が単純となり、半
導体装置の低コスト化を図ることもできる。
Therefore, according to the method for manufacturing a semiconductor device of the present invention, when the lead electrode is shortened and the IC with the lead electrode is separated from the lead forming substrate, the lead electrode does not bend, and Even if the length is short, the bumps and soldered parts of the lead electrode will not be damaged by the stress due to the change of the ambient temperature, and the mounting density of the lead electrode IC on the substrate can be increased. There is an advantage that a method for manufacturing a semiconductor device such as that described above can be provided. In addition, the forming member not only has a function of simply bending the lead electrode of the IC and moving the IC to a predetermined position on the circuit board, but also has a function of wiring the lead electrode of the IC mounted on the circuit board and the wiring on the circuit board. It has a function of soldering between patterns and can perform lead forming, mounting of IC on circuit board and soldering in a series of operations, simplifying the manufacturing process and reducing the cost of semiconductor devices. Can also be planned.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の一実施例に係る各工程を示す説明図で
あって、第1図(a)はリード形成用基板上にリード電
極付きICを設けた状態を、第1図(b)はリード電極付
きICをフォーミングステージ上に載置した状態を、第1
図(c)はフォーミング部材とフォーミングステージと
によってリード電極付きICのリード電極を折り曲げた状
態を、第1図(d)はフォーミング部材によってリード
電極付きICを回路基板上に取り付けた状態をそれぞれ示
す。第2図はリード電極付きICを回路基板上に取り付け
た状態を示す説明図である。 13……リード電極、20……リード電極付きIC、30……回
路基板、31……配線パターン、32……半田、40……リー
ド形成用基板、51……フォーミングステージ、511……
段差、52……フォーミング部材、521……吸着コレッ
ト、522……加熱押圧体。
FIG. 1 is an explanatory view showing each step according to one embodiment of the present invention. FIG. 1 (a) shows a state in which an IC with lead electrodes is provided on a lead forming substrate, and FIG. ) Shows the state where the IC with lead electrodes is placed on the forming stage.
FIG. 1C shows a state in which the lead electrode of the IC with lead electrodes is bent by the forming member and the forming stage, and FIG. 1D shows a state in which the IC with lead electrodes is mounted on the circuit board by the forming member. . FIG. 2 is an explanatory view showing a state in which an IC with lead electrodes is mounted on a circuit board. 13 ... lead electrode, 20 ... IC with lead electrode, 30 ... circuit board, 31 ... wiring pattern, 32 ... solder, 40 ... lead forming board, 51 ... forming stage, 511 ...
Step, 52 Forming member, 521 Adsorbing collet, 522 Heating body.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】リード形成用基板上に剥離可能に形成され
たリード電極とこのリード電極に接続されたICとを有す
るリード電極付きICを前記リード形成用基板から分離
後、段差を有するフォーミングステージ上に載置し、次
いで吸着手段と加熱手段とを有するフォーミング部材を
下降させ、前記フォーミング部材の下端に設けられた加
熱押圧体を前記段差に押圧することにより前記ICのリー
ド電極を屈曲形成した後、前記フォーミング部材により
前記ICを吸着保持させ、この状態で前記フォーミング部
材を移動させて前記ICを回路基板上の所定位置に載置
し、その後、前記フォーミング部材の加熱押圧体の熱に
より前記リード電極と前記回路基板上の配線パターンと
の間をハンダ付けするようになっていることを特徴とす
る半導体装置の製造方法。
1. A forming stage having a step after separating an IC with a lead electrode having a lead electrode releasably formed on a lead forming substrate and an IC connected to the lead electrode from the lead forming substrate. The lead electrode of the IC was bent and formed by lowering the forming member having the suction means and the heating means, and pressing the heating pressing body provided at the lower end of the forming member against the step. Thereafter, the IC is sucked and held by the forming member, and in this state, the forming member is moved to place the IC at a predetermined position on the circuit board, and thereafter, the heat is applied by the heat pressing body of the forming member. A method for manufacturing a semiconductor device, comprising: soldering between a lead electrode and a wiring pattern on the circuit board.
JP63233316A 1988-09-17 1988-09-17 Method for manufacturing semiconductor device Expired - Lifetime JP2709484B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63233316A JP2709484B2 (en) 1988-09-17 1988-09-17 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63233316A JP2709484B2 (en) 1988-09-17 1988-09-17 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0281464A JPH0281464A (en) 1990-03-22
JP2709484B2 true JP2709484B2 (en) 1998-02-04

Family

ID=16953220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63233316A Expired - Lifetime JP2709484B2 (en) 1988-09-17 1988-09-17 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2709484B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5585281A (en) * 1995-02-03 1996-12-17 Motorola, Inc. Process and apparatus for forming and testing semiconductor package leads
US6405429B1 (en) * 1999-08-26 2002-06-18 Honeywell Inc. Microbeam assembly and associated method for integrated circuit interconnection to substrates

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6144431Y2 (en) * 1980-09-17 1986-12-15
JPS5832441A (en) * 1981-08-20 1983-02-25 Matsushita Electric Ind Co Ltd Apparatus for bending and shaping lead of semiconductor element
JPS6334935A (en) * 1986-07-29 1988-02-15 Rohm Co Ltd Method for mounting ic

Also Published As

Publication number Publication date
JPH0281464A (en) 1990-03-22

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