JP2709501B2 - Semiconductor element connection method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for connecting semiconductor devices.

(Prior Art) FIG. 3 shows a schematic structure of a conventional flip chip connection of a semiconductor element. In the figure, 1 is a semiconductor element, 2 is a wiring board, 3 is a solder bump, 4 is an electrode provided on each of the semiconductor element 1 and the wiring board 2, and AA 'indicates the center of the semiconductor element. .

In flip-chip connection, the electrical connection between the semiconductor element 1 and the electrode 4 of the wiring board 2 can be performed by batch connection in which the solder bumps 3 are heated and melted, so that workability is superior to the wire bonding method. Also, wire bonding method and TA
Unlike the B (Tape Automated Bonding) method, the arrangement of electrodes is not limited to the periphery of the semiconductor element, so that the number of connection terminals can be greatly increased.

However, in this connection structure, as shown in FIG. 4, when a temperature change occurs, a dimensional deviation B occurs due to a difference in the coefficient of thermal expansion between the semiconductor element 1 and the wiring board 2, and a shear distortion occurs in the solder bump 3. Connection reliability decreases.

Since the shear strain increases with an increase in the center distance between the solder bump 3 and the semiconductor element 1, an area where the solder bump 3 can be arranged is limited due to an allowable shear strain of the solder bump 3. Is difficult to apply to semiconductor devices.

As a means for reducing the shear strain of the solder bumps, a method using a wiring board material having a thermal expansion coefficient close to that of the semiconductor element can be considered, but there is a disadvantage that the wiring board material is limited.

On the other hand, a method has been proposed in which a multistage bump is formed by stacking solder bumps supported by a polyimide film to reduce shear distortion (Japanese Patent Application Laid-Open No. 62-293730).

However, since the solder bumps are stacked, there are disadvantages in that the number of necessary members increases and the cost increases due to an increase in the number of connection steps.

FIG. 5 shows a semiconductor element connection structure in which metal bumps are brought into contact with each other by pressure to obtain electrical connection. In FIG.
Metal bumps 13 are formed on the respective electrodes 4 of the semiconductor element 1 and the wiring board 2. Pressure is applied to the metal bumps 13 due to the shrinkage force of the shrinkable resin 5 at the time of curing, and the metal bumps 13 are brought into mechanical contact with each other to obtain electrical connection.

However, in this connection structure, there are portions where the height of the metal bumps 13 varies and electrical connection cannot be obtained.
In addition, since the thermal expansion coefficient of the shrinkable resin 5 is larger than that of the metal bumps, when the temperature changes, the pressure is reduced, and the contact of the metal bumps becomes unstable.

(Problems to be Solved by the Invention) In the present invention, a large shear strain generated between the semiconductor element and the wiring board described above, a variation in bump height, and a pressure fluctuation due to a difference in thermal expansion coefficient between the resin and the shrinkable resin. The present invention provides an inexpensive method for connecting a semiconductor element, which has high reliability in electrical connection and enables fine connection.

[Means for solving the problem]

The present invention is a method for electrically connecting a semiconductor element and a wiring board, wherein an insulating substrate having a through hole formed of a superelastic material is interposed between the semiconductor element and the wiring board. The gist is a method for connecting a semiconductor element.

In the present invention, in order to solve the above-described problem, a semiconductor element mounting structure in which a superelastic material is interposed, a hole is formed in the insulating substrate at the same interval as the connection pitch, a through-hole structure is formed with a superelastic metal, This is a method in which alignment is performed between an element and a wiring board, and connection is obtained by soldering or external pressure.

As the superelastic material, a metal having an elastic strain of 0.5% or more is desirable.

This superelastic material includes, for example, Ti-Ni, Fe-Pt, Fe-Pd, Mn-C
u, In-Ti, Ni-Al, Au-Cd, Ag-Cd, Au-Cu-Zn, Cu-Zn-Al, Cu-Zn-
Sn, Cu-Al-Ni, Cu-Sn or the like is used, and a through hole is formed by plating or spattering these metals.

The superelastic metal formed as described above may be subjected to heat treatment such as heating and cooling as needed in order to improve superelastic properties.

Table 1 shows the types and compositions of superelastic alloys that can be used in the present invention.

In the present invention, by using an insulating substrate with through holes formed of a superelastic material as a connection medium, high precision,
A low-cost and highly reliable semiconductor element connection can be obtained.

(Example) Next, the present invention will be described based on an example shown in the drawings.

FIG. 1 shows a cross-sectional structure of a connecting portion of the present invention.
Denotes an insulating substrate, for example, a polyimide film, 7 denotes a copper plating layer, 8 denotes a super elastic through hole, and 9 denotes a solder. In FIG. 1, a hole is formed in the insulating substrate 6 so as to be at the same position as the electrode 4 of the semiconductor element 1 and the electrode 4 of the wiring board 2, and a through-hole is formed with a superelastic metal 8.
And the wiring substrate 2 are soldered so that both electrodes are electrically connected.

With reference to FIGS. 2 (a) to 2 (e), a procedure for manufacturing an insulating substrate having a superelastic through hole will be described.

First, a hole is drilled in the insulating substrate 6 by a minute drill or etching (FIG. 2A). Next, electroless copper plating 7 is formed on the entire surface of the insulating substrate 6 (FIG. 2B). Next, a plating resist 10 is formed by photolithography on portions other than the conductor (FIG. 2C). After the electroless plating is exposed, Cu-34.7 wt% Zn-3.0 wt% Sn is formed by electroplating as a superelastic alloy 8. Next, a solder 9 is electroplated as a joining material (FIG. 2 (d)).

Next, after the plating resist 10 is removed and the solder 9 is etched, the electroless plated copper 7 other than the conductor is etched with an ammonium persulfate solution or the like (FIG. 6 (e)).

The insulating substrate with the superelastic through-hole completed in the above steps is aligned with the connection electrode 4 between the semiconductor element 1 and the wiring substrate 2 and heated in a reflow furnace, so that the two electrodes are soldered.

The thus obtained mounting structure sufficiently follows thermal distortion due to a difference in thermal expansion between the wiring board and the semiconductor element due to a temperature change because the superelastic metal having the through hole has 2% elastic distortion. Therefore, extremely high reliability was obtained.

(Effect of the Invention) According to the present invention, by using a superelastic material for a portion of a semiconductor element which receives thermal strain, it is aimed to prevent breakage by repeating deformation within an elastic range even with repeated strain. Since the bump structure can flexibly follow external distortion, a highly reliable semiconductor element connection structure can be obtained.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention and shows a connection structure using an insulating substrate having a through hole formed of a superelastic material as a bonding medium. FIG. 2 shows a step of forming a through hole in the embodiment of the present invention. 3 to 5 are cross-sectional views of a semiconductor element and a wiring board connected by conventional solder bumps. FIG. 4 shows a state in which the wiring board expands due to a temperature change and shear strain is introduced into the bumps. FIG. 5 is a sectional view showing a semiconductor element connection structure in a case where solder bumps are brought into contact with each other by pressure and fixed with resin. DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Wiring board, 3 ... Solder bump, 4 ... Metal electrode, 5 ... Resin, 6 ... Insulating board, 7
... electroless copper plating layer, 8 ... through-hole made of superelastic material, 9 ... solder, 10 ... plating resist.

Continuation of the front page (72) Inventor Yoshio Ozeki 1618 Ida, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside the New Technology Research Laboratories 1 Nippon Steel Corporation (72) Inventor Keisuke Watanabe 1-7-12 Toranomon, Minato-ku, Tokyo Offshore Inside Electric Industry Co., Ltd. (72) Takashi Kanamori 1-7-12 Toranomon, Minato-ku, Tokyo Oki Inside Electric Industry Co., Ltd. (72) Inventor Yasuo Iguchi 1-7-12 Toranomon, Minato-ku, Tokyo Oki (56) References JP-A-2-137240 (JP, A) JP-A-57-28337 (JP, A) JP-A-2-206139 (JP, A) JP-A-2-180036 (JP, A) JP-A-2-185050 (JP, A) JP-A-2-206124 (JP, A) JP-A-2-206137 (JP, A) JP-A-2-224256 (JP, A) Kaikai 62-152444 (JP, U)

Claims (1)

(57) [Claims] 1. A method for electrically connecting a semiconductor element and a wiring board, wherein an insulating substrate having a through-hole made of a superelastic material is interposed between the semiconductor element and the wiring board. Semiconductor element connection method.