JP2712272B2 - High temperature superconductor - Google Patents
High temperature superconductorInfo
- Publication number
- JP2712272B2 JP2712272B2 JP10359388A JP10359388A JP2712272B2 JP 2712272 B2 JP2712272 B2 JP 2712272B2 JP 10359388 A JP10359388 A JP 10359388A JP 10359388 A JP10359388 A JP 10359388A JP 2712272 B2 JP2712272 B2 JP 2712272B2
- Authority
- JP
- Japan
- Prior art keywords
- temperature superconductor
- film
- semiconductor device
- tin
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment
Landscapes
- Oxygen, Ozone, And Oxides In General (AREA)
- Inorganic Compounds Of Heavy Metals (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高温超導電体構造に関し、とりわけ半導体装
置における高温超導電体による電極配線構造に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-temperature superconductor structure, and more particularly to an electrode wiring structure using a high-temperature superconductor in a semiconductor device.
従来、Y1Ba2Cu3O7等から成るセラミック系高温超導電
体表面にはAg膜が形成されて成るのが通例であった。Conventionally, an Ag film is usually formed on the surface of a ceramic high-temperature superconductor made of Y 1 Ba 2 Cu 3 O 7 or the like.
しかし、上記従来技術によると、高温超導電体の臨界
温度が不安定になると云う課題があった。However, according to the above prior art, there is a problem that the critical temperature of the high-temperature superconductor becomes unstable.
本発明は、かかる従来技術の課題を解決し、臨界温度
の不安定さの無い高温超電導体の構造を提供する事を目
的とし、とりわけ、半導体装置における高温超導電体配
線の安定化を計る新しい構造を提供する事を目的とす
る。An object of the present invention is to solve the problems of the prior art and to provide a structure of a high-temperature superconductor without instability of a critical temperature, and in particular, a new method for stabilizing a high-temperature superconductor wiring in a semiconductor device. The purpose is to provide the structure.
本発明の高温超導電体は、Y1Ba2Cu3O7等から成るセラ
ミック系高温超導電体表面には、TiN、NbN、WN、MoN、Z
rNから選ばれた導電性窒化膜が形成されて成ることを特
徴とする。The high-temperature superconductor of the present invention has a ceramic-based high-temperature superconductor made of Y 1 Ba 2 Cu 3 O 7 or the like, and has TiN, NbN, WN, MoN, ZN
It is characterized in that a conductive nitride film selected from rN is formed.
また、本発明の高温超導電体は、半導体装置における
Y1Ba2Cu3等から成るセラミック高温超伝導体膜配線の少
なくとも一主表面にはTiN、NbN、WN、MoN、ZrNから選ば
れた導電性窒化膜が形成されてなることを特徴とする。Further, the high-temperature superconductor of the present invention is used in a semiconductor device.
A conductive nitride film selected from TiN, NbN, WN, MoN and ZrN is formed on at least one main surface of a ceramic high-temperature superconductor film wiring made of Y 1 Ba 2 Cu 3 or the like. .
また、本発明の高温超導電体は、前記高温超導電体と
前記導電性窒化膜との間に酸素層を有することを特徴と
する。Further, the high-temperature superconductor of the present invention is characterized in that an oxygen layer is provided between the high-temperature superconductor and the conductive nitride film.
Y1Ba2Cu3O7等から成るセラミック系高温超導電体表面
に、TiN、NbN、WN、MoN、ＺrＮ等の導電性窒化膜を形成
すると、Y1Ba2Cu3O7等のセラミック系高温超導電体から
の酸素放出を防止することができ、酸素放出による臨界
温度の低下を防止することができる作用がある。The Y 1 Ba 2 Cu 3 consisting O 7 or the like ceramic high-temperature superconducting collector surface, TiN, NbN, WN, MoN , to form a conductive nitride film such as Z r N, Y 1 Ba 2 Cu 3 O 7 , etc. Has the function of preventing the release of oxygen from the ceramic high-temperature superconductor of the present invention and preventing the critical temperature from being lowered by the release of oxygen.
以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be described in detail with reference to examples.
第１図は本発明の一実施例を示す高温超導電体による
線材の断面図である。すなわち、Y1Ba2Cu3O7芯線１の表
面にはTiN被覆層３がスパッタ法等により形成され、該T
iN被覆層３を通して高エネルギーイオン打込み装置によ
る酸素イオン打込み層２が形成された後、400℃程度の
アニール処理が施されて成る。尚、TiN被覆層３の下にA
g層が形成されても良い事は云うまでもない。FIG. 1 is a sectional view of a wire made of a high-temperature superconductor showing one embodiment of the present invention. That is, a TiN coating layer 3 is formed on the surface of the Y 1 Ba 2 Cu 3 O 7 core wire 1 by a sputtering method or the like.
After the oxygen ion implanted layer 2 is formed by the high energy ion implanter through the iN coating layer 3, an annealing process at about 400 ° C. is performed. In addition, A under the TiN coating layer 3
It goes without saying that the g layer may be formed.
第２図は本発明の他の実施例を示す半導体装置におけ
る高温超導電体配線構造を示す断面図である。すなわ
ち、Si基板11の表面には、通常の半導体装置の製造方法
によりSiO2膜12及び拡散層13が形成され、該拡散層13の
上のSiO2膜12にはコンタクト穴が開けられ、その上にTi
N膜14、Y1Ba2Cu3O7膜15及び主表面へのTiN膜16がスパッ
タ法で形成された後、ホト・エッチングにより電極配線
となされた後、Si3N4膜17がプラズマCVD法により形成さ
れ、その後、必要とあらばY1Ba2Cu3O7膜15内に酸素イオ
ン打込みがなされ、アニール処理された後、Si3N4膜17
にパッド部コンタクト穴開けされて、該パッド部にAl電
極18が通常の半導体装置の製造に従って形成される。FIG. 2 is a sectional view showing a high-temperature superconductor wiring structure in a semiconductor device according to another embodiment of the present invention. That is, an SiO 2 film 12 and a diffusion layer 13 are formed on the surface of the Si substrate 11 by a normal method of manufacturing a semiconductor device, and a contact hole is formed in the SiO 2 film 12 on the diffusion layer 13. Ti on top
After the N film 14, the Y 1 Ba 2 Cu 3 O 7 film 15 and the TiN film 16 on the main surface are formed by the sputtering method, the resulting film is used as an electrode wiring by photo etching, and the Si 3 N 4 film 17 is is formed by a CVD method, then, if necessary Y 1 Ba 2 Cu oxygen ion implantation to 3 O 7 film 15 is made, after being annealed, Si 3 N 4 film 17
A contact hole is formed in the pad portion, and an Al electrode 18 is formed in the pad portion in accordance with a normal manufacturing of a semiconductor device.
本発明により、セラミック系高温超導電体の臨界温度
の不安定さを防止できる効果があり、とりわけ、セラミ
ック系高温超導電体による電極配線を半導体装置に適用
した場合及び該電極配線に酸素イオン打込みにより臨界
温度の上昇を計った場合には、酸素の自然放出を導電性
窒化膜で防止する事ができる効果を保ちながら、パッド
部に外部リード線との接続のためのAl電極を形成するこ
とが出来る効果がある。The present invention has the effect of preventing instability of the critical temperature of a ceramic-based high-temperature superconductor. Particularly, when an electrode wiring made of a ceramic-based high-temperature superconductor is applied to a semiconductor device and oxygen ion implantation is performed on the electrode wiring. When the rise in critical temperature is measured, it is necessary to form an Al electrode for connection with an external lead wire on the pad while maintaining the effect that the spontaneous release of oxygen can be prevented by the conductive nitride film. There is an effect that can be.
第１図は本発明の一実施例を示す高温超導電体線材の断
面図であり、第２図は本発明の他の実施例を示す半導体
装置における高温超導電体配線構造を示す断面図であ
る。 １……Y1Ba2Cu3O7芯線 ２……酸素イオン打込み層 ３……TiN被覆層 11……Si基板 12……SiO2膜 13……拡散層 14、16……TiN膜 15……Y1Ba2Cu3O7膜 17……Si3N4膜 18……Al電極FIG. 1 is a sectional view of a high-temperature superconductor wire showing one embodiment of the present invention, and FIG. 2 is a sectional view showing a high-temperature superconductor wiring structure in a semiconductor device showing another embodiment of the present invention. is there. 1 ...... Y 1 Ba 2 Cu 3 O 7 core 2 ...... oxygen ion implanted layer 3 ...... TiN coating layer 11 ...... Si substrate 12 ...... SiO 2 film 13 ...... diffusion layers 14, 16 ...... TiN film 15 ... … Y 1 Ba 2 Cu 3 O 7 film 17 …… Si 3 N 4 film 18 …… Al electrode
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 39/06 ＺＡＡ Ｈ０１Ｌ 21/88 ＺＡＡＲ Continued on the front page (51) Int.Cl. 6 Identification number Agency reference number FI Technical indication location H01L 39/06 ZAA H01L 21/88 ZAAR
Claims (3)
導電体表面には、TiN、NbN、WN、MoN、ZrNから選ばれた
導電性窒化膜が形成されて成ることを特徴とする高温超
電導体。1. A ceramic high-temperature superconductor made of Y 1 Ba 2 Cu 3 O 7 or the like, on which a conductive nitride film selected from TiN, NbN, WN, MoN, and ZrN is formed. High-temperature superconductor characterized.
セラミック高温超伝導体膜配線の少なくとも一主表面に
はTiN、NbN、WN、MoN、ZrNから選ばれた導電性窒化膜が
形成されてなることを特徴とする半導体装置の配線にお
ける高温超電導体。2. A conductive nitride film selected from TiN, NbN, WN, MoN, and ZrN on at least one main surface of a ceramic high-temperature superconductor film wiring made of Y 1 Ba 2 Cu 3 O 7 or the like in a semiconductor device. A high-temperature superconductor in a wiring of a semiconductor device, wherein a superconductor is formed.
間に酸素層を有することを特徴とする請求項１又は請求
項２記載の高温超電導体。3. The high-temperature superconductor according to claim 1, further comprising an oxygen layer between said high-temperature superconductor and said conductive nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10359388A JP2712272B2 (en) | 1988-04-26 | 1988-04-26 | High temperature superconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10359388A JP2712272B2 (en) | 1988-04-26 | 1988-04-26 | High temperature superconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01275407A JPH01275407A (en) | 1989-11-06 |
| JP2712272B2 true JP2712272B2 (en) | 1998-02-10 |
Family
ID=14358068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10359388A Expired - Lifetime JP2712272B2 (en) | 1988-04-26 | 1988-04-26 | High temperature superconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2712272B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09122510A (en) * | 1995-11-02 | 1997-05-13 | Satake Eng Co Ltd | Detachment device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01132008A (en) * | 1987-11-18 | 1989-05-24 | Matsushita Electric Ind Co Ltd | Superconductor and its manufacture |
| JPH01137685A (en) * | 1987-11-25 | 1989-05-30 | Matsushita Electric Ind Co Ltd | Formation of superconducting thin film |
| JPH01140683A (en) * | 1987-11-26 | 1989-06-01 | Matsushita Electric Ind Co Ltd | Formation of superconducting thin film |
-
1988
- 1988-04-26 JP JP10359388A patent/JP2712272B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01275407A (en) | 1989-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3753774A (en) | Method for making an intermetallic contact to a semiconductor device | |
| CA1048654A (en) | High speed, high yield cmos/sos process | |
| GB991174A (en) | Semiconductor devices and methods of making them | |
| US5895252A (en) | Field oxidation by implanted oxygen (FIMOX) | |
| US3492174A (en) | Method of making a semiconductor device | |
| EP0365107A3 (en) | Manufacturing method for vertically conductive semiconductor devices | |
| US4039359A (en) | Method of manufacturing a flattened semiconductor device | |
| JP2712272B2 (en) | High temperature superconductor | |
| JP2607399B2 (en) | Semiconductor substrate manufacturing method | |
| GB1280199A (en) | Method for producing semiconductor device utilizing ion implantation | |
| US3694700A (en) | Integrated circuit including field effect transistor and cerment resistor | |
| US5219766A (en) | Semiconductor device having a radiation resistance and method for manufacturing same | |
| JPS61123152A (en) | Separation of semiconductor device | |
| JPS6289357A (en) | Manufacture of low resistivity region with low defect density in bipolar integrated circuit | |
| JP3105999B2 (en) | Solar cell manufacturing method | |
| US4840918A (en) | Method of noise reduction in CCD solid state imagers | |
| JP2666337B2 (en) | High-Tc superconductor contact structure | |
| JP2956521B2 (en) | Method for manufacturing high-temperature superconductor | |
| JP2961544B2 (en) | Semiconductor integrated circuit device | |
| JPS61228661A (en) | Semiconductor device and its manufacturing method | |
| JPH01165156A (en) | semiconductor equipment | |
| EP0432789A1 (en) | Method of manufacturing a semiconductor element with the extrinsic gettering process | |
| JPS58170030A (en) | Manufacture of semiconductor device | |
| JPH01238144A (en) | Manufacture of semiconductor device | |
| JPH0628281B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081031 Year of fee payment: 11 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081031 Year of fee payment: 11 |