JP2713082B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having at least a pair of symmetric MOSFETs.

[0002]

2. Description of the Related Art Some semiconductor devices include a pair of MOSFETs.
Some devices have a T. For example, it is a sense amplifier. In order to increase the storage capacity of a semiconductor memory device, the size of the memory cell has been reduced and the degree of integration has been increased.

In order to improve the storage capacity of a semiconductor memory device, it is necessary to reduce not only the size of a memory cell but also the size of a sense amplifier. In general, when the size of a semiconductor device is reduced, according to a change in process parameters in a process of manufacturing such a semiconductor device,
The tendency of the shape and size of each part of the formed semiconductor element to change and the actual electric property of the semiconductor element to shift from the expected electric property increase.

A semiconductor device such as a sense amplifier includes at least a pair of MOSFETs that are required to have high symmetry. For this reason, if the symmetry is degraded due to the above-mentioned variation in the process parameters, such a semiconductor device cannot achieve a desired function. FIG.
1 shows a typical configuration of a sense amplifier circuit. FIG. 11 shows a first bit line pair bit1 and bit1 bar, a second bit line pair bit2 and bit2 bar, and a sense amplifier SA connected to each bit line pair.
Are shown. Each sense amplifier SA has a pair of MOs.
It has an SFET. FIG. 12 shows each sense amplifier SA
Among them, a circuit configuration of a MOSFET pair requiring high symmetry is schematically shown. Here, the first MOSFET
Has a source region 110, a gate electrode 140a, and a drain region 120a.
It has a source region 110, a gate electrode 140a, and a drain region 120a shared with the first MOSFET. In the sense amplifier SA, regarding electric characteristics,
The first MOSFET and the second MOSFET need to be equivalent. In other words, high symmetry is required between the first MOSFET and the second MOSFET.

FIG. 13 shows an example of a layout of a conventional sense amplifier. FIG. 14 is a sectional view taken along line BB of FIG. On the upper surface of the semiconductor layer (substrate) 1, a plurality of active regions 20a and 20b separated by the separation region 3 are provided. The bit line pairs bit1, bit1, bar, bit2, bit2 bar,... Extend in the first direction X. The plurality of active regions 20a and 20b are respectively arranged along the second direction Y. The sense amplifier that senses the bit line pair bit1 and the bit1 bar includes a pair of MOSFETs. This pair of MOSFETs has a gate electrode 14a,
14b. The gate electrodes 14a and 14b correspond to the gate electrodes 140a and 140b in FIG.
Source region 110 and drain region 120 in FIG.
a and 120b are source regions 1 in FIG.
1, corresponding to the drain regions 12a and 12b.

In this prior art, the sense amplifier MOS
The first MOSFET and the second MOS of the FET pair
The FETs are formed in separate active regions. That is, the first active region 20a is separated from the second active region 20b by the separation region 3 (FIG. 1).
4).

According to such a sense amplifier, the following problem occurs with respect to symmetry. That is, the ion implantation for forming the source region 11 and the drain regions 12a and 12b deteriorates the symmetry of the electrical characteristics of the pair of MOSFETs. This is because the ions are in the semiconductor layer 1
Is injected into the semiconductor layer 1 not perpendicularly to the surface but at an angle shifted from the perpendicular by about 7 °. Such oblique ion implantation prevents channeling of ions, but shifts the position of the channel region, which should be located immediately below the gate electrode, in a certain direction with respect to the positions of the gate electrodes 14a, 14b. As a result, the positional relationship between the source region 11 and the drain region 12a, 12b with respect to the gate electrodes 14a, 14b loses the symmetry, thereby deteriorating the symmetry of the electrical characteristics of the pair of MOSFETs.

According to such a sense amplifier,
Since the isolation region 3 exists between the first MOSFET and the second MOSFET, it is difficult to reduce the size of the sense amplifier.

FIG. 15 shows another configuration example of a conventional sense amplifier. FIG. 16 is a sectional view taken along line CC of FIG. According to this sense amplifier, the first MOSFET
There is no element isolation between the first MOSFET and the second MOSFET.
Each of the pair of MOSFETs has a U-shaped gate electrode 14a, 14b. On the planar layout, regions where the gate electrodes 14a and 14b cut out from the active region 2 are drain regions 12a and 12b. In this sense amplifier, even if the isolation region 3 is not used, a pair of M
The drain regions 12a and 12b of the OSFET are separated from each other.

In this conventional example, the problem related to oblique ion implantation in the above ion implantation step is also solved. This is because the influence of the shift of the source region 11 and the drain regions 12a and 12b with respect to the gate electrodes 14a and 14b is offset by each other.

[0011]

However, the above-mentioned prior art has the following problems.

When the resistance of a certain contact 4 among the plurality of source contacts 4 in the source region 11 fluctuates,
The symmetry of the pair of MOSFETs is lost. This will be described below with reference to FIGS. 17 (a) and 17 (b).

First, the bit line resistance is 5 kΩ, the bit line capacitance is 100 fF, and the resistance of the source contact is 1
Assuming that the sheet resistance of the source region is 0 Ω and the sheet resistance of the source region is 100 Ω / □, the asymmetry of the sense amplifier caused by the change in the resistance of the source contact is examined.

It is assumed that dust generated during the manufacturing process affects one of the source contacts 4, and as a result, the contact resistance becomes 1 kΩ (FIG. 17B). When a simulation was performed under these conditions, it was found that the sensing speed of the sense amplifier was reduced by about 20%.

In a miniaturized sense amplifier used in a DRAM, such a defect of the source contact 4 is liable to occur, so that the risk of malfunction of the sense amplifier due to the asymmetry of the resistance of the source contact 4 is further increased. Increase.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide at least one pair of MOSFETs whose symmetry hardly deteriorates even if process parameters fluctuate during a manufacturing process. To provide a semiconductor device. Another object of the present invention is to provide a semiconductor device provided with at least one pair of MOSFETs having a reduced layout size and a configuration suitable for high integration.

[0017]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device comprising a semiconductor layer having an upper surface, an active region formed on the upper surface, and an isolation region formed on the upper surface and surrounding the active region, wherein the device is formed on the active region. A pair of MOSFETs, the pair of MOSFETs being symmetric about a first plane of symmetry substantially perpendicular to the top surface, and being perpendicular to both the top surface and the first plane of symmetry. The pair of MOSFETs each have a source region, a drain region, and a channel region formed on a surface of the active region. Is common to the pair of MOSFETs and in front of the semiconductor layer.
At the portion along the axis where the upper surface and the second symmetry plane intersect.
And a source contact region, wherein each drain region is separated from the source region by each of the channel regions, thereby achieving the above object.

[0018] Each of the channel regions of the pair of MOSFETs may have a substantially U-shaped shape.

[0019] Each of the channel regions of the pair of MOSFETs may have a substantially O-shape.

Each of the pair of MOSFETs has a gate electrode located above the channel region and defining a shape of the channel region.

[0021] Preferably, the source region and the drain region are self-aligned with the gate electrode.

The semiconductor device further comprises a plurality of pairs of MOSFETs having the same structure as the pair of MOSFETs,
Along the axis where the upper surface and the second symmetry plane intersect
May have a plurality of the source contact regions .

Each of the gate electrodes of the pair of MOSFETs has a first portion substantially parallel to the upper surface and the second symmetry plane, and is electrically connected to the first portion;
And it may have a second part parallel to the first part.

Preferably, the first portion and the second portion of each of the gate electrodes of the pair of MOSFETs cross a part of a boundary between the active region and the isolation region.

Each gate electrode of the pair of MOSFETs has a third portion for electrically connecting an end of the first portion and an end of the second portion, and the third portion has ,
It may be substantially parallel to the second plane of symmetry.

Preferably, in each of the gate electrodes of the pair of MOSFETs, a width of the first portion and the second portion is smaller than a width of the third portion.

Each of the gate electrodes of the pair of MOSFETs has a fourth portion for electrically connecting the first portion and the second portion, and the fourth portion is connected to the third portion. The first portion and the second portion may be connected in parallel.

Preferably, among the gate electrodes of each of the pair of MOSFETs, the fourth portion crosses a part of a boundary between the active region and the isolation region.

[0029] Each gate electrode of the pair of MOSFETs may have a ring-shaped portion.

The ring-shaped portion of each gate electrode of the pair of MOSFETs may be located on the active region without crossing a part of a boundary between the active region and the isolation region.

Preferably, the ring-shaped portion of each gate electrode of the pair of MOSFETs crosses a part of a boundary between the active region and the isolation region.

[0032]

The pair of MOSFETs have a pair of gate electrodes.
Wherein the gate electrode pair is substantially perpendicular to the top surface.
A first symmetry plane, and the upper surface and the
For the second symmetry plane perpendicular to both of the first symmetry planes
Symmetric, and each of the gate electrode pairs is
A first portion and a second portion extending along an end of the first portion;
A third portion electrically connecting the end of the second portion, and
A fourth portion for electrically connecting the first portion and the second portion;
Wherein the fourth portion comprises the active region and the isolation region.
Is located on the border with.

Preferably, the width of the first portion and the second portion of the gate electrode is smaller than the width of the third portion.

[0035]

According to the present invention, even if the process parameters fluctuate during the manufacturing process, the electric characteristics of the MOSFET can be improved.
Symmetry does not easily deteriorate. Further, the layout size is reduced, which is suitable for high integration. Further, since the area of the drain region can be reduced, the drain capacitance is reduced and the operation speed of the semiconductor device is improved.

[0036]

(Embodiment 1) FIG. 1 schematically shows a planar structure of a main part of a semiconductor device according to the present invention. FIG.
FIG. 2 is a sectional view taken along line AA of FIG. 1. This semiconductor device has a DR
AM sense amplifier. The present semiconductor device includes a semiconductor layer (including a single crystal semiconductor substrate) 1, a plurality of active regions 2 formed on an upper surface of the semiconductor layer 1, and an isolation region for isolating each active region 2 from each other. 3 is provided.
FIGS. 1 and 2 show one active region 2 surrounded by an isolation region 3, and another portion of the semiconductor device, for example,
DRAM memory cells and the like are omitted for simplicity.

The present semiconductor device has a plurality of MOSFET pairs 10 arranged in the active region 2. Each MOSFE
The T pair corresponds to the MOSFET pair in FIG. 12, and forms one sense amplifier SA. Each of the MOSFET pairs 10 includes a first MOSFET 10a and a second MOSFET 10a.
10b.

Each of the MOSFET pairs 10 is symmetric with respect to a first plane of symmetry parallel to the first direction X shown in FIG. The first symmetry plane is perpendicular to the upper surface S of the semiconductor layer 1 shown in FIG. Each of the MOSFET pairs 10 is also symmetric with respect to a second plane of symmetry parallel to the second direction Y shown in FIG. This second plane of symmetry is perpendicular to both the upper surface S (FIG. 2) of the semiconductor layer 1 and the first plane of symmetry.

As shown in FIG. 2, the first MOSFE
Each of the T10a and the second MOSFET 10b has a source region 11, a drain region 12a, 12b, and a channel region 13a, 13b formed on the surface of the active region 2. Source region 11 and drain region 12a,
Reference numerals 12b each denote an impurity diffusion layer formed in the active region 2 of the semiconductor layer 1. When the MOSFETs 10a and 10b are of the n-channel type, the active region 2
The source region 11 and the drain regions 12a and 12b are regions where the n-type impurity is relatively heavily doped. In this sense amplifier, the source region 11 is
a, 10b are common. However, the drain region 12
a and 12b are separated from the common source region 11 by corresponding channel regions 13a and 13b, respectively, as shown in FIG.

As shown in FIG. 2, the first and second M
Each of the OSFETs 10a and 10b has a channel region 1
Gate electrodes 14a, 14 located above 3a, 13b
b. The gate electrodes 14a and 14b define the shapes of the channel regions 13a and 13b. The source region 11 and the drain regions 12a, 12b are formed in self-alignment with the gate electrodes 14a, 14b.

More specifically, the MOSFET of the present sense amplifier
Is described below. As shown in FIG. 1, each gate electrode 14a, 14b is formed on the upper surface of the semiconductor layer 1 and on the second
It has a first portion substantially parallel to the plane of symmetry and a second portion substantially parallel to the first portion. First
The portion and the second portion are connected by a third portion.
The first part and the second part each have a width of 0.8 μm and a width of 2 μm.
m . The third part is 0.8 μm each
And a length of 2 μm. The width of each part of these gate electrodes 14a and 14b is
The length of each portion corresponds to the channel width (W) of the MOSFET 10a, 10b.
It corresponds to. Each MOSFET 10 in this embodiment
The channel lengths of a and 10b are 0.8 μm and the channel width is about 4 μm. The distance between the third part of the first MOSFET 10a and the third part of the second MOSFET 10b is 0.6 μm. Note that the width of the active region 2 measured along the first direction X is about 6 μm.

The first of the gate electrodes 14a, 14b
The first portion and the second portion extending in the direction X cross the boundary between the active region 2 and the isolation region 3. Thus, the substantially U-shaped gate electrodes 14a and 14b are arranged so as to cut out the drain regions 12a and 12b from the active region 2. According to the layout of the prior art in FIG. 13, the width of the active region 2 measured along the first direction X is about 10 μm according to the design rule adopted in this embodiment. This is the first
This is because it is necessary to provide the isolation region 3 having a width of 0.6 μm or more between the MOSFET 10a and the second MOSFET 10b. On the other hand, in the present embodiment, as described above, the width of the active region 2 measured along the first direction X is about 6 μm. Therefore, the area occupied by the sense amplifier is reduced by 40%.

The gate electrodes 14a and 14b can be generally formed into an arbitrary plane shape by patterning a layer made of an electrode material by a photolithography step and an etching step. Real gate electrodes 14a, 14
The shape of b does not need to be composed of only linear elements, as shown in FIG. Gate electrodes 14a, 1
4b may be curved, thereby forming a round U-shape. The effects of the present invention, which will be described later, occur regardless of the material of the gate electrodes 14a and 14b, and the type and size of the cross-sectional configuration.

As shown in FIG. 2, channel regions 13a and 13b are formed in portions of the active region 2 immediately below the gate electrodes 14a and 14b, respectively. That is, the channel region 13 has a planar shape substantially corresponding to the planar shape of the gate electrodes 14a and 14b.
Are formed in the active region 2. Each of these channel regions 13a, 13b has a single source region 11 common to each MOSFET pair 10 and a MOSFET 10
a, drain regions 12a, 12b provided for every 10b
Exists between The size of each channel region 13 can be arbitrarily adjusted by changing the shape (width and length) of the gate electrodes 14a and 14b. When the sense amplifier operates, the source region 11 and the drain region 12a,
The conductivity of the channel region 13 connecting to the gate electrode 12b is controlled according to the potential applied to the corresponding gate electrodes 14a and 14b.

The source region 11 and the drain region 12a,
12b, after forming the gate electrodes 14a and 14b having a desired shape, performing an ion implantation process using the gate electrodes 14a and 14b as a mask, thereby forming the gate electrodes 14a and 14b.
b can be formed in a self-aligned manner. Note that the planar shape and position of the channel region 13 completely match the planar shape and position of the gate electrodes 14a and 14b due to the implantation angle of ion implantation, lateral diffusion of impurities due to heat treatment after ion implantation, and the like. is not. For example, in FIG. 2, when impurity ions are implanted into the semiconductor layer 1 in the direction of arrow M, the source region 11 and the drain region 12a,
12b is shifted in the direction opposite to the first direction X with respect to each of the gate electrodes 14a and 14b.

The source region 11 and the channel region 13
, And between the drain regions 12a and 12b and the channel region 13, an LDD region, a punch-through stopper region, and the like may be provided.

As shown in FIG. 1, a plurality of MOSFEs
The T pairs 10 are arranged along the second direction Y. When the sense amplifier is used for sensing bit line pairs, a number of MOSFET pairs equal to the number of bit line pairs are arranged along the second direction Y. For example, 102
1024 MOSs for 4 bit line pairs
FET pairs are arranged. In this case, the second region of the active region 2
The length along the direction Y reaches, for example, 4 μm × 1024 = about 4 mm.

A plurality of source contacts 4 are formed in a region between each of the plurality of MOSFET pairs 10 and along an axis parallel to the second direction Y. These source contacts 4 are for electrically connecting the source region 11 formed in the active region 2 to a wiring (not shown). Although only three source contacts 4 are shown in FIG. 1, in this embodiment, approximately the same number of MOSFET pairs 10 are provided. The potential of the wiring connected to the source contact 4 corresponds to the potential of the terminal 110 of the circuit in FIG. In the present sense amplifier, the size of the source contact 4 is typically 0.6 μm × 0.6
μm. The distance between the source contacts 4 is about 4 μm
It is. This means that the noise measured along the second direction of one sense amplifier is about 4 μm.

FIG. 3 schematically shows an arrangement relationship between the sense amplifiers and the bit line pairs according to the present embodiment. When sense amplifiers are arranged on both sides of the memory cell array portion where the bit line pairs exist, the sense amplifiers shown in FIG. 1 can sense bit lines arranged at 1 μm intervals. According to the conventional sense amplifier shown in FIG. 15, the arrangement interval of the bit lines is about 2 μm. 64 megabit D
In a RAM, usually, it is necessary to arrange bit lines at intervals of 1 μm, so it is difficult to apply the sense amplifier of FIG. 15 to a 64-Mbit DRAM. The sense amplifier of the present embodiment is suitable for such a highly integrated semiconductor memory device. In addition, one drain contact (not shown) for connecting each drain region 12a, 12b and a wiring is provided for each corresponding drain region 12a, 12b. In this embodiment, the drain contacts provided in the drain regions 12a and 12b are connected to the bit line pairs shown in FIG.

According to this sense amplifier, even if the value of the contact resistance of any one of the plurality of source contacts 4 is changed from the contact resistance of the other source contact 4 for some reason, each pair of source contacts 4 MOSFET1
The symmetry of the electrical characteristics of 0a and 10b is maintained. The effect of the change in the contact resistance depends on the left and right MOSFETs 10.
This is because they contribute similarly to a and 10b.

In this embodiment, the source contact 4 is
Although they are arranged in one row along the direction Y, they may be arranged in two or more rows. Further, the number of source contacts 4 may be about half of the number of MOSFET pairs 10. First MOSFET 10a and second MOSFET
In order to make the electrical characteristics of the ET 10b equal, it is preferable that the arrangement of the source contacts 4 is symmetric with respect to the second symmetry plane. However, when two rows of source contacts are provided, if one of the corresponding two source contacts becomes extremely large, the first MOSFET 10a and the second MOSFET
As a result of the difference in the source parasitic resistance of the SFET 10b, the characteristics of the sense amplifier deteriorate. Therefore, the row of the source contacts 4 is most preferably one row.

If the position of the row of the source contacts 4 shifts in the first direction X, the source resistance of the first MOSFET 10a and the source resistance of the second MOSFET 10b have values slightly different from each other. FIG. 4 shows the source contact 4 shifted in the first direction X by a distance x from the position of the second symmetry plane. FIG. 5 shows the shift amount x
And the relationship between the speed and the sensing speed of the sense amplifier. In the position as shown in FIG.
Is provided, the source parasitic resistance in the first MOSFET 10a becomes, for example, 10Ω, and the second MOSFET 1a
The source parasitic resistance of 0b is, for example, 1 kΩ.
In such a case, the sensing speed is reduced by about 20 percent. For this reason, in order to maintain the symmetry of the MOSFET pair 10 high and prevent the sensing speed from lowering, it is preferable that the position of the row of the source contacts 4 is located near the second symmetry plane.

In the layout, even if the source contact 4 is on the second symmetry plane, the position of the source contact 4 is shifted to some extent due to an alignment shift in the photolithography process. However, such shifts are typically on the order of 1 μm or less, so that the source parasitic resistance only slightly changes. Therefore, the shift of the position due to the manufacturing process of the source contact 4 hardly affects the characteristics of the sense amplifier.

When the sheet resistance of the source region 11 is sufficiently small, one source contact 4 may be provided for a plurality of MOSFET pairs 10. By doing so, the number of the source contacts 4 can be reduced, and the size of the sense amplifier measured in the second direction Y can be further reduced. Even if the number of source contacts 4 is reduced, the first MO in each MOSFET pair 10
The symmetry between the SFET and the second MOSFET is maintained.
Further, when the number of the source contacts 4 is reduced, there is an advantage that the probability of occurrence of a contact failure is reduced in the semiconductor device as a whole.

In this embodiment, the shape of the gate electrode on the planar layout is substantially U-shaped, but the shape of the gate electrodes 14a and 14b on the layout is V-shaped as shown in FIG. It may be a type.

(Embodiment 2) FIG. 7 schematically shows a plan structure of a main part of another sense amplifier according to the present invention.
This sense amplifier also has a plurality of MOs formed in the active region 2.
An SFET pair 10 is provided. Multiple MOSFET pairs 1
0 are the first MOSFET 10a and the second MOSFET
FET 10b. MOSFET vs. 1 in FIG.
0, the MOSFET pair 10 of this sense amplifier is
It is symmetric with respect to a first plane of symmetry parallel to the first direction X. The MOSFET pair 10 is also symmetric with respect to the second plane of symmetry. First MOSFET 10a and second MOS
Each of the FETs 10b has a source region 11, drain regions 12a and 12b, and channel regions 13a and 13b formed on the surface of the active region 2. Source area 11
Is common to the MOSFETs 10a and 10b. However, the drain regions 12a, 12b are separated from the source region by the corresponding channel regions 13a, 13b, respectively.

The gate electrodes 24a, 24b of each of the MOSFETs 10a, 10b have a first portion and a second portion substantially parallel to the second plane of symmetry. Each of the gate electrodes 24a and 24b has a third portion that electrically connects an end of the first portion and an end of the second portion, and the third portion is substantially formed with respect to the second symmetry plane. Parallel. Further, each of the gate electrodes 24a and 24b has a fourth portion for electrically connecting the first portion and the second portion.
The first part and the second part are connected in parallel with the third part. Thus, the first to fourth portions form a ring-shaped portion.

As shown in FIG. 7, each gate electrode 24
The active region 2 is divided into a source region 11 and a plurality of drain regions 12a and 12b by ring-shaped portions a and 24b. In the sense amplifier of FIG.
Although a part of the boundary between 2a and 12b is in contact with the boundary (isolation region 3) between active regions 2, in the present sense amplifier, drain regions 12a and 12b are connected to corresponding gate electrodes 24a and 24b.
24b, and is not in contact with the isolation region 3. For this reason, even if the position of the gate electrodes 24a and 24b is slightly shifted from the position of the active region 2 due to misalignment of a mask in a photolithography process for forming the gate electrodes 24a and 24b, the drain region 24
The areas of a and 24b do not change.

For example, a region surrounded by a ring-shaped portion;
If the distance from the isolation region is 1 μm, the gate width (W) of the MOSFET is maintained at a constant value even if the gate electrodes 24 a and 24 b shift in the first direction X by 1 μm. As a result, symmetry is maintained with respect to the electrical characteristics of each MOSFET pair 10. Gate electrode 24
The larger the distance (margin) between the ring-shaped portions of the active regions a and 24b and the boundary of the active region 2, the larger the gate electrodes 24a, 2b
The gate width (W) of the MOSFET can be kept constant with respect to the large positional deviation of 4b.

In FIG. 7, each gate electrode 24a, 2
4b (ie the channel regions 13a, 13b also)
Although constituted by a straight line portion, the gate electrode 24a,
The ring-shaped portion 24b may have a shape that is topologically equivalent to the ring shape, for example, an ellipse, a triangle, a polygon, or the like. 2. Description of the Related Art Generally, in a semiconductor device manufacturing process, a pattern is transferred to a photoresist on a semiconductor device being manufactured using a photomask that defines a pattern. Even if the pattern on the photomask is composed of linear portions as shown in FIG. 7, the pattern transferred to the photoresist may have a curved shape. It is clear that the above-described advantages of the present invention do not require that the gate electrodes 24a, 24b be formed of linear components at all.

In the active region 2, the gate electrodes 24a,
MOSFET channel regions 13a and 13b are formed in a portion located immediately below 24b. That is, a plurality of channel regions 13 a and 13 b having a planar shape substantially corresponding to the planar shapes of the gate electrodes 24 a and 24 b are formed in the active region 2. In this sense amplifier, each of these channel regions 13a and 13b has a ring shape, and a single source region 11 common to each of the MOSFETs 10a and 10b,
a, drain regions 12a, 12b provided for every 10b
Exists between Each channel region 13a, 13b
Is controlled by adjusting the shapes (width and length) of the gate electrodes 24a and 24b. In the planar layout, the region surrounded by the ring-shaped portions of the gate electrodes 24 a and 24 b is completely included in the active region 2.

According to the above configuration, the position of the gate electrodes 24a, 24b with respect to the position of the active region 2 is set in the first direction X.
, The gate width (W) of each MOSFET remains unchanged. As a result, the two M
The electrical characteristics of the OSFETs 10a and 10b maintain symmetry.

The plurality of MOSFET pairs 10 are arranged in the second direction Y
And each MOSFET pair 10 is
It is symmetric about an axis parallel to the second direction Y. In addition, each M
A plurality of source contacts 4 are formed in a region between the OSFET pair 10 and along an axis parallel to the second direction Y.

According to the above configuration, the position of the gate electrodes 24a and 24b with respect to the position of the active region 2 is set in the first direction X.
And each MOSF is slightly shifted in the second direction Y.
The gate width (W) of the ET is unchanged. Even if the contact resistance of the source contact 4 varies,
The symmetry of OSFET pair 10 is maintained.

(Embodiment 3) FIG. 8 schematically shows a planar structure of a main part of another semiconductor device according to the present invention. This semiconductor device has basically the same structure as the structure of the device shown in FIG. The description of the same parts is omitted, and different parts will be described below.

Each gate electrode 14a, 14b of the MOSFET pair 10 of the present sense amplifier has a first portion (gate length L) substantially parallel to the upper surface of the semiconductor layer 1 and the second symmetry plane.
1, a gate width W1), a second portion (gate length L2, gate width W2) substantially parallel to the first portion, and a second portion connecting an end of the first portion and an end of the second portion. It has three portions (gate length L3, gate width W3). The gate electrodes 14a and 14b of FIG. 1 and the gate electrodes 14a and 14b of FIG.
Is that the gate lengths L1 and L1 of the first and second portions are different.
2 is shorter than the gate length L3 of the third portion.

The MOSFET 10a shown in FIG.
10b can be considered to have a structure in which three sub-MOSFETs share the source region 11 and the drain regions 12a and 12b. That is,
Sub-MO for the first part of the gate electrodes 14a, 14b
SFET (S1) and sub-MOSFE for the second part
T (S2) and MOSFET related to the third part (S3)
Thus, each MOSFET is configured.

As shown in FIG.
(S1) and the sub MOSFET (S2)
It has a structure symmetrical with respect to the plane of symmetry. However, more strictly, a slight difference may occur between the electric characteristics of the sub-MOSFET (S1) and the electric characteristics of the sub-MOSFET (S2). Generally, the gate electrodes 14a, 1
4b, the source region 11 and the drain region 1 are formed.
In order to form 2a and 12b, an impurity ion implantation step is performed. When implanting ions into a single-crystal semiconductor substrate, for reasons such as preventing channeling of ions,
Ions are implanted at an angle shifted from a direction perpendicular to the upper surface of the semiconductor substrate. In such a case, the gate electrode 14a,
14b, the source region 11 and the drain region 12
a and 12b become slightly asymmetric. However, each MOS
Since the FETs 10a and 10b have the sub-MOSFET (S1) and the sub-MOSFET (S2), the asymmetry of each sub-MOSFET (S1 and S2) is mutually canceled.

On the other hand, for the sub MOSFET (S3), such an asymmetry canceling effect does not occur. According to the present embodiment, by making the channel length of the sub MOSFETs (S1 and S3) shorter than the channel length of the sub MOSFET (S3), the sub MOSFET (S3)
Reduces the rate of contribution to the sensing sensitivity of the sense amplifier. Thereby, the sub MOSFET (S3)
Has little effect on the sensing speed of the sense amplifier.

In this embodiment, the MOSFET 10a,
The effective gate length of 10b is Le, and the effective gate width We is
Then, the following equation is established.

We / Le = (W1 / L1 + W2 / L2 + W3 / L
3) / 3 where W1 = W2 = W3 = 1.3 μm, L3 = 0.8
When the sensing speed of the sense amplifier is calculated by setting L1 = L2 as μm, the speed when L1 = L2 = 0.6 μm is shown in FIG. 9 as compared with the speed when L1 = L2 = 0.8 μm. About 18 percent faster.

According to the present embodiment, by employing the configuration as shown in FIG. 8, the sensing speed can be increased while suppressing the effect of asymmetry due to oblique ion implantation.

(Embodiment 4) FIG. 10 schematically shows a planar structure of a main part of another semiconductor device according to the present invention.
This semiconductor device has basically the same structure as the structure of the device shown in FIG. The description of the same parts is omitted, and different parts will be described below.

The MOSFETs 10a, 1
0b is a first portion (width: 0.6 μm) substantially parallel to the upper surface and the second symmetry plane of the semiconductor layer 1, and is substantially parallel to the first portion. The second part (width: 0.6 μm), the third part (width: 0.8 μm) connecting the end of the first part and the end of the second part, and the connection of the first part and the second part 4th part (width: 0.
6 μm or more). The difference between the gate electrode of FIG. 2 and the gate electrode of FIG. 4 is that the widths of the third and fourth portions are wider than the widths of the first and second portions, and that the fourth portion has an isolation region 3 and an active region 2. Crossing part of the border with

With such a structure, in addition to the effects obtained from the sense amplifier of FIG.
Can be obtained. In a highly integrated semiconductor integrated circuit, it is extremely important to reduce the occupied area (layout area) of the sense amplifier and the like, and therefore, the configuration of this embodiment is particularly preferable for a highly integrated semiconductor device. In particular, the present sense amplifier is suitable for putting a DRAM or the like having a storage capacity of 64 megabits or more into practical use.

Although the present invention has been described with reference to a sense amplifier, the present invention is not limited to a sense amplifier, but is applicable to all semiconductor devices that are required to have high symmetry with respect to a pair of MOSFETs. It is. In other words, it has the circuit configuration shown in FIG.
The present invention can be applied to all semiconductor devices that require symmetry of the MOSFET pair.

[0077]

According to the present invention, even if the process parameters fluctuate during the manufacturing process, the symmetry of the electrical characteristics of the MOSFET hardly deteriorates. Further, the layout size is reduced, which is suitable for high integration. Further, since the area of the drain region can be reduced, the drain capacitance is reduced and the operation speed of the semiconductor device is improved.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a semiconductor device according to the present invention.

FIG. 2 is a sectional view taken along line AA of FIG. 1;

FIG. 3 is a schematic plan view showing an arrangement of a sense amplifier, a bit line pair, and the like according to the present invention;

FIG. 4 is a diagram showing a position shift of a source contact;

FIG. 5 is a graph showing a relationship between a position shift of a source contact and a sensing speed.

FIG. 6 is a plan view showing a V-shaped gate electrode.

FIG. 7 is a layout diagram of another semiconductor device according to the present invention.

FIG. 8 is a layout diagram of still another semiconductor device according to the present invention.

FIG. 9 is a graph showing a relationship between a sensing speed and a gate length.

FIG. 10 is a layout diagram of still another semiconductor device according to the present invention.

FIG. 11 is a circuit diagram of a sense amplifier.

FIG. 12 is a circuit showing a MOSFET pair included in a sense amplifier.

FIG. 13 is a layout diagram of a conventional sense amplifier.

FIG. 14 is a sectional view taken along line BB of FIG. 13;

FIG. 15 is a layout diagram of another conventional sense amplifier.

FIG. 16 is a sectional view taken along line CC of FIG. 15;

FIG. 17 is a circuit diagram of a sense amplifier for explaining a problem caused by a defective source contact.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor layer 2 Active region 3 Isolation region 4 Source contact 10 Sense amplifier 10a, 10b MOSFET 11 Source region 12a, 12b Drain region 14a, 14b, 24a, 24b Gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 27/04 H01L 27/04 A 27/088 27/10 471 (56) References JP 3 -257861 (JP, A) JP-A-58-207677 (JP, A) JP-A-5-13713 (JP, A)

Claims (17)

(57) [Claims] 1. A semiconductor device comprising: a semiconductor layer having an upper surface; an active region formed on the upper surface; and an isolation region formed on the upper surface and surrounding the active region. A pair of MOSFETs formed in the active region, the pair of MOSFETs being symmetric about a first plane of symmetry substantially perpendicular to the top surface, and wherein both the top surface and the first plane of symmetry are provided. A pair of MOSFETs each having a source region, a drain region, and a channel region formed on the surface of the active region. The source region is common to the pair of MOSFETs, and
An axis at which the upper surface of the semiconductor layer intersects with the second symmetry plane
A semiconductor device having a source contact region in a portion along the line, and each drain region is separated from the source region by each of the channel regions. 2. The semiconductor device according to claim 1, wherein each of said channel regions of said pair of MOSFETs has a substantially U-shaped shape. 3. The semiconductor device according to claim 1, wherein each of said channel regions of said pair of MOSFETs has a substantially O-shape. 4. The semiconductor device according to claim 1, wherein each of said pair of MOSFETs includes a gate electrode located above said channel region and defining a shape of said channel region. 5. The semiconductor device according to claim 1, wherein the source region and the drain region are
The semiconductor device according to claim 1, wherein the semiconductor device is self-aligned with the gate electrode. 6. The apparatus of claim 1, further comprising a plurality of pairs of MOSFET having the same structure as the pair of MOSFET, and the semiconductor layer the upper surface and the second plane of symmetry cross Do
A plurality of said source contact regions in a portion along an axis
A semiconductor device having: 7. A gate portion of each of the pair of MOSFETs, a first portion substantially parallel to the upper surface and the second symmetry plane, and electrically connected to the first portion,
5. The semiconductor device according to claim 4, further comprising a second portion parallel to said first portion. 8. The semiconductor according to claim 7, wherein said first portion and said second portion of each gate electrode of said pair of MOSFETs cross a part of a boundary between said active region and said isolation region. apparatus. 9. A gate electrode of each of said pair of MOSFETs has a third portion for electrically connecting an end of said first portion and an end of said second portion. Part,
The semiconductor device according to claim 8, wherein the semiconductor device is substantially parallel to the second plane of symmetry. 10. The semiconductor device according to claim 9, wherein, of each of the gate electrodes of said pair of MOSFETs, a width of said first portion and said second portion is smaller than a width of said third portion. 11. A gate electrode of each of said pair of MOSFETs has a fourth portion for electrically connecting said first portion and said second portion, and said fourth portion is connected to said third portion. The semiconductor device according to claim 9, wherein the first portion and the second portion are connected in parallel with the portion. 12. The semiconductor device according to claim 11, wherein the fourth portion of each of the gate electrodes of the pair of MOSFETs crosses a part of a boundary between the active region and the isolation region. 13. The semiconductor device according to claim 4, wherein each gate electrode of said pair of MOSFETs has a ring-shaped portion. 14. The ring-shaped portion of each gate electrode of the pair of MOSFETs is located on the active region without crossing a part of a boundary between the active region and the isolation region. 14. The semiconductor device according to item 13. 15. The semiconductor device according to claim 13, wherein said ring-shaped portion of each gate electrode of said pair of MOSFETs crosses a part of a boundary between said active region and said isolation region. 16. The pair of MOSFETs comprises a gate electrode pair.
It includes a said gate electrode pairs, first symmetry plane substantially perpendicular to the upper surface
, And perpendicular to both the upper surface and the first plane of symmetry.
The two symmetry planes are also symmetrical, and each of the gate electrode pairs includes a first part and a second part extending along the first symmetry plane,
Electrically connecting the end of one part to the end of the second part
A third portion, and electrically connecting the first portion and the second portion.
A fourth portion following the active region and the isolation region.
The semiconductor device according to claim 1, wherein 17. The device according to claim 17 , wherein the first portion of the gate electrode and the first portion are provided.
The width of the second portion is smaller than the width of the third portion.
7. The semiconductor device according to 6.