JP2716134B2 - Semiconductor transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor transistor using ion implantation, and more particularly, to a semiconductor transistor in which the transistor characteristics are reduced in gm. [Prior Art] In recent years, application of a semiconductor transistor to a digital IC or a monolithic IC has been aimed at achieving a larger scale and higher performance in a high frequency range. In particular, for large-scale integration, it is extremely important to achieve planarization and to improve uniformity of characteristics in a wafer surface. For that purpose, an active layer is formed on a semi-insulating substrate using ion implantation technology,
Transistors provided with source, gate, and drain electrodes have been made planar to improve the uniformity of characteristics within a wafer surface. However, since the operating layer is formed on the semi-insulating substrate by the ion implantation technique, a leakage current flows on the interface side of the operating layer with the substrate due to the impurity trap, and the gate voltage of the transistor's current-voltage characteristic The phenomenon of so-called gm lowering, in which modulation is less likely to be applied on the deep side of, was observed. In 1982, IEEE Tran
s.ED ED-29 A transistor described in K. Yamasaki has been proposed. In this transistor, as shown in FIG. 4, after a p-type impurity atom is implanted into a semi-insulating substrate 21 at a low dose, a donor impurity atom is ion-implanted and activated to form a p-type impurity at an interface between the operation layer 22 and the substrate. Layer 23 is formed and the source electrode
24, a drain electrode 25 and a gate electrode 26 are provided. [Problems to be Solved by the Invention] In the above-mentioned conventional transistor, although the phenomenon of lowering of gm near the pinch-off is eliminated by burying a p-type layer on the substrate interface side, FIG. As shown by the current-voltage characteristics of the transistor, gm near the gate voltage of 0 (V) was not observed when the p-type buried layer was not present due to the combined action of the substrate trap and the p-type impurity on the surface side. There is a problem that an overfill phenomenon is observed. As described above, when the conventional transistor is applied to a digital IC having an E / D configuration, the gm is small as an E-type transistor, the driving capability is inferior even if the D-type transistor is good, and the characteristics of the IC are not preferable. There is a problem. An object of the present invention is to provide a semiconductor transistor capable of increasing gm and improving driving capability even when applied to a digital IC having an E / D configuration. [Means for Solving the Problems] The semiconductor transistor of the present invention is characterized in that the semiconductor transistor of the present invention has an operation layer formed by ion implantation on a GaAs substrate, and has a source and a drain on the surface of the semiconductor substrate. In a semiconductor transistor having an ohmic electrode and a gate electrode, a P-type layer is provided on the substrate side of the operation layer, and a surface compensation layer containing any one of indium, aluminum and boron is provided on the surface side. Embodiment Next, the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention. Beryllium inon is implanted as a p-type impurity atom into the chromium-doped semi-insulating gallium arsenide substrate 1 at an acceleration energy of 90 KeV and a dose of 6 × 10 ¹¹ cm ^-2 to form a p-type layer 3 on the interface side of the substrate. Indium ions as group atoms are implanted over the entire surface at an acceleration energy of 70 KeV and a dose of 5 × 10 ¹¹ cm ⁻² to form a surface compensation layer 4. Next, + Si ³⁰ is selectively implanted as n-type impurity atoms under the condition of 50 KeV, 5 × 10 ¹² cm ⁻² ,
° C., was activated by annealing the 20min / H _2, to form the active layer 2. Needless to say, the operation layer 2, the p-type layer 3, and the surface compensation layer 4 are actually formed in a laminated state based on the result of the implantation and the processing. By forming each ohmic electrode of the source electrode 5 and the drain electrode 6 and the gate electrode 7 on the operation layer 2,
A planar gallium arsenide field effect transistor is obtained. FIG. 3 shows the drain voltage-current characteristics of the transistor having this configuration. As can be seen from this figure, by having the surface compensation layer 4 containing group III atoms on the surface side of the operating layer 2, the surface compensation layer 4 is substituted with the group III atoms, and the surface compensation layer 4 becomes a substrate trap. The compounding action with the p-type impurity is eliminated, and the phenomenon of gm overfilling is prevented. The operation layer 2
Having the p-type layer 3 on the substrate side prevents lowering of gm as in the conventional case, thereby obtaining excellent transistor characteristics. As a result, when applied to a digital IC having an E / D configuration, a drastic improvement in drive capability can be expected. FIG. 2 is a longitudinal sectional view of a second embodiment of the present invention. In this embodiment, a beryllium ion as a p-type impurity atom is applied to a semi-insulating gallium arsenide substrate 11 doped with indium, which is a group III atom, at an acceleration energy of 90 KeV and a dose of 6.
The entire surface is implanted at × 10 ¹¹ cm ⁻² to form a p-type layer 13. Subsequently, + Si ³⁰ is applied as an n-type impurity atom at 50 KeV, 5 × 10 ¹² cm ⁻²
And activated by annealing at 800 ° C. for 20 min / H ₂ to form the operation layer 12. On the surface side of the operation layer 12, a surface compensation layer 14 is formed on the surface portion of the substrate 11. Even in the case of this embodiment, it goes without saying that the operation layer 12, the p-type layer 13, and the surface compensation layer 14 are actually formed in a laminated state according to the results of these implantations and treatments. The source electrode 15 and the drain electrode 16 on the operation layer 12
By forming the respective ohmic electrodes and the gate electrode 17, the planar type gallium arsenide field effect transistor can be obtained. In this embodiment, the same effects as in the first embodiment can be obtained. Note that magnesium may be used as the p-type impurity atom, and aluminum or boron may be used as the group III atom. Further, sulfur or selenium may be used as the n-type impurity atom. [Effect of the Invention] As described above, the present invention has a p-type layer on the substrate side of the operation layer formed on the semiconductor substrate, and has a surface compensation layer containing group III atoms on the surface side, On the surface side, the combined action of the substrate trap and the p-type impurity is eliminated, and on the substrate side, the action of the p-type layer prevents the gm from rising and falling, resulting in excellent transistor characteristics. When applied to a / D configuration digital IC, there is an effect that a drastic improvement in driving capability can be expected.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view of a second embodiment of the present invention, and FIG. 3 is a transistor obtained by the present invention. FIG. 4 is a longitudinal sectional view of a conventional semiconductor transistor, and FIG. 5 is a current-voltage characteristic diagram of a conventional semiconductor transistor. 1 ... Chromium-doped semi-insulating gallium arsenide substrate, 2 ...
Operating layer, 3 ... p-type layer, 4 ... Surface compensation layer, 5 ... Source electrode, 6 ... Drain electrode, 7 ... Gate electrode, 11 ...
… Indium-doped semi-insulating gallium arsenide substrate, 12 ……
Operating layer, 13 p-type layer, 14 surface compensation layer, 15 source electrode, 16 drain electrode, 17 gate electrode, 21
... Semi-insulating substrate, 22 ... Operation layer, 23 ... P-type layer, 24 ...
Source electrode, 25 ... Drain electrode, 26 ... Gate electrode.

Claims (1)

(57) [Claims] In a semiconductor transistor having an operation layer formed by ion implantation on a GaAs substrate and having ohmic electrodes of source and drain and a gate electrode on the surface of the semiconductor substrate, a P-type layer is provided on the substrate side of the operation layer, A semiconductor transistor comprising a surface compensation layer containing any one atom of indium, aluminum, and boron on its side.