JP2716294B2 - System switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system switching system, and more particularly, to a system switching system in a circuit for selecting two redundantly configured clock and frame synchronization signals.

[0002]

2. Description of the Related Art Conventionally, this kind of system switching system is shown in FIG.
As shown in the figure, a second selection circuit 13 which receives the 0-system frame synchronization signal 10 and the 1-system frame synchronization signal 11 as inputs and is selected by the switching signal 4, and receives the 0-system clock and the 1-system clock 2 as inputs, , A PLL circuit 14 and a counter circuit 15.

When either the 0-system clock 1 or the 1-system clock 2 is selected by the switching signal 4 in the first selection circuit 12, the first selection circuit 12 follows the selection clock 3, which is the output signal of the first selection circuit 12. The PLL circuit 14 outputs the output clock 5. The counter circuit 15 which operates by the output clock 5 also uses the switching signal 4 to
The phase is synchronized by the selected frame synchronization signal 7 which is the output of the selected selection circuit 13, and the output frame synchronization signal 6 synchronized with the output clock 5 is output.

[0004]

In the conventional system switching method, when the switching operation is performed by the switching signal 4, the PLL circuit performs the following operation by the phase difference between the 0 system clock 1 and the 1 system clock 2. At this time, the frequency of the output clock 5 fluctuates until it completely follows. During this time, the counter circuit 15 operated by the output clock 5 periodically synchronizes the phase with the output of the second selection circuit 13. To continue the operation, the output frame synchronization signal 6 is
Originally, the output clock 5 must always be output at the same cycle in synchronization with the output clock 5, but a change in the output clock 5 causes a different cycle to be output. In particular, when the fluctuation is severe, there has been a problem that the transmission device may operate improperly.

An object of the present invention is to provide a system switching system capable of minimizing a change in an output frame synchronization signal during a switching operation.

[0006]

According to the present invention, a first selection circuit which receives a first system clock and a second system clock as inputs and is selected by a switching signal, and a frame synchronization of the first system are provided. A signal and a frame synchronization signal of the second system as inputs,
A second selection circuit selected by the switching signal; a PLL circuit that follows a selection clock that is an output signal of the first selection circuit and generates an output clock; A detection circuit that outputs a pulse, a timer circuit that operates by the transition point pulse,
A control circuit for controlling a selected frame synchronization signal, which is an output signal of the first selection circuit, by an output of the timer circuit; and a control circuit which operates by the output clock and is phase-synchronized by an output of the control circuit. A counter circuit for generating a signal.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The system switching method of FIG. 1 includes a first selection circuit 12, a second selection circuit 13, a PLL circuit 14, and a counter circuit 15.
, A detection circuit 16, a timer circuit 17, and a control circuit 18.

The first selection circuit 12 outputs 0-system clocks 1 and 1
The system clock 2 is input, and the second selection circuit 13 receives the 0-system frame synchronization signal 10 and the 1-system frame synchronization signal 11 as inputs, and is selected by the switching signal 4.

[0010] The PLL circuit 14 follows the selection clock 3 which is an output signal of the first selection circuit 12, and outputs an output clock 5. The detection circuit 16 detects a change in the switching signal 4 and outputs a change point pulse.
It operates for a time longer than the maximum tracking time of the PLL circuit 14 by the change point pulse.

The control circuit 18 controls the selected frame synchronizing signal 7 which is the output signal of the second selection circuit 13 based on the output of the timer circuit 17. The counter circuit 15 is operated by the output clock 5, is phase-synchronized by the output of the control circuit 18, and generates an output frame synchronization signal 6. Note that when the phase synchronization is not performed, the counter circuit 15
An output frame synchronization signal 6 is output by self-running.

Next, the operation of this embodiment will be described.

In FIG. 1, when the switching signal 4 switches between the 0-system clock 1 and the 0-system frame synchronizing signal 10, and the 1-system clock 2 and the 1-system frame synchronizing signal 11, the PLL circuit performs the following operation as in the conventional system. Do
The output clock 5 varies in frequency. At this time, the detection circuit 16 detects the change of the switching signal 4 and
To work. The operation of the timer circuit 17 is controlled by the PLL circuit 14.
And a control signal 9 is output.

In accordance with the control signal 9, the control circuit 18 controls the counter circuit 15 so that the phase is not synchronized while the timer circuit 17 is operating. During the operation of the timer circuit 17, the counter circuit 15 runs free because the phase is not synchronized by the output of the control circuit 18, and outputs the output frame synchronization signal 6 without disturbing the cycle. With the termination of the timer circuit 17, the counter circuit 15 performs the phase synchronization operation again.

As described above, in this embodiment, the disturbance of the output frame synchronization signal after the system switching can be minimized by allowing the counter circuit to run while the output clock is fluctuating.

[0016]

As described above, according to the present invention, a detection circuit, a timer circuit, and a control circuit are provided in a circuit for selecting two redundant clocks and a frame synchronization signal, and the output clock fluctuates. Interval, counter circuit 15
Has the effect that disturbance of the output frame synchronization signal after system switching can be minimized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 1 0 system clock 2 1 system clock 3 selected clock 4 switching signal 5 output clock 6 output frame synchronization signal 7 selected frame synchronization signal 8 change point pulse 9 control signal 100 0 system frame synchronization signal 11 1 system frame synchronization signal 12 first Selection circuit 13 Second selection circuit 14 PLL circuit 15 Counter circuit 16 Detection circuit 17 Timer circuit 18 Control circuit

Claims (1)

(57) [Claims] 1. A first selection circuit which receives a first system clock and a second system clock as input, and is selected by a switching signal; a first system frame synchronization signal and a second system frame. A second selection circuit which receives a synchronization signal and is selected by a switching signal, a PLL circuit which follows a selection clock which is an output signal of the first selection circuit and generates an output clock, and a change in the switching signal And a detection circuit that outputs a change point pulse; a timer circuit that operates by the change point pulse; and a selected frame synchronization signal that is an output signal of the first selection circuit is controlled by an output of the timer circuit. A control circuit, and a counter circuit that operates by the output clock, is phase-synchronized by an output of the control circuit, and generates an output frame synchronization signal. System switching system.