JP2718746B2 - Terminal interface received data control circuit - Google Patents

Description

The present invention relates to a reception data control circuit of a terminal interface provided between a communication line and a terminal device, and a reception data control circuit of a terminal interface realizing various conditions in the terminal interface on a minimum scale. And control signals of a loop control signal looped back in the own device, a loop control signal looped out, an interface selection signal, a channel master selection signal, a transmission clock selection signal, and a reception clock selection signal, and a line. A control condition classification unit that receives a data signal of a received data signal, a transmitted data signal, and a loop data signal that is looped back through a loop bit buffer, and classifies each control signal by condition,
It is configured to include a data classification unit that selects one of the data signals corresponding to each output of the control condition classification unit, and a synthesis unit that synthesizes each output of the data classification unit.

The present invention relates to a reception data control circuit for a terminal interface provided between a communication line and a terminal device.

In recent years, data transmission has been performed via various transmission networks. In such a case, it is necessary for the device that interfaces the communication terminal device and the line to perform control according to various conditions such as the operating condition of the terminal device, the interface condition of the terminal, and the execution of a test when the line fails. In an interface that handles communication of a plurality of channels, it is necessary to provide a circuit for performing these controls for each channel.

It is desired to configure a circuit for outputting appropriate reception data to a terminal in response to those requirements with a minimum scale.

[Prior Art] FIG. 4 is a diagram of a communication connection system, FIG. 5 is an explanatory diagram of Conventional Example 1, and FIG. 6 is an explanatory diagram of Conventional Example 2.

In FIG. 4, a connection path is formed between the terminal 1 and the terminal 5 via the terminal interface 2, the communication network 3 and the terminal interface 4, and bidirectional data communication is performed. Communication between the terminal interface 2 and the terminal interface 4 is performed according to the same protocol (there are various systems such as CCITT V24, V28, X20, X21). Then, signals are transmitted and received between the terminal and the terminal interface by an interface such as RS232C. In this case, the transmitted / received signal includes transmission data (SD
Displayed as: Send Data), Received data (displayed as RD: Receive D)
ata), and the received data includes received data A (indicated by RD.A) received from the network side at the terminal interface 2 and received data B (RD.B transmitted from the terminal interface 2 and received by the terminal 1). ).

In addition, there is a clock signal A of the terminal 1 supplied to the terminal interface 2 and a clock signal A supplied from the network side (for example, an exchange) (received as a clock component in the data signal).

In this terminal interface, a connection (loop 2) for returning data received from the line as transmission data in order to perform a test from the network side when a failure occurs, or a terminal interface for performing a test on the own device side. (Loop 1) looping back transmission data or loop data (transmission data for a loop that does not pass through a buffer)
). Loop 1 and loop 2 are formed in the directions indicated by arrows in FIG.

The terminal interface shown in FIG. 4 is shown as performing one-channel communication. However, one terminal interface controls a plurality of channels of communication. In this case, each channel has an interface with each terminal ( This is called a channel interface).
The test function is controlled for each channel.

In such a terminal interface (or channel interface), Conventional Examples 1 and 2 are described as control circuits for outputting received data corresponding to any of various states such as a normal data communication state and a test state. This will be described with reference to FIGS. 5 and 6.

In the explanatory diagram of the conventional example 1 shown in FIG. 5, the configuration shown in A. is distinguished between an X-interface (X20, X21, etc.) and a V-interface (V-24, V-28, etc.) as communication network interfaces. There is no clock switching. In this conventional configuration, control is performed based on the V-interface standard,
The terminal interface is the master clock (4th
There is no clock switching function because it often operates with the clock A) in the figure.

Loop 1 and loop 2 are used as control signals of the received data control circuit shown in FIG. 5A. The output conditions of the received data Y output to the terminal are shown in FIG. 5B. In the figure, LP1 and LP2 represent Loop 1 and Loop 2, Mark represents "1" output, and Y represents an output of the reception data control circuit.

According to this, when the loopback test is not performed (loop
When both 1 and 2 are "0"), RD.A is output as output Y, and when the control signal of loop 1 (LP1) is "1", transmission data SD is obtained and loop 2 (LP2) is output. When the control signal is "1", Mark (= "1") is output.

As a modification of the configuration of the conventional example 1, the circuit of the conventional example 2 shown in FIG. 6 is used.

Even in the configuration of the conventional example 2, there is no distinction between the X-interface and the V-interface, and the control is performed substantially in accordance with the standard of the V-interface.

As shown in A of FIG. 6, a control signal ST1CK for selecting a transmission clock is added as control signals in addition to LP1 and LP2,
The loop data (indicated by LD) that has been looped back via the bit buffer is added as data. The loop data is data in which the transmission data SD is looped back via the buffer.

The output condition by the combination of the logic circuits of this configuration is shown in FIG. 6B. According to this, when the control inputs of LP1 and LP2 are "0", the received data RD is obtained at the output Y, Is "1", that is, when a loop test is performed on the network side, Mark (= "1") is output to the terminal side. The operation of outputting the transmission data SD when LP1 is "1" is the same as that of the first conventional example. Next, when the loop 1 is “1” and the transmission clock ST1CK is “1”, the loop data (indicated by LD) is output as the output Y.
Is output. In the loop data, the transmission data SD is looped back via the buffer. The mode in which ST1CK = “1” is input is called a pseudo ST1 mode, and appears to be different from the system clock when viewed from the network side.

[Problems to be Solved by the Invention] In the above-described conventional example 1 and conventional example 2, the operating conditions of the terminal and the interface conditions of the terminal (such as the V-interface and the X-interface) required in the terminal interface of the data communication are used. In addition, it is not possible to perform control based on various conditions at the time of test execution when a line fault occurs. If these controls cannot be performed, unnecessary information is treated as valid, and there is a problem that, for example, a normal state is determined to be abnormal in a test. Further, there is a problem that the scale of a circuit for configuring a control circuit for received data corresponding to these various conditions becomes large.

An object of the present invention is to provide a reception data control circuit of a terminal interface which realizes various conditions in the terminal interface on a minimum scale.

[Means for Solving the Problems] FIG. 1 is a basic configuration diagram of the present invention.

In FIG. 1, reference numeral 10 denotes a control condition classification unit, and 11 to 13 denote first control units.
A logical unit, a second logical unit, a third logical unit, 14 is a data classifying unit,
Reference numerals 15 to 17 indicate a logical product unit, and reference numeral 18 indicates a combining unit.

LP1 and LP2 are control signals for instructing loop 1 and loop 2, respectively. ST1 is a control signal for selecting a transmission clock.
1 is a control signal for selecting the receiving clock (generated on the terminal side),
X-in is a control signal for selecting the X-interface as the terminal interface (when "1", the X-interface,
When "0", the V-interface) and CHMAS are clock signal switching signals.
In the figure, a control signal for selecting a clock is shown, SD represents transmission data, RD.A represents reception data from a network, and LD represents loop data obtained by folding the transmission data SD via a bit buffer.

According to the present invention, various control signals in a terminal interface are classified into control conditions according to control, and data is controlled according to the classified conditions, thereby generating a received data output suitable for the control conditions.

[Operation] In the control condition classification unit 10, the first logic unit 11 outputs a control signal
LP1 and LP2 are input to perform logical processing, and the output is input to the data classification unit 14, and the logical product unit 15
Controls the output of RD.A. The second logic unit 12 performs a logical operation on the input control signal X-in and LP1 and LP2, and inputs the result to the synthesis unit 18. The third logic unit 13 receives the other control signals LP1 and LP2 together with the control signals ST1, CHMAS and RT1, performs a logical operation, and inputs a classification output 130 of one control condition to the data classification unit 14. Then, the output of the loop data LD is controlled, the classification output 131 of the other control condition is output to the data classification unit 14, and the output of the transmission data SD is controlled in the AND unit 17. The output of the data classification unit 14 is combined in the combining unit 18 to generate a received data output RD.B.

FIG. 2 is an explanatory view of an embodiment of the present invention.

FIG. 2A shows the configuration of the embodiment, and FIG. 2B shows the output conditions of the embodiment.

In the example configuration, 20, 21, 22, 23, 26, 27, 28 and 30
Is an AND circuit, 24 and 25 are NOR circuits, and 29 and 31 are OR circuits. The first logic unit 11 in FIG.
, The second logic unit 12 corresponds to a NOR circuit 25, the third logic unit 13 corresponds to a circuit including AND circuits 20 to 23, 26 and an OR circuit 29, respectively, and each logical product of the data classification unit 14 in FIG. Department
Reference numerals 15 to 17 correspond to the AND circuits 28, 27, and 30 in FIG.

The second embodiment is based on the configuration of the embodiment of the reception data control circuit shown in A.
The output conditions shown in Fig. B can be satisfied. In the output condition diagram, the output Y represents the received data RD.B, MARK means "1", and SPACE means "0". The display of "-" in the control signal column indicates that the signal is ignored (Don't care).

For example, when LP1 and LP2 are “0”, if no loop test is performed from either the terminal side or the network side, the NOR circuit
"1" output is generated from 24, and receive data RD.A is AND circuit
It is obtained as an output Y via a circuit 28 and an OR circuit 31.

When LP2 is “1” (in a state where a loop test is performed from the network side), the control signal X of the X-interface is “1”.
In the case of, “0” is generated from the NOR circuit 25 and the output Y
Obtained as That is, in the X interface,
By outputting a meaningless SPACE ("0") output to the terminal during the execution of the loop test to the network side, the terminal can ignore this. If MARK occurs at this time, the terminal processes it as meaningful data.

Similarly, when the control signal X is set to "0" to indicate that the terminal interface is V when LP2 is "1",
"1" is generated from the NOR circuit 25, and the output Y is output from the OR circuit 31.
Appears as. At this time, the terminal of the V interface processes the "1" (MARK) as meaningless. When the loop of the own device is performed (LP1 = “1”), if the control signal ST1CK for selecting the transmission clock is set to “0”, the control signal ST1CK passes through the AND circuit 26 and the OR circuit 29 regardless of other control signals. 1 "output is generated, and the transmission data SD is obtained at the output Y via the AND circuit 30 and the OR circuit 31.

Similarly, when performing a loop of the own device (LP1 = "1"),
Set the control signal ST1CK for selecting the transmission clock to “1” and set the control signal RT1CK for selecting the reception clock to channel master C.
When both the signals for selecting the clock of the HMAS are “0”, the loop data LD is obtained at the output Y through the AND circuits 20, 23, 27 and the OR circuit 31.

As described above, the selection of the loop data LD into which the buffer is inserted or the non-inserted transmission data SD is automatically performed by combining the control signals ST1CK, RT1CK, and CHMAS.

 The same applies to other output conditions.

FIG. 3 is a block diagram showing the circuit of the embodiment as an IC circuit.

In FIG. 3, reference numeral 40 denotes an IC circuit including a two-input NOR circuit, 41 denotes an IC circuit including a plurality of inverters, 42 denotes an IC circuit including a plurality of two-input AND circuits, and 43 denotes a two-input AND circuit. IC circuit with multiple components, 44 is a 3-input NOR circuit, 45
Is an IC circuit having a plurality of two-input OR circuits. The circuit of FIG. 3 performs the same logical operation as the circuit of FIG. 2, and the internal configuration of the IC circuit is the same as that of FIG.

The configuration shown in FIG. 3 can be included as a part of a circuit in an LSI circuit together with another control circuit (such as a transmission control circuit) of the terminal interface. Also, when connected to a line by multiple channels,
The reception data control circuit corresponding to each channel can be realized by one LSI circuit.

[Effects of the Invention] According to the present invention, the receiving area can be reduced by incorporating the reception data control circuit as a part of the LSI circuit of the terminal interface. In addition, an automatic buffer insertion function for each clock when Loop 1 and Loop 2 are executed can be realized, and interface-specific control can be performed when Loop 2 is executed.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is an explanatory diagram of an embodiment of the present invention, FIG. 3 is a block configuration diagram in which the circuit of the embodiment is formed into an IC circuit, FIG. Fig. 5 shows Conventional Example 1
FIG. 6 is an explanatory view of Conventional Example 2. In FIG. 1, 10: control condition classifying unit 11-13: first logical unit to third logical unit 14: data classifying unit 15-17: logical product unit 18: combining unit

Claims (1)

(57) [Claims] 1. A receiving data control circuit of a terminal interface provided between a communication line and a terminal device, comprising: a loop control signal looping back in the own device; a loop control signal looping outward; an interface selection signal; a channel master selection signal; Each control signal of a clock selection signal and a reception clock selection signal, and each data signal of a reception data signal from a line, a transmission data signal, and a loop data signal looping back through a loop bit buffer are input. Control condition classifier that classifies by condition (10)
A data classifying unit (14) for selecting one of the data signals corresponding to each output of the control condition classifying unit; and a synthesizing unit (18) for synthesizing each output of the data classifying unit. Characteristic reception data control circuit of terminal interface.