JP2719466B2 - Imaging system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging system for displaying a plurality of images on one screen by superimposing a plurality of image signals.

[0002]

2. Description of the Related Art FIG. 4 shows a first video signal serving as a main screen.
To superimpose the second video signal, which will be the sub-screen, on the
FIG. 3 is a block diagram illustrating a configuration of a data unit. First video
Signal X_(t)Is a synchronization signal according to the specified television system
Can also be obtained from a TV camera operating on CS1
Therefore, the synchronization signal C generated inside the television camera
A video component is superimposed on S1. In addition, the second video signal
No.Y _(t)Similarly, based on a predetermined synchronization signal CS2,
Obtained from a working TV camera. Like this
Two TV cameras, each operating at its own timing
Video signal X output from_(t), Y_(t)Is vertical scanning and water
Since the flat scan timings do not match, the center unit
In the unit 10, the video signal Y_(t)Each timing
Video signal X_(t)Video signal X_(t)Video signal
No.Y_(t)Are constructed. Note that the video signal Y
_(t)Use an image sensor with a reduced number of pixels,
Image components are compressed by thinning out image components at regular intervals
And a specific period within the vertical scanning period and the horizontal scanning period.
Video components are superimposed only during the period.

The video signal Y _(t) input to the center unit 10 is temporarily stored in the field memory 12 by the memory control circuit 11 for each screen, and then read out from the field memory 12 at a predetermined timing. The timing of this reading is set based on the synchronization signal extracted from the video signal X _(t) by the synchronization separation circuit 13. Therefore, the timing of the vertical scanning and the horizontal scanning of the video signal Y _(t) coincides with the video signal X _(t) . Video signal Y timing of the video signal X _(t) and the vertical and horizontal scanning are matched _(t) is input together with the video signal X _(t) to the signal combining circuit 14. The signal synthesizing circuit 14 selects and outputs the video signal X _(t) or the video signal Y _(t) in accordance with the switching pulse SP supplied from the switching control circuit 15, thereby outputting the video signal X _(t) and the video signal Y _{(t). (t)} and a third video signal Z _(t) combined with the third video signal. That is, the image signal an image signal X _(t) in the period in which the video component of the video signal Y _(t) is present Y
by replacing _{(t), the} configured to obtain the third image signal Z for displaying the image of the image signal Y _(t) to a portion of the image of the image signal X _{(t) (t).}

For example, as shown in FIG. 5, when a sub-screen having a size of 1 / n is superimposed on the main screen in the vertical and horizontal directions, each 1 / n period of the vertical scanning period and the horizontal scanning period is used. Then, the video signal Y _{( t)} is replaced with the video signal X _(t) . As shown in FIG. 6, the switching pulse SP that determines the timing of replacing the video signal X _(t) with the video signal Y _(t) is 1 / n of the vertical scanning period (1V) (V / n).
At this time, the signal synthesizing circuit 14 selects the video signal Y _(t) side during this period, and the horizontal scanning period (1
It becomes L level during 1 / n period (H / n) of H) and causes the signal synthesizing circuit 14 to select the video signal Y _(t) side. In the switching pulse SP, the components of the vertical scanning cycle and the horizontal scanning cycle are created from the output of the counter that creates the vertical synchronizing signal VS and the horizontal synchronizing signal HS. Supplied to Therefore, the video signal X _(t) is changed to the video signal Y ₍ during the period when the switching pulse SP in the vertical scanning period is at the L level and during the period when the switching pulse SP in the horizontal scanning period is at the L level. _t)
Therefore, a sub-screen is displayed on a part of the main screen, and two screens can be simultaneously displayed on one monitor screen.

However, in the center unit 10 described above, since the video signal X _(t) needs to be temporarily stored in the field memory 12, the video signal Y _(t) is added to the large-scale field memory 12. An A / D converter for converting the digital value and a D / A converter for converting the digital value into the video signal Y _(t) again are required. For this reason, the circuit configuration of the center unit 10 becomes large, which causes an increase in the cost of the entire system.

[0006]

Therefore, the video signal Y
_(t) is operated in accordance with the synchronization signal separated from the video signal X _(t) to synchronize the video signal Y _(t) with the video signal X _(t) in advance, thereby obtaining the video signal X _(t) The present applicant has proposed a method of synthesizing the image signal Y and the video signal Y _{(t) as} it is in Japanese Patent Application Nos. 2-167634 and 2-231680. In these methods, a synchronizing signal component is extracted from a video signal X _(t) constituting a main screen to generate a synchronizing signal CS, and the synchronizing signal CS is supplied to a television camera for obtaining a sub-screen, so that the TV The operation of the camera is synchronized with the video signal X _(t) , and the video signal Y _(t) forming the sub-screen is synchronized in advance with the video signal X _(t) .

However, when the synchronizing signal CS of the video signal X _(t) is supplied to the television camera for obtaining the sub-screen, a communication line for transmitting the video signal Y _(t) from the television camera for the sub-screen to the center unit. In addition, a communication line for transmitting the synchronization signal CS from the center unit to the sub-screen TV camera is required, and the number of communication lines between the TV camera and the center unit increases. Despite the simplification, sufficient cost reduction cannot be achieved. In particular, in a monitoring system or the like in which a plurality of television cameras are connected to a center unit, an increase in the number of communication lines causes a significant increase in cost. Therefore, simplification of the circuit lines and simplification of the communication lines are desired. Also, a method of transmitting the video signal Y _(t) and the synchronizing signal CS by superimposing them on the same communication line is described below.
Since the impedance of the side on which the video signal Y _(t) is superimposed (the television camera for the sub-screen) and the side on which the synchronizing signal CS is superimposed (the center unit) are not matched, attenuation occurs in the communication line. It is not suitable for an imaging system in which a television camera and a center unit are connected by a long communication line.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized by a first video signal for outputting a first video signal according to a predetermined television system. An imaging unit for separating a vertical synchronizing component and a horizontal synchronizing component from the first video signal, obtaining a synchronizing signal according to the television system, sending out the synchronizing signal to a communication line, and superimposing the second video signal on the communication line Of the first video signal, and replaces the video component with a part of the first video signal at a timing based on the synchronization signal, and replaces the video by the second video signal with a part of the video by the first video signal. A center unit that outputs a third video signal to be displayed; and a synchronization unit that captures the synchronization signal from the communication line, and adds a vertical synchronization component and a horizontal synchronization component of the synchronization signal to a vertical synchronization component of the image sensor. And a second imaging unit that outputs a second video signal synchronized with the synchronization signal by matching the timings of scanning and horizontal scanning. The center unit and the second imaging unit Another object of the present invention is to provide a drive circuit for superimposing the two video signals on the communication line via the same resistance.

[0009]

According to the present invention, a synchronizing signal is superimposed on a communication line connecting the second imaging unit and the center unit via a resistor from the driving circuit on the center unit side, and the center circuit is driven from the driving circuit on the imaging unit side to the center. By superimposing the second video signal via a resistor equal to the resistance of the unit side, the video signal and the synchronization signal are transmitted through a single communication line, and simultaneously the second imaging unit side and the center unit side Are matched. Therefore, the video signal and the synchronization signal can be transmitted by a single communication line without attenuating.

[0010]

FIG. 1 is a circuit diagram showing the configuration of an imaging system according to the present invention. Here, the center unit 20 to which the first video signal X _(t) and the second video signal Y _(t) are input is used.
And an imaging unit 30 that outputs a video signal Y _(t) . An imaging unit that outputs a first video signal X _(t) is omitted because there is no difference from a known imaging unit. The signal source for obtaining the first video signal X _(t) is not limited to an imaging unit such as a television camera, but may be recorded on a receiving device or a recording medium that receives a television broadcast and obtains the video signal X _(t). The read signal is read out and the video signal X _(t)
The same applies to a reproducing apparatus for reproducing.

The first video signal X _(t) input to the center unit 20 constitutes a main screen, is first captured by the clamp circuit 21, and is fixed at a desired level every blanking period. Thus, a reference level is set. The input side of the clamp circuit 21 is connected in parallel with a resistor R1 for impedance matching with an imaging unit that outputs a video signal X _(t) . The synchronization separation circuit 22 extracts only the synchronization component from the output of the clamp circuit 21 and inputs the same to the phase lock loop 23. The phase lock loop 23 operates using the output of the sync separation circuit 22 as a reference signal, and outputs a horizontal sync signal HS of a horizontal scanning cycle synchronized with the video signal X _(t) . Synchronous signal generation circuit 24
Counts the horizontal synchronizing signal from the phase lock loop 23, obtains a vertical synchronizing signal VS of a vertical scanning cycle from the count value, and obtains the vertical synchronizing signal VS and the horizontal synchronizing signal HS.
And a synchronizing signal CS is created. Then, the synchronization signal CS is sent from the driver 25 to the communication line 40 via the resistor R2.

Also, the communication unit 40 is connected to the center unit.
20 is input to the second video signal Y _(t)Shows the sub screen
The communication unit is constituted by an imaging unit 30 described later.
Video signal X_(t)Like, clan
Is taken into the loop circuit 26. This clamp circuit 26
Video signal X_(t)The same structure as the clamp circuit 21
The video signal Y every blanking period._(t)
Is fixed to a desired level to set a reference level. What
Contact, video signal Y_(t)Is a synchronization signal CS, that is, a video signal X
_(t)At the same time as the video signal Y shown in FIG._(t)
In the same way as in
Video component is compressed to 1 / n in a specific period
Only the video component is superimposed. And clamp
The output of the circuit 21 and the output of the clamp
And input from the switching control circuit 28.
Video signal X at a timing according to the switching pulse SP_(t)of
Partly video signal Y_(t)Is replaced by Here, switching
Switching operation of the switching control circuit 28 by the pulse SP
The timing is the same as that shown in FIG.
Y_(t)During the period when the video component of
Correlated. Therefore, the video signal X_(t)Part of the video
Signal Y_(t)And the video signal X_(t)Of the picture by
Part of video signal Y_(t)3rd movie displaying video by
Image signal Z_(t)Are synthesized. And this video signal Z_(t)
Is output from the driver 29 via the resistor R3. When
At this time, the communication line 40 includes the center unit 20 itself.
Output the synchronization signal CS_(t)Superimposed with
Video signal Y_(t)Vertical and horizontal scanning
Since the timing matches the synchronization signal CS, the synchronization signal
The effect of signal CS is video signal Y_(t)It does not extend to.

On the other hand, from the communication line 40 to the imaging unit 3
The synchronization signal CS taken into 0 is input to the clamp circuit 31 and is fixed to a desired level every blanking period to set a reference level. Actually, the video signal Y _(t) output from the imaging unit 30 itself is superimposed on the communication line 40 together with the synchronization signal CS, and a signal including a video component and a synchronization component is obtained from the clamp circuit 31. Become. Therefore, the sync separation circuit 32 removes the video component from the output of the clamp circuit 31 and supplies only the sync component to the phase lock loop 33, similarly to the sync separation circuit 22 of the center unit 20. The phase lock loop 33 generates a horizontal synchronizing signal HS of a horizontal scanning cycle and supplies it to a synchronizing signal generating circuit 34. The synchronizing signal generating circuit 34 generates a horizontal synchronizing signal VS of a vertical scanning cycle from the horizontal synchronizing signal HD. I do. A drive circuit 36 for driving the CCD image sensor 35 receives a vertical synchronization signal VS from the synchronization signal generation circuit 34.
And a horizontal synchronizing signal HD, and generates a driving clock according to these synchronizing signals. Accordingly, the CCD image sensor 35 synchronizes the timing of the vertical scanning and the horizontal scanning with the vertical synchronization signal VS and the horizontal synchronization signal HS, and outputs the synchronization signal C
A video signal Y _(t) synchronized with S is generated. The video signal Y _(t) is subjected to processing such as sampling and level correction in the signal processing circuit 37 and then sent out from the driver 38 to the communication line 40 via the resistor R4. here,
The video signal Y _(t) sent from the driver 38 to the communication line 40 is different from the video signal X _(t) and includes only a video component without a synchronization component.

By the way, the resistors R2 to R4 connected in series to the output side of each video signal and the synchronizing signal CS are set to the same resistance value, and each of the drivers 25, 29,
38, the output impedance of each of the resistors R2 to R
4 is set so as to correspond to the resistance value. The resistance value is set to 75Ω for a general communication line using a coaxial cable. Therefore, the center unit 20
And the input / output impedance of the imaging unit 30 match, so that there is no attenuation in the communication line 40, and the signal level of the communication line 40 is stabilized. When the signal level of the communication line 40 is stabilized, the center unit 20 and the imaging unit 30 can be handled by a clamp circuit having a small clamping ability, so that the configurations of the clamp circuits 21, 26, and 31 can be simplified.

FIG. 2 is a circuit diagram showing an example of a clamp circuit having a simplified circuit configuration. The clamp circuit is configured to detect a blanking period of an input video signal and generate a clamp pulse inside the circuit. Input npn transistor t for receiving video signal at base
1 has a collector connected to a power supply and an emitter connected to a resistor r1
Grounded. One end of a potential fixing capacitor c1 is connected to the emitter of the npn transistor t1. The output pnp transistor t2 has the base connected to the other end of the capacitor c1 and the emitter connected to the resistor r2.
, The collector is grounded, and the collector is connected to the base of an output npn transistor t3 having characteristics complementary to the pnp transistor t2. The npn transistor t3 has a collector connected to a power supply, an emitter grounded via a resistor r3, and outputs a video signal having a reference level set from the emitter. The collector is a capacitor c
The switch npn transistor t4 connected to the other end of 1 has a base supplied with a clamp pulse, and has an emitter grounded via a capacitor c2. And npn
A predetermined potential for determining a clamp level is applied to the emitter of the transistor t4 from a variable resistor vr that divides a power supply potential.

The collector of the npn transistor t5 which receives the potential fluctuation on the output side of the capacitor c1 at the base is connected to the power supply, the emitter is grounded via the resistor r4, and one end of the capacitor c3 is connected to this emitter. The other end of the capacitor c3 is connected between the resistors r5 and r6 connected in series between the power supply ground and further connected to the base of the pnp transistor t6. The pnp transistor t6 is configured so that the collector is electrically grounded, the emitter is connected to the power supply via the resistor r7, and the emitter outputs a clamp pulse. General video signals are
As shown in FIG. 3, since the video component is superimposed on the plus side with respect to the reference level, and the synchronization component is superimposed on the minus side, the level is larger or smaller than the level slightly lower than the reference level indicated by the broken line. Is determined, the synchronization component can be separated. Therefore, by setting the resistance values of the resistors r5 and r6, the signal determination level is set to a value slightly lower than the reference level of the video signal, and the blanking pulse corresponding to the blanking period of the video signal is set to the pnp transistor t.
6 are output from the emitters. Since this blanking pulse is accompanied by the delay time of the circuit, only the change point is taken out by the resistor r8 and the capacitor c4, the clamp timing is set at the fall timing, and the gate of the switch npn transistor t4 is set. Supplied to

According to such a clamp circuit, the circuit itself detects the blanking period of the input video signal,
Since the operation is performed to set the reference level of the video signal at that timing, there is no need to supply a clamp pulse from outside the circuit.

[0018]

According to the present invention, it is possible to realize an imaging system for displaying a plurality of images on one screen with a very simple circuit configuration, and at the same time, to prevent signal attenuation on a communication line. The level of the signal on the communication line can be stabilized. Further, since the signal level on the communication line is stabilized, the configuration of the clamp circuit that captures a signal from the communication line can be simplified, so that the circuit configuration of each part of the system can be reduced, and further cost reduction can be expected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an imaging system of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a clamp circuit.

FIG. 3 is a waveform diagram illustrating an operation of the clamp circuit.

FIG. 4 is a block diagram illustrating a configuration of a center unit of a conventional imaging system.

FIG. 5 is a schematic diagram of a reproduction screen.

FIG. 6 is a timing chart showing the operation of the center unit.

[Explanation of symbols]

 10, 20 Center unit 11 Memory control circuit 12 Field memory 13, 22, 32 Synchronization separation circuit 14, 27 Signal synthesis circuit 15, 28 Switching control circuit 21, 26, 31 Clamp circuit 23, 33 Phase lock loop 24, 34 Synchronization signal Generation circuit 25, 29, 38 Driver 30 Imaging unit 35 CCD image sensor 36 Drive circuit 37 Signal processing circuit

Claims (3)

(57) [Claims] A communication line for transmitting a video signal bidirectionally.
And outputs a first video signal including a video component and a synchronization component
And a video source connected to the communication line.
An imaging unit that outputs a second video signal including
Connected to the signal source and the communication line;
The first video signal based on the synchronization component of the video signal
In addition to generating a synchronized signal, the first video signal
Part of the signal is replaced with the second video signal and the first video signal is replaced.
The second video signal is provided in a partial area of the screen corresponding to the image signal.
For generating a third video signal for displaying a screen corresponding to
And a center unit, wherein the center unit is
Communication of the synchronization signal via a resistor having a constant resistance value
From the driver circuit that outputs to the line and the communication line
The reference level is clamped to a predetermined value and the second video signal is
Includes a clamp circuit that captures the signal and follows the synchronization signal
At the timing, the first video signal or the second video signal
The switching of the image signal is controlled, and the imaging unit
Is used to clamp the reference level from the communication line to a predetermined value.
And a clamp circuit for taking in the synchronization signal
2 through a resistor having a constant resistance value.
Including a driver circuit that outputs to the communication line,
The image sensor is driven at the timing according to the signal
Imaging system. 2. A clamp circuit for the center unit,
The clamp circuit of the imaging unit is connected to the communication line.
In response to the output synchronization signal, the power of the communication line is
The position is clamped to a predetermined potential.
2. The imaging system according to 1. 3. A plurality of image pickup units for taking in the synchronizing signal from the communication line and sending out a video signal synchronized with the synchronizing signal to the communication line, wherein each of the images from the plurality of image pick-up units is sent to the center unit. The imaging system according to claim 1, wherein a signal is selectively replaced with a part of the first video signal.