JP2719681B2 - Pseudo-random pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial applications"   This invention is 2ⁿ-1 bit period, the same pattern is
A pseudo-random generator that generates repeated pseudo-random patterns at high speed
Related to a pseudo-random pattern generator. "Conventional technology"   In the field of digital communications, high-speed simulation of 3 GHz to 10 GHz
Although a similar random pattern generator is required,
The register system is technically too difficult.   Fig. 5 shows a memo that can be realized only with relatively simple high-speed technology.
Of a conventional pseudo-random pattern generator using the re-method
It is a figure showing an example.   This conventional example is 2^Four-1 = 15-bit basic random pattern
For example, "100110101111000" is continuously repeated
To generate a pseudo-random pattern
Pattern is a pattern in which one word consists of 4 bits
A description will be given using an example stored in the memory 11.   15-bit basic random pattern `` 10011010111100
0 ”is divided into partial patterns in units of 4 bits from the beginning.
Address 0, the 4-bit partial pattern "1001"
Partial pattern "1010" at address 1 Partial pattern at address 2
"1111", and at the end of address 3 is the end of a 15-bit pattern
Partial pattern "000" for 3 bits at the end and the next 15
Bit length basic random pattern "100110101111000"
4 with the pattern "1" for the first one bit of
The bit partial pattern “0001” is stored. 4 or more
Subsequent partial patterns "0011", "0101", "1110"
Is stored at address 7, the end of the basic random pattern.
Partial pattern "00" for 2 bits at end and 3rd basic
Partial pattern for the first two bits of the random pattern
The partial pattern “0010” that is combined with “10” is stored.
You. Similarly, a basic random pattern of 15 bits length
Is divided into 4-bit partial patterns and stored.
In the ground, the last 4 bits of the fourth basic random pattern
The partial pattern "1000" of the division is stored.   When the clock 13 is supplied to the address counter 12,
Address counter that counts clock 13
The count value of the data 12 is stored in the address decoder 14 of the pattern memory 11.
Parallel-serial from the decoded memory address
The partial pattern is converted to 4-bit parallel data to the conversion circuit 15.
Supplied. The parallel-to-serial conversion circuit 15
Is converted to serial data and pseudo-random
Output sequentially as a pattern.   The count value of the address counter 12 is changed from 0 to 3 by the clock 13.
The pattern memory 11 sequentially stores partial
Turns “1001”, “1010”, “1111”, and “0001” read
These four partial patterns are stacked and serially
Output as the first basic random pattern.
`` 100110101111000 '' and the following basic random pattern
The first bit "1" is output. Continue to address 4
Subsequent patterns "0011", "0101" ... are sequentially read out
So, in addition to the “1” left before, the basic random pattern
Pseudo-random with repeated "100110101111000"
A pattern is generated.   On the other hand, the last address of the pattern memory 11 is stored in the register 16.
"14" is a binary code "0011" as a stop code indicating
10 ”. This setting value “14” and the address
The count value of the counter 12 is supplied to the coincidence detection circuit 17 shown in FIG.
When the count value matches the set value “14”,
The output circuit 17 outputs a match detection signal, and the AND gate 18
be opened. Clock 13 after this match is detected
18 and the address count through OR gate 19.
The data is supplied to the data 12 to clear the count value. Therefore, address 14
When the partial pattern "1000" is read,
The reading operation of the partial pattern starting from the beginning is continued.   Thus, it is stored from address 0 to address 14.
Cyclically read four 15-bit basic random patterns
The same random pattern every 15 bits.
Can generate a pseudo-random pattern that is returned
You. "Problems to be solved by the invention"   When the basic random pattern has been read,
Does not match the end of the read partial pattern.
For example, as shown in the example of FIG. 5, addresses 3, 7,...
End of basic random pattern stored at address 14
And the end of the partial pattern stored at those addresses
Does not match and the fourth basic random pattern is read out.
For the first time at the address 14
The end of the basic random pattern matches.   As a long pseudo-random pattern (2^{twenty three}-1) bit
There can be a reference pattern of length, but with such a length,
Actually generate repeated pseudo-random patterns
In (2^{twenty three}-1) × 4 = 8388607 × 4 This requires a 4 × 8 Mbit memory.   Also, such a large capacity memory has a long read cycle.
The number of stacking stages must be 256, for example.
Must. Therefore, 8M bits x 256 bits = 2G bits
Memory with a capacity of
It is difficult to realize. "Means to solve the problem"   In the present invention, (2ⁿ-1) Pseudo lattice with bit as period
Random pattern (n is an integer of 3 or more)^mBit (m =
Positive integer, n> m)ⁿ/ 2^m= 2^nmPieces
Turns and their 2^nm(2ⁿ-1) bit
Continuous in a cycle 2^mThe bit pattern is 2^{m + 1}Bit
These patterns are stored in a pattern memory that is one word.
The turns are read cyclically.   That is, the clock is counted and the address is given to the memory.
Two^nmHexadecimal address counter and read from pattern memory
Of the input partial pattern in parallel for each clock
Register and, after its parallel input, a shift register
Means for shifting one bit, and the shifted partial pattern
Means for writing the sequence to the read memory address again, and
After writing data, the clock
2 from one end^mA latch where bits are latched, and
Sending the latched pattern as a serial pattern
Column-to-serial converter and clock counting 2ⁿHex counter
And part 2ⁿOutput from memory by the output of the binary counter
Turn, input pattern to memory 2^mSwitch bit by bit
Means for controlling the pattern memory.   2 moreⁿThe address register by the output of the binary counter
Go one step further and transfer the memory read pattern to the shift register
Input in parallel, shift register by 1 by 1 bit shift means
Bit shift and write the shifted pattern to memory
The pattern generation control by means of
It is configured to be. "Action of the invention"   According to the configuration of the present invention, the data read from the pattern memory is read.
The partial pattern that has been shifted
The cyclically shifted random pattern is the pattern
It is stored again at the address read from the memory.
Therefore, the next partial pattern to be read is the pattern memory
Is always well separated. "Example"   FIG. 1 shows an embodiment of the pseudo-random pattern generator of the present invention.
It is a figure showing an example. According to the configuration of the present invention, 2ⁿ-1
The basic random pattern that is repeated periodically every time is 2^m
Every 2^nmAnd the basic lane from those breaks
Each random pattern is 2 long^{m + 1}Bit putter
And stored in the pattern memory. In this example
Corresponds to the conventional example shown in FIG. 5 where n = 4 and m = 2.
Let me 2^Four-1, that is, a 15-bit basic random pattern `` 100110101111000 '' Is generated as a pseudo-random pattern is repeated
It is shown in   According to the configuration of the present invention, pseudo-random pattern generation
The device is composed of a pattern generator 21 and its controller 22.
In this embodiment, a basic random pattern having a length of 15 bits is used.
Pseudo random patterns are generated by repeatedly outputting
This is the case where the
In the turn memory 23, one word is composed of 8 bits.
4-word random access memory (RAM) is used
You.   The pattern generating section 21 stores an 8-bit image in which a partial pattern is stored.
Pattern × 23 words, pattern memory 23, pattern memory 23
9-stage shift register 2 supplied with 8-bit output
4. A part of the parallel output of the shift register 24 is supplied.
Latch 25 consisting of two registers, supplied by the output of latch 25
Parallel-to-serial conversion circuit 26 and pattern memory 23
8 stations connecting the input and output terminals of the shift register 24
It is composed of switches 27 and 28.   Outputs D0, D of the first, second to eighth bits of the pattern memory 23
1 to D7 are the first, second to eighth switches 27 of the read switch 27.
A, 27B to 27H are supplied to one input contact S1 respectively.
Both output the fifth, sixth to eighth bits of the pattern memory 23
D4, D5 to D7 are the first, second to fourth switches 27A, 27B to 27D, respectively.
Connected to the other input contact S2 and
The outputs D0, D1 to D3 of the first, second to fourth bits are the fifth, sixth to sixth
8 Switches 27E, 27F to 27H are connected to the other input contact S2.
It is. These read switches 27A, 27B to 27H are connected to the control terminal 29.
Is uniformly controlled by the selection signal supplied to
Either contact S1 or the signal supplied to the other input contact S2
From the respective output terminals Q to the second,
Configuration to supply to third to ninth shift stages 24B, 24C to 24I
Is done.   First, second to fourth shift stages 24A, 24B of shift register 24
To 24D are the first, second to fourth registers 25A, 2 of the latch 25.
5B to 25D, and further, the first, second to fourth registers 25A, 2
The outputs of 5B to 25D are supplied to a parallel-serial conversion circuit 26.
The parallel-serial conversion circuit 26 converts the supplied parallel data into serial data.
Data and output them sequentially as a pseudo-random pattern.
You.   The outputs of the second, third to ninth shift stages 24B, 24C to 24I are
Eleventh, twelfth to eighteenth switches 28A and 28B of the write switch 28
To 28H, and the sixth and
The outputs of the seventh to ninth shift stages 24F and 24G to 24I are the eleventh, twelfth to first
4 Supply the power to the other input contact S2 of the switches 28A, 28B to 28D.
And the outputs of the second, third to fifth shift stages 24B, 24C to 24E are the first.
5, the other input contact S2 of the 16th to 18th switches 28E and 28F to 28H
Respectively. These switches 28A, 28B-28H
Is uniformly controlled by a selection signal supplied to the control terminal 29,
Supplied to one input contact S1 or the other input contact S2
Output one of the signals from each output terminal Q,
Write data for the first, second to eighth bits of the
Data D0, D1 to D7.   Furthermore, the output of the second shift stage 24B is the ninth shift stage 24I
Serial data input S_inSupplied to   Start signal 31 and clock 32 are supplied to control unit 22
Various control signals for controlling the pattern generator 21
Is made.   The clock 32 is a first flip-flop circuit 33 of JK type.
Trigger end 33T, first and second AND circuits 34, 35 and first OR
The signal is supplied to a circuit 36. J of the first flip-flop circuit 33,
The K terminal supplies an “H” level signal and an “L” level signal, respectively.
At the falling edge of the signal supplied to the trigger end T,
The signal at the output terminal Q changes to "H" level. This first file
The output of the flip-flop circuit 33 is used as a gate control signal
One input terminal of the first, second, third, and fourth AND circuits 34, 35, 37, 38
A, and this gate control signal is an “H” level signal
In the state of the open signal, these AND circuits 34, 35, 3
7,38 gates are opened and each supply to the other input B
The control signal is output from each output terminal C. Follow
When the gate is opened, the other end 34B of the first AND circuit 34
Clock 32 supplied to the first AND circuit 34
Then, it is supplied to the counter 41 via the second OR circuit 39.   Counter 41 is 2ⁿHexadecimal counter. Address counsel
The maximum count value is 2 for the basic random pattern^mBit by bit
It is made equal to the number of sub-patterns to be created.   In this example, 2ⁿHex counter, in this case 2^FourSugi Coun
The lower two digits of the address 41 are also used as the address counter 42,
The 2-digit count outputs A1 and A2 are used as pattern signals as address signals.
This is supplied to an address decoder 44 in the memory 23. Best
The output of the digit A4 is supplied to the first pulse generator 45, and the first pulse
The output of the pulse generator 45 is further supplied to a second pulse generator 46.
And is supplied to the counter 41 through the second OR circuit 39.
It is. The output pulse of the second pulse generator 46 and the pulse
The lock 32 is connected to the first delay circuit 47 through the first OR circuit 36.
And its delayed output is switched through a third AND circuit 37.
The shift register 24 is supplied as a read pulse 51. So
Read pulse 51 further delays τ2 by the second delay circuit 48.
Received as a left shift pulse 52 through a fourth AND circuit
Supplied to the shift register 24, and further to its left shift pulse
52 is supplied as a write pulse 53 through a third delay circuit 49.
It is supplied to the turn memory 23.   Also, 2^FourA4 of the binary counter 41 is the second flip-flop.
Is supplied to the loop circuit 43. Of the second flip-flop circuit 43
The “H” level signal is given to the J and K terminals,
Each time a power signal is supplied, an output signal from its output terminal Q
Is inverted. The second flip-flop circuit
The output of 43 is the selection signal of the contact S1 or S2 of the switches 27 and 28
Control terminals 29 of the two 8-unit switches 27 and 28
Supplied to   In the above configuration, in this embodiment, n = 4, m = 2
And the 15-bit basic random pattern is 2^Two= 4 bits
2 separated from each other by 4 bits
^{2 + 1}= 2 for 8 bits^4-2= 4 partial patterns putter
Are stored in order from address 0 to address 3 in memory 23
You. That is, the code is stored in the pattern memory 23 shown in FIG.
As shown by "0" and "1", the reference run is at address 0.
The first 8 bits of the dumb pattern "100110101111000"
Partial pattern "10011010", address 1 is the first break
8-bit partial pattern "1010
1111 ”, starting at the ninth bit, which is the second
7 bits up to the 15th bit and the next basic random pattern
8-bit partial pattern including the first bit of
"11110001" and at address 3 is the third break
3 bits from the 13th bit to the 15th bit and the following basics
5 from the first bit to the fifth bit of the random pattern
8-bit partial pattern "00010011" combining bits
Are respectively stored.   FIG. 2 shows the data stored in the pattern memory 23.
And read the same pattern every 15 bits
Generates a pseudo-random pattern that repeats periodically
FIG. 6 is a waveform diagram of each part of the control unit 22 showing an operation example for causing
You. Waveform A is a waveform diagram showing the start signal 31, and waveform B is
6 is a waveform diagram showing a lock 32. FIG. FIG. 3 shows the pattern
Storage status of partial patterns stored in memory 23
Changes during the control process of pseudorandom pattern generation.
FIG. In this transition diagram, the sun in FIG.
Pull clock (waveform D-, ..., ',' ...
…), Classified into ……, ',' …… columns
Of the partial pattern in the pattern memory 23 at that time.
The storage state and the read pattern are shown. Initial column
Is the part stored in the random pattern 23 before the operation starts.
Indicates the storage status of the minute pattern.
`` 0 '', `` 10101111 '' at address 1, `` 11110001 '' at address 2, 3
“00010011” is stored in the address. Each part putter
Sign before Sets the break position of every 4 bits of the basic random pattern
Show. This break position Moves cyclically to the left as control proceeds.
For example, in the column showing the state after one clock control,
The partial pattern of the ground is cyclically shifted left by one bit,
The break position has moved between the 7th and 8th bits.
Is shown. Hereafter, as shown in each column,
Shows that they are going to receive left shift rotation sequentially
It is. The code at addresses 2 and 3 in the initial column is 15 bits long
Indicates the end position of the basic random pattern. Also, each column
The symbol ▲ written in
Indicates the rest position. Note that the 4 bits shown in the upper position in each column
Pattern is then latched into latch 25
This shows a 4-bit partial pattern.   When the start signal 31 changes to the “H” level signal (wave
A-), first and second flip-flop circuits 33 and 43, and
The counter 41 is released from the reset state and becomes operable.
You. Address counter 42 followed by a quaternary counter
The count values are both zero. The next clock 32 (waveform B
The gate of the first flip-flop circuit 33 in synchronization with-)
When the control signal is an open signal (waveform C-), the first, second,
4 AND circuits 34, 35, 37, 38 are supplied.   In this embodiment, a hexadecimal counter 41 is used.
The lower two digit count output is a quaternary address counter 42.
This is the case when used. Clock 32 is the first AND circuit
34, but the clock 32 shown in waveform B-
The gate is not open at the time
And the clock 32 after the waveform B-
A sample clock 54 (waveform D-) passes through the circuit 34.
Is supplied to the quaternary address counter 42. This sample
The clock 54 (waveform D) is counted by the address counter 42.
And the quaternary count value is output as an address signal.
(Waveform E). The count value output is the address of pattern memory 23
The signal is supplied to the decoder 44, and the
The read address of the memory 23 is 0, 1, 2, 3 as shown in the waveform E.
Addresses and also cyclically specified as 0,1,2 ....   The shift register 24 includes nine shift stages 24A, 24B to 24I.
Switching means for those shift stages 24A, 24B to 24I
27, 8-bit outputs D0, D1 to D of the pattern memory 23
7 is supplied. Further, the signal supplied to the first AND circuit 34 is
On the other hand, the same clock 32 (waveform B-) is
At time 47, a delay amount of τ1 is received.
Gate open (waveform C-) Third AND circuit 37
, And shift as read pulse 51 (waveform F−).
Is supplied to the register 24. This read pulse 51
In order to avoid this, the shift register 24 has its second, third to ninth shift stages.
An 8-bit partial pattern is read into 24B, 24C to 24I. First
Indeterminate "*" because data is not supplied to shift stage 24A
For example, if the partial pattern at address 0 is read,
The shift register 24 looks like "* 10011010".   The clock that has passed through the first delay circuit 47 is further converted into a second delay circuit
48 and receives a delay of τ2 through the fourth AND circuit 38
Given to shift register 24 as left shift pulse 52
(Waveform G−), the second and third pulses are generated by the left shift pulse 52.
-9th shift stage 24B, 24C-24I data "10011010"
Each left shift stage, ie, first, second to eighth shift
Shifted to stages 24A, 24B-24H, and to ninth shift stage 24I
Is the data of the second shift stage 24B, in this case "1" is directly
Column input end S<sub>in</sub>Supplied from Therefore, shift register 2
The data in 4 changes to “100110101”.   The second, third to ninth shift stages 24B, 24 of the shift register 24
The outputs of C to 24I are output to the pattern
The memory address supplied to and read from memory 23, in this case
It is written again to address 0. That is, the fourth AND circuit 38
Output (waveform G−), that is, the left shift pulse 52
The write pulse 53 (wave
H-) is supplied to the pattern memory 23 and shifted.
2nd, 3rd to 9th shifts from 9 outputs of register 24
8-bit output “00110101” of stages 24B, 24C to 24I is at address 0
Is written to. Therefore, it is stored at address 0 before writing.
The data "10011010" was shifted left rotation shift,
That is, the data is shifted to the left and the leftmost data in the data sequence.
"1" is rotated to the right and at the right end of the data string
It is added (Fig. 3-column).   Further, the first, second to fourth shifts of the shift register
The four outputs of stages 24A, 24B to 24D are connected to sample clock 54 (wave
Consisting of four registers 25A, 25B to 25D according to form D-)
Latched by latch 25. In this case, the data is stored in the latch 25.
Is latched and supplied to the parallel-serial conversion circuit 26.
Is done.   Thus, the first clock 32 (waveform B-)
The 8-bit partial pattern "1001" stored at address 0
"1010" is a 4-bit pattern "1001" on the left side in parallel
-Supplied to the serial conversion circuit 26 and rotated to the left
And is stored again at address 0 (Fig. 3-
Field).   On the other hand, the address counter 42 has the same sample clock
54 (waveform D-) is counted, and the count value becomes "1"
(Waveform E-). The partial pattern of this address "1010111
1 ”is read out in the same manner (waveform F−),
Received a shift (waveform G-) and re-written to address 1.
(Waveform H-), and the left 4 bits in it
Of the sample clock 54 (waveform D
-) Is latched by the latch 25 (Fig. 3-
Field). According to the increment of the address counter 42, addresses 2 and 3
About the 8-bit partial pattern stored at the address
Also, the left 4 bits “1111” and “0001” are
Latch 25, and the parallel-to-serial conversion circuit 26
Supplied. These are stored at addresses 2 and 3.
The left rotation of each partial pattern is also 1 bit.
Rewriting is performed after receiving the shift. As a result,
Each of the four partial patterns in the pattern memory 23 is 1
It is rotated to the left by a bit (Fig. 3-
Field).   The parallel-to-serial conversion circuit 26 converts the supplied four partial patterns.
Stack "1001", "1010", "1111" and "0001".
And convert to serial data "1001101011110001" and output
I do. That is, Nos. 0, 1 to 3 with 4 clocks as one cycle
From the ground read output, the first, second to fourth bits on the left
Select and read the output of
As a result, the left end of the partial pattern "10011010" at address 0
16-bit pattern starting with, that is, basic random
The pattern "100110101111000" followed by "1"
Generated.   The fourth clock (waveform
D-) completes one cycle, and the address counter is counted.
The numerical value returns to "0" (waveform E-). In this state
Each address of the row memory 23 has a 1-bit left row.
Basic random pattern as a result of receiving the shift
From the second bit of the
8-bit partial patterns "00110101", "0101111"
1 "," 11100011 "and" 00100110 "are stored.
(Figure 3-column).   Therefore, with the next four clocks 32,
Read the partial pattern from pattern memory 23 and
Tension shift and latch the left 4 bits
The partial pattern stored at address 0
16-bit pattern starting from the left end of "00110101",
In other words, the pattern starting from the second bit of the basic random pattern
Turn “0011010111100010” is generated. This putter
And the pattern sequence generated in the previous four clock cycles
When combined with the rightmost data “1” of
Turns 100110101111000 and 10 are generated
And   Also in this case, the part stored in the pattern memory 23
The pattern is further shifted left by one bit.
(Figure 3,-,, column)
The minute pattern “01101010” is stored. Therefore, continued
In four clocks 32, the basic random pattern “1001
10101111000 ”, a 16-bit pattern starting from the third bit.
Turn “0110101111000100” is generated and the previous 4 clocks
Combined with the remaining pattern "10" generated by the cycle
The basic random patterns "100110101111000" and "10
0 "is generated. Transition of pattern memory 23 at this time
The figure is shown in the column of FIG. In the following four clock cycles
Is 16 starting from the 4th bit of the basic random pattern.
The bit pattern "1101011110001001" is generated and
With "100" generated in 4 clock cycles of
The basic random patterns `` 100110101111000 '' and `` 100
1 "pattern is formed. Pattern memory 2 at this time
The data of 3 is as shown in the column of FIG.   In the present invention, the clock 32 is 2<sup>n</sup>Hex counter
Ball 2<sup>Four</sup>16 clocks 32
Be counted.   The quaternary counter 42 is formed every four clock cycles
In addition to the basic random pattern `` 100110101111000 '', complete
Of the pattern carried over to the next cycle without being tied
Counts the number of bits, and the number of carried bits is latched.
Detected to be equal to the number of 25 registers 25A, 25B to 25D
I do. In this case, the number of bits remaining without being completed is 1
Increment by 1 bit for each cycle, 4 cycles (16 clocks)
) Detects that the number of registers in latch 25 is equal to 4.
(Waveform I-).   This 2ⁿAt the falling edge of the most significant digit A4 of the hexadecimal counter 41 (wave
I-), the output of the second flip-flop circuit 43 is inverted
(Waveform J-), and the switching means is provided by the inverted output.
That is, two 8-unit switches 27 and 28 are switched to the input terminal S2 side
available.   FIG. 4 is a circuit diagram showing an example of the switching means 27 and 28.
You. The input contacts S1 and S2 are connected to the eleventh AND circuit 61 and the twelfth
Circuit 62 is connected to one input terminal A of the
A control signal is supplied to the input terminal B. Given to control end 29
The control signal is sent to the 11th AND circuit 61 via the inverter 63.
Directly to the other input terminal B and to the twelfth AND circuit 62.
Be paid. An “L” level signal is supplied to the control terminal 29
And the 11th AND circuit 61 is opened and the twelfth AND circuit
The gate of the road 62 is closed, and an “H” level signal is
When supplied, the eleventh AND circuit 61 closes the gate,
The 12 AND circuit 62 has its gate opened. 11th AND circuit 61
And the output of the twelfth AND circuit 62 is supplied to the eleventh OR circuit 64.
It is. Therefore, according to the control signal, the input contact S1 or S2
Is output from the output terminal Q.   By this switching control, the fifth and the fifth
The outputs D4 and D5 to D7 of the 6th to 8th bits are the first, second to fourth switches.
Second and third shift registers 24 via the switches 27A and 27B to 27D.
To the fifth shift stage 24B, 24C to 24E, the first, second to fourth bits
Outputs D0, D1 to D3 are the fifth, sixth to eighth switches 27E, 27F to 27
The sixth, seventh to ninth shift stages 2 of the shift register 24 via H
4F, 24G to 24I. In addition, the sixth, seventh-
The outputs of the ninth shift stages 24F, 24G to 24I are the eleventh, twelfth to fourteenth switches.
Via the switches 28A, 28B to 28D, the first and
The second, third to fifth shift stages 24 are connected to the input terminals of the second to fourth bits.
The outputs of F, 24G to 24I are the fifth, sixth to eighth data of the pattern memory 23.
It is supplied to the input terminal of each bit.   In other words, the selection signal is inverted (waveform J-),
Changeover switches 27 and 28 from input contact S1 to input contact S2
To the 5th, 6th to 8th memories of the pattern memory 23.
The outputs D4 and D5 to D7 of the shift register 24 are the second and third
To the fifth shift stage 24B, 24C to 24E, and
Configured to be supplied to the second to fourth registers 25A, 25B to 25D
Is done.   According to the present invention, the output of the hexadecimal counter 41 is
It is supplied to the first pulse generator 45. First pulse generator 45
Is the falling edge (waveform I-) of the output of the hexadecimal counter 41
An adjustment pulse 55 having a pulse width τ4 is generated (waveform K−
). This adjustment pulse 55 is added via the second OR circuit 39.
Is supplied to the counter 42, and the count value is incremented by one.
(Waveform E-). The adjustment pulse 55 is applied to the second pulse.
The output pulse (waveform L) is supplied to the
As the adjustment clock 56, the shift
Read pulse 51 of register 24 (waveform F-), left shift
Pulse 52 (waveform G-) and rewriting to pattern memory 23
Supplied as a write pulse 53 (waveform H-)
Each control operation is performed one clock separately from clock 32.
It is advanced only for the amount of money.   That is, the 16th sample clock (waveform D−) is counted.
By counting, the address value of the address counter 42 becomes
When it becomes "0" (waveform E-), the pattern at address 0 is read.
Read out by the output pulse (waveform F-)
(Shifted waveform G-).
Data is returned to address 0 by the write pulse (waveform H-).
Is written to.   On the other hand, the pulse width of the adjustment pulse 55 of the first pulse generator 45
τ4 is selected to be larger than τ1 + τ2 + τ3. Writing
Is completed by the write pulse 54 (waveform H-).
Also, the second, third to fifth shift stages 24B, 24 of the shift register 24
Before the data of C to 24E is latched into the latch 25, the pulse
The address counter 42 steps at the trailing edge of the adjustment pulse 44 having the width τ4.
(Waveform E−), and the count value changes to “1”.
You. The second pulse is generated at the trailing edge of the adjustment pulse 55.
The adjusting clock 56 (waveform L) is output from the heater 46.
The adjustment clock 56 passes through the first, second, and third delay circuits 47, 48, and 49.
The read pulse (wave) of the partial pattern at address 1
F-), left shift pulse (waveform G-), write
Shift register 24 and pattern as pulse (waveform H-)
Supplied to the memory 23, and thus the partial pattern at address 1.
And receive a 1-bit left rotation shift.
Then, the 4-bit partial pattern “1010” on the right
Latch 25 (waveform D- '), parallel-serial conversion
It is supplied to the circuit 26. Therefore, the sump shown in waveform D-
Address 0 by a series of control pulses following the clock 54
Read, shift and rewrite
However, since there is no control pulse shown as the waveform D- ', 0
The pattern “1001” stored at the address
Adjustment that does not latch the latch 22 with the
Done. In other words, the carryover generated in the previous four cycles
Pattern the same pattern as the partial pattern "1001"
Reading from the memory 23 is avoided. Then it is number 2
4 bits “1010” on the right side of the partial pattern are latched.
Then, it is supplied to the parallel-serial conversion circuit 26. Therefore,
Combined with the passed "1001", the subsequent reference lander
The system pattern “100110101111000” is sequentially generated.   The same adjustment control is applied to the column following the column 'in FIG.
Is performed.   In the above example, the second and third shift registers 24
The third to ninth shift stages 24B, 24C to 24I
Read data and shift to the left by one step each.
The output of the second shift stage 24B to the ninth shift stage 24I.
After the rotation shift as described above, the first, second to fourth
The parallel outputs of shift stages 24A, 24B to 24D are latched by latch 25.
As described above, an eight-stage shift register is used.
In the first, second to eighth shift stages of the pattern memory 23
And immediately output the parallel outputs of the first, second to fourth shift stages.
Latch, then rotate shift and pattern
It can be configured to re-store the data in the memory 23.   Also, instead of the shift register, a normal 8-unit
Data from that register to the pattern memory.
The rotation is shifted by the connection method
It can also be configured to be rewritten. "The invention's effect"   As described above in detail, according to the present invention,
In the pattern memory for storing this random pattern
Is a pseudo-random pattern generated by the conventional memory read method.
Uses a memory that has a very small storage capacity
Be composed. Moreover, a pseudo run is performed from the pattern memory.
Control technology for generating dam patterns is also simple.
It is realized only by the high-speed read control technology. Therefore, the digital
High-speed pseudo-random patterns as in the field of telecommunications
It is particularly useful where generation is required.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a circuit example of a pseudo-random pattern generator according to the present invention, and FIG. 2 is a waveform for explaining an operation example of the pseudo-random pattern generator shown in FIG. Figure, third
The figure shows a state in which patterns stored in the pattern memory are sequentially transited. FIG. 4 shows an example of a circuit of switching means. FIG. 5 shows an example of a conventional pseudo-random pattern generator. FIG. 6 is a diagram showing a coincidence detecting circuit. 11: pattern memory, 12: address counter, 13: clock, 14: address decoder, 15: parallel-serial conversion circuit, 1
6: register, 17: match detection circuit, 18: AND circuit, 19: OR circuit, 21: pattern generation unit, 22: control unit, 23: pattern memory, 24: shift register, 25: latch, 26: parallel-serial Conversion circuit, 27: read switch, 28: write switch, 29: control terminal, 31: start signal, 32: clock, 33: first flip-flop circuit, 34: first AND circuit, 35: second
AND circuit, 36: first OR circuit, 37: third AND circuit, 3
8: Fourth AND circuit, 39: Second OR circuit, 41: ^2n- ary counter, 42: Address counter, 43: Second flip-flop circuit, 44: Address decoder, 45: First pulse generator, 46:
Second pulse generator, 47: first delay circuit, 48: second delay circuit, 49: third delay circuit, 51: read pulse, 52: left shift pulse, 53: write pulse, 54: sample clock, 5
5: adjustment pulse, 56: adjustment clock, 61: AND circuit, 62:
AND circuit, 63: inverter, 64: OR circuit.

Claims (1)

(57) [Claims] A pseudo random pattern (n is an integer of 3 or more) having a period of (2 ⁿ -1) bits is represented by 2 ^m bits (m = positive integer, n>
m) of 2 ⁿ / 2 ^m = 2 ^nm patterns divided sequentially for each m) and a 2 ^m- bit pattern continuous with the 2 ^nm patterns
2 ^{m + 1} bit pattern is stored as one word in memory and clock is counted and address is given to the above memory 2 ^nm
Hexadecimal address counter, a shift register in which a pattern read from the memory is input in parallel for each clock, a means for shifting the shift register by 1 bit after the parallel input, and the shifted pattern in the memory A latch for latching 2 ^m bits from one end of the shift register by the clock after the writing; and a parallel-serial conversion circuit for transmitting the latched pattern as a serial pattern. When the 2 ^n-ary counter for counting the clock, the output pattern of the memory by an output of the 2 ^n-ary counter, and means for switching each 2 ^m bits input pattern, the output of the 2 ^n-ary counter, the address counter Step by one, and input the read pattern of the memory in parallel to the shift register, To perform the 1-bit shift by means of bit shifting, the pseudo random pattern generator including means for causing the writing by the writing means.