JP2720469B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A method for manufacturing a thin film transistor (TFT) for driving a liquid crystal, without losing the advantage of the self-alignment method, and at the boundary between the protective film and the source / drain electrodes S and D. The object of the present invention is to provide a method of manufacturing a TFT without forming a gap, a gate electrode having a predetermined pattern on a transparent insulating substrate, and a semiconductor formed on the gate electrode via a gate insulating film. An active layer, a source electrode and a drain electrode on the semiconductor active layer, when manufacturing a thin film transistor which is disposed opposite to the semiconductor active layer with a protective film formed immediately above the gate electrode, the semiconductor active layer A protective film is formed on the entire upper surface, and a portion of the protective film immediately above the gate electrode is in contact with the protective film, and is smaller than the gate electrode, and is at least partially in contact with the protective film. Forming a resist film having a wider portion, and using the resist film as a mask, forming a lower protective film on the transparent insulating substrate in such a manner that the etching rate in a direction perpendicular to the surface of the transparent insulating substrate is higher than in other directions. Etching by anisotropic etching method,
Forming a protective film having an exposed end portion directly below the resist film; and forming a source / drain electrode material film over the exposed end portion of the protective film by a film forming method having good step coverage. Removing the resist film and lifting off the electrode material film attached on the resist film.

[Industrial applications]

The present invention relates to a method for manufacturing a thin film transistor (TFT) for driving a liquid crystal.

Since liquid crystal display devices have characteristics such as low power consumption, light weight, and easy color display, they are gaining a wide market as flat display devices such as pocket TVs and OA terminal devices.
In particular, a thin-film transistor-driven active matrix type liquid crystal display device capable of obtaining a large-capacity and clear gradation display has been partially put into practical use and is being actively developed and studied at present.

In this active matrix type liquid crystal device, a thin film transistor is added to each pixel. Therefore, in order to manufacture an active matrix liquid crystal display device, it is necessary to manufacture tens of thousands to hundreds of thousands of transistors with no defect and a high yield.

[Conventional technology]

The conventional method of manufacturing a self-aligned TFT is shown in FIGS.
This will be described with reference to FIG.

[Refer to FIG. 3 (a)] After a gate electrode G made of a Ti (titanium) film is formed on a transparent insulating substrate 1 according to a predetermined pattern, the gate insulating film 2 is made of SiN (silicon nitride) having a thickness of about 3000 mm. )
An a-Si (amorphous silicon) film having a thickness of about 1000 mm as a film and a semiconductor active layer 3;
(SiO ₂ ) film is continuously formed by a plasma CVD method.

[Refer to FIG. 3 (b)] Next, the positive type register film 5 applied on the laminated film is irradiated with ultraviolet rays from the back surface of the substrate using the gate electrode G as a mask. By this step, the exposed portion 6 of the resist film 5 other than immediately above the gate electrode G becomes soluble in the developing solution.

[See FIG. 3 (c)] Therefore, by subjecting the resist film 5 to a development treatment, the resist film 5 'remains only directly above the gate electrode G. Using the resist film 5 'as a mask, the exposed portion of the protective film 4 is removed by etching to form a protective film 4' self-aligned with the gate electrode G.

[Refer to FIG. 3 (d)] Then, with the resist film 5 'remaining, an a-Si: H film 71 and a Ti film are used as the source / drain electrode material films 7.
72 is continuously formed.

[Refer to FIG. 3 (e)] Next, the source / drain electrode material film 7 adhering to the resist film 5 'used as the mask is removed by a lift-off method, and the source electrode S And a drain electrode D are formed.

[Problems to be solved by the invention]

As described above, in the conventional self-alignment method, as shown in FIG. 3E, a minute gap A is formed on the boundary between the protective film 4 'and the source electrode S and the drain electrode D.

This is a lift-off method in which the electrode material film 7 just above the channel is used.
This is intended to prevent the gap A from being generated. This time, lift-off becomes difficult.

The existence of such a gap A causes a problem of lowering the reliability or yield of the TFT as described below.

Starting from gap A, underlying semiconductor active layer (a-Si film) 3
And the gate insulating film (SiN film) 2 is easily broken. As a result, the breakdown voltage between the gate electrode G and the source / drain electrodes S and D decreases.

To reduce the photocurrent of the TFT, the semiconductor active layer (a
It is effective to reduce the thickness of the (Si: H film) 3 to about 100 °. However, if there is a gap A, a-Si: H
The film may be attacked, and the TFT characteristics are degraded.

Therefore, the present invention does not lose the advantage of the self-alignment method,
Moreover, it is an object of the present invention to provide a method of manufacturing a TFT which does not cause a gap on a boundary between the protective film and the source / drain electrodes.

[Means for solving the problem]

The configuration of the present invention will be described below with reference to FIGS. 1 (a) to 1 (c).

In the method of manufacturing a thin film transistor according to the present invention, as shown in FIG. 1A, a stencil-shaped resist film 5 'is formed on a protective film 4 formed on a semiconductor active layer 3, and this is used as a mask. The protective film 4 is etched using an anisotropic etching method to form a protective film 4 'whose end is exposed to the area immediately below the resist film 5'.

Next, as shown in FIG. 1 (b), after forming a source / drain electrode material film 7 by a film forming method having a good step coverage property, as shown in FIG. 1 (c), a resist film used as the mask is used. 5 'is removed, and the electrode material film 7 attached to the upper layer is lifted on.

(Operation)

As described above, by using the stencil-shaped resist film 5 'as a mask and patterning the protective film 4 by anisotropic etching, not only the portion of the protective film 4 covered with the resist film 5' but also the resist The shaded portion of the film 5 'is not etched.

Accordingly, a protective film 4 'having a substantially same shape as the projected pattern of the resist film 5', that is, the resist film 5 'as viewed from directly above is formed.

Next, by a film forming method having a good step coating property, for example, a plasma chemical vapor deposition (P-CVD) method for forming a film under a relatively high gas pressure, the source / drain electrode material film 7 is formed. When n ⁺ a-Si: H film 71 and Ti film 72 are formed,
Since the electrode material film 7 is also applied to the end of the protective film 4 'that is exposed without being covered with the resist film 5', no gap is formed between the electrode material film 7 and the protective film 4 '.

Therefore, if lift-off is performed to remove unnecessary portions of the source / drain electrode material film 7 deposited thereon together with the resist film 5 'used as a mask, the protective film 4', the source electrode S and the drain electrode A structure with no gap between D is obtained.

As described above, according to the present invention, it is possible to solve the problem caused by the structural gap A according to the conventional technology.

Furthermore, since the resist film 5 'has a stencil shape at the time of the lift-on, the distance between the side surface of the resist film 5' and the electrode material film 7 is large, and therefore, the solvent easily permeates the side surface of the resist film 5 '. There is also an effect that the process becomes easy.

As described above, according to the present invention, no gap is formed between the source electrode S and the drain electrode D and the protective film 4 ', so that the yield and reliability of the TFT are improved.

It is preferable that the resist film 5 'has a stencil shape which spreads from the lower portion to the upper portion as described above, but is not limited to this. The point is that a portion wider than the portion in contact with the lower protective film may be present.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 2 (a) to 2 (d).

[See FIG. 2 (a)] On a transparent insulating substrate 1 such as a glass substrate, a thickness of about 70
After a gate electrode G made of 0 ° Ti is formed in accordance with a predetermined pattern, the gate electrode G is formed by a P-CVD method, for example, to a thickness of about 3000 mm.
A gate insulating film 2 made of a SiN film and an a-Si: H film as a semiconductor active layer 3 (thickness of about 100 to 1000 mm, an SiO ₂ film 41 with a thickness of about 200 mm as a protective film 4 above the channel and a thickness of about 200 mm). 1000Å S
A laminate with the iN film 42 is continuously formed. Next, a positive type photoresist is applied on the entire surface to form a resist film 5, and then the back surface of the transparent insulating substrate 1 is irradiated with ultraviolet rays using the gate electrode G as a mask. As a result, the exposed portion 6 of the resist film 5 other than immediately above the gate electrode G becomes soluble in the developing solution.

[Refer to FIG. 2 (b).] Next, in order to form a photoresist having a stencil structure, a surface hardening treatment, for example, toluene at 20 ° C. to 35 ° C.
After soaking for about 20 minutes and drying at a temperature of about 70 ° C. for about 5 minutes, normal development is performed.

Since the resist film 5 has been subjected to a surface hardening treatment, not only the exposed portion 6 is removed and the resist film 5 'remains immediately above the gate electrode, but also the shape thereof is thinner in an undercut shape, A stencil-shaped resist film 5 'as shown is formed.

When forming the stencil-shaped resist film 5 ', it is necessary to control the exposure amount and the like in accordance with the surface hardening treatment.

Next, after the stencil-shaped resist film 5 'is post-baked, the exposed portion of the SiN film 42 in the protective film 4 is removed by anisotropic reactive ion etching using the resist film 5' as a mask. I do. In this step, for example, CF ₄ (flow rate of about 100 sccm), O ₂ (flow rate of about 10 sccm)
m), by performing parallel plate type plasma etching at a gas pressure of about 10 pa and an RF power of about 300 W.

In this step, was provided an SiO ₂ film 41 under the SiN film 42, at the time of patterning the SiN film 42 by the anisotropic etching method, that the SiO ₂ film 41 serves as a stopper for etching down Since the stopper is used, the SiN film 42 can be etched and the etching can be stopped without etching an extra portion.

The SiN 42 can be patterned using the stencil-shaped resist film 5 'as a mask by the above-described anisotropic etching method, but no effective anisotropic etching method is known for the SiO ₂ film 41. On the other hand, the SiO ₂ film 41 has a property that it can be used as a stopper for anisotropic etching of the SiO film 42 as described above. Therefore, in this embodiment, the protective film 4 has a two-layer structure of the SiO ₂ film 41 and the SiN film 42, and the lower SiO ₂ film 41 is used as an etching stopper to form the upper SiN film 41.
After patterning the film 42, the exposed portion of the lower SiO ₂ film 41 is etched by a wet etching method using a hydrofluoric acid-based etchant using the obtained SiN film 42 as a mask. If the SiO ₂ film 41 is made sufficiently thin, it can be easily etched, and undesired etching such as side etching can be prevented from progressing.

In this manner, the protective film 4 'that covers immediately above the gate electrode G, that is, the channel region, and that exposes the area immediately below the resist film 5' is left. Since the portion other than the region where the protective film 4 'remains, that is, the surface of the a-Si: H film of the semiconductor active layer 3 where the source / drain electrodes are to be formed is exposed,
Immediately proceed to the next step so that a natural oxide film is not formed on this surface.

[See FIG. 2 (c)] Then, while leaving the resist film 5 ', n ⁺ a-Si: H
P-CVD with a substrate temperature of 120 ° C or less using a film 71 (thickness: about 300 mm)
The Ti film 72 (thickness of about 1000 mm) is deposited by the evaporation method at a substrate temperature of 120 ° C or less using a revolving type substrate holder.
The film is formed continuously.

In the method of forming the n ⁺ a-Si: H film 71, since the reaction gas pressure is relatively high, flying particles are wrapped around, and n is also applied to the end of the protective film 4 'near the root of the resist film 5'. ^{+ The} a-Si: H film 71 adheres. In addition, since Ti is formed using a self-revolving type substrate holder, the throwing power is similarly improved. Therefore, as shown in this step, the electrode material layer 7 covering the end of the protective film 4 'is formed.

[See FIG. 2 (d)] Next, the resist film 5 'is removed, and unnecessary portions of the electrode material layer 7 deposited thereon are lifted off. In addition,
In this step, since the side wall of the resist film 5 'is exposed, the resist film 5' can be easily removed.

As described above, according to the TFT manufacturing method of the present embodiment, since the source electrode S and the drain electrode D are formed by the self-alignment method as in the related art, there is no displacement from the gate electrode G, and the protective film There is no gap between 4 'and the source electrode S and the drain electrode D. Therefore, the occurrence of various problems caused by the presence of the gap is prevented, and the reliability and manufacturing yield are improved. In addition, conventionally, it is attempted to eliminate the gap. Although it was difficult to remove the resist film, in this embodiment, the removal of the resist film 5 'is very easy.

It should be noted that the present invention is a self-aligned TFT with the above-described backside exposure.
Normal TFT including a process of forming a lift-off resist pattern using a photomask, not limited to manufacturing
It goes without saying that it can be applied to manufacturing.

〔The invention's effect〕

As described above, according to the present invention, there is no gap between the source / drain electrodes and the upper protective film of the channel, which has been a problem in the conventional self-alignment method. It is possible to eliminate the deterioration of the retention and reliability, and it is possible to surely and easily perform the lift-off process.

[Brief description of the drawings]

1 (a) to 1 (c) are explanatory views of the configuration of the present invention, FIGS. 2 (a) to 2 (d) are explanatory views of an embodiment of the present invention, and FIGS. 3 (a) to 3 (e) are conventional drawings. It is a self-alignment method explanatory drawing. In the figure, 1 is a transparent insulating substrate, 2 is a gate insulating film,
3 is a semiconductor active layer, 4, 4 'are protective films, 5, 5' are resist films, 6 is a portion to be exposed, 7 is an electrode material film, G is a gate electrode,
S indicates a source electrode, D indicates a drain electrode, and A indicates a gap.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichi Soeda 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-2-260369 (JP, A)

Claims (3)

(57) [Claims] 1. A gate electrode (G) having a predetermined pattern on a transparent insulating substrate (1), and a semiconductor active layer (3) formed on the gate electrode via a gate insulating film (2).
And a thin film transistor in which a source electrode (S) and a drain electrode (D) are disposed on the semiconductor active layer so as to face each other with a protective film (4 ′) formed immediately above the gate electrode of the semiconductor active layer interposed therebetween. In manufacturing, a protective film (4) is formed on the entire surface of the semiconductor active layer (1), and a portion of the protective film (4) in contact with the protective film immediately above the gate electrode (G) is a gate. Forming a resist film (5 ') smaller than the electrode and having at least a portion wider than a portion in contact with the protective film; and using the resist film (5') as a mask, a lower protective film ( 4) is etched by an anisotropic etching method in which an etching rate in a direction perpendicular to the surface of the transparent insulating substrate (1) is higher than that in other directions, and an end portion is exposed immediately below the resist film. Form the film (4 ') Forming a source / drain electrode material film (7) over the exposed end of the protective film (4 ') by a film forming method having good step coverage; and the resist film (5') And lifting off the electrode material film deposited on the upper portion of the thin film. 2. A positive resist film (5) is formed on the protective film (4), and the back surface of the transparent insulating substrate (1) is formed on the resist film (5) using the gate electrode (G) as a mask. After performing exposure from the surface, and then subjecting the resist film to a surface hardening process, the resist film is subjected to a development process, and the portion of the protective film immediately above the gate electrode is in contact with the protective film. 2. The method of manufacturing a thin film transistor according to claim 1, wherein a resist film (5 ') which is smaller and has at least a portion wider than a portion in contact with the protective film is formed. 3. A silicon dioxide film (41) and a silicon nitride film (42) thicker than the silicon dioxide layer (41) are formed on the semiconductor active layer (3) as the protective film (4). The silicon film is etched by an anisotropic etching method in which the etching rate in a direction perpendicular to the surface of the transparent insulating substrate is larger than in other directions, and then the silicon nitride film formed by the anisotropic etching is used as a mask. 2. The method according to claim 1, wherein the silicon dioxide film is etched by a wet etching method to form a protective film exposing an end portion.