JP2722593B2 - Data compression buffer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly, to a data buffer using a FIFO (first-in first-out) buffer.

[Conventional technology]

As a conventional data buffer, a data buffer using a FIFO buffer is known.

[Problems to be solved by the invention]

In the data buffer using the conventional FIFO buffer described above, the number of data that can be loaded is determined by the capacity of the FIFO buffer and the unload operation, and even when the same data is continuously input / output to / from the FIFO buffer, one data can be loaded. Loading and unloading are performed for each data, and the FIFO buffer cannot be used efficiently.

[Means for solving the problem]

A data compression buffer according to the present invention loads input data on an input data bus in response to a data load signal, stores the loaded input data as storage data, and responds to a data unload signal. A data FIFO buffer for unloading the stored data as output data on an output data bus, and a plurality of resists each holding data set by firmware and outputting the held data, When loading the input data into the buffer, monitor the input data on the input data bus, and stop sending the data load signal when input data equal to the held data continues, A load control circuit for outputting a first control signal and a counter number load signal; While Shin, the unload controller for stopping the transmission of the data unloading signal, counts up every receive said first control signal,
First counter means for outputting the counted up value as a first selection signal; and a plurality of counters to which counter numbers are assigned,
Selecting a counter having a first counter number selected by the first selection signal as a first selected counter, and successive identical data equal to the held data in the first selected counter Is counted up from an initial value, the counted value is held as a data count, the first counter number is output as an input counter number, and the output counter number is received as a second selection signal. A counter having a second counter number selected by the second selection signal is selected as a second selected counter, and the second selected counter is held by the second selected counter. Second counter means for outputting the second control signal during a period from when the data count is counted down to the initial value; In response to a number load signal, the input counter number is loaded, the loaded input counter number is stored as a storage counter number, and in response to the unload signal, the storage counter number is stored in the output counter number. For counter number to unload as
FO buffer.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, a data compression buffer according to an embodiment of the present invention loads input data on an input data bus IDB in response to a data load signal DL described later and stores the loaded input data. In addition to storing as data, in response to a data unload signal DA described later,
It has a data FIFO buffer 10 for unloading stored data on the output data bus ODB as output data.

The data load signal DL is supplied from the load control circuit 20. The load control circuit 20 is supplied with a buffer load signal BL instructing a buffer load. Load control circuit
Reference numeral 20 includes a plurality of registers (not shown) in which data can be set by firmware. Each of the registers holds data set by firmware and outputs the held data. The load control circuit 20 sends a data load signal DL for causing the data FIFO buffer 10 to perform data loading to the data FIFO buffer 10 in response to the buffer load signal BL. The input data is constantly monitored, and when the input data equal to the held data continues, the transmission of the data load signal DL is stopped, and the first control signal C1 and the counter number load signal CNL are output.

The data unload signal DA is supplied from the unload control circuit 30. The unload control circuit 30 is supplied with a second control signal C2 described later and a buffer unload signal BA instructing buffer unload. When the buffer unload signal BA is supplied and the second control signal C2 is not received, the unload control circuit 30
A data unload signal DA is sent to the data FIFO buffer 10 in order to cause the buffer 10 to perform normal data unloading. On the other hand, the unload control circuit 30 stops sending the data unload signal DA while the buffer unload signal BA is supplied and the second control signal C2 is being received.

The first control signal C1 is supplied to the first counter circuit 40 and the second counter circuit 50. The first counter circuit 40
It counts up each time it receives the first control signal C1, and outputs the counted value as a first selection signal S1. The first selection signal S1 is supplied to the second counter circuit 50.

The second counter circuit 50 is further supplied with a later-described second selection signal S2 (output counter number OCN) and a buffer load signal BL. The second counter circuit 50 has a plurality of counters to which counter numbers are assigned. When loading the data FIFO buffer 10, the second counter circuit 50 selects a counter having a first counter number selected by the first selection signal S1 as a first selected counter. The first selected counter counts up the number of consecutive identical data equal to the held data from the initial value, and the first selected counter holds the counted value as the data count. Further, the first counter number is output as the input counter number ICN.

On the other hand, when unloading to the data FIFO buffer 10, the second counter circuit 50 outputs an output counter number OCN described later.
As a second selection signal S2, and the second selection signal S2
Is selected as the second selected counter. And
The second control signal C2 is output until the second selected counter counts down from the number of data held in the second selected counter to an initial value.

Counter number load signal CNL and data unload signal D
A and input counter number ICN are FIFO buffer for counter number
Supplied to 60. When loading the data FIFO buffer 10, the counter number FIFO buffer 60 loads the input counter number ICN in response to the counter number load signal CNL,
The loaded input counter number is stored as a storage counter number. Also, the FIFO buffer 60 for the counter number
Unloads the storage counter number as the output counter number OCN in response to the data unload signal DA when unloading to the data FIFO buffer 10.

 Next, the operation of the present embodiment will be described.

Normal data transfer uses a data FIFO buffer 10, and input data is input from an input data bus IDB by a buffer load signal BL and a buffer load signal BA, and output data is output from an output data bus ODB.

The data to be compressed from the firmware is written in the register of the load control circuit 20 in advance.

When the input data on the input data bus IDB is the same as the data written to the register by the firmware and is continuous, when the input data is input to the data FIFO buffer 10, the load control circuit 20 outputs the data load signal DL. Stopping does not load the input data. Also, the first
The first counter circuit 40 and the second counter circuit 50 know that the same data has been continuously loaded by the control signal C1, and the first counter circuit 40 uses the first selection signal to generate the second counter. Select one counter in circuit 50.
Further, the counter selected by the buffer load signal BL counts up. At the same time, the counter number for managing how many times the same data as the data set by the firmware has been loaded into the counter number FIFO buffer 60 is used as the input counter number ICN, and the counter number load signal CNL is sent to the counter number FIFO buffer 60. Load using.

This time, the data FI is output by the buffer unload signal BA.
When data is unloaded from the FO buffer 10, the FIFO counter 60 for the counter number is also
Unloaded using DA. At that time, for the counter number
The FIFO buffer 60 outputs, as the output counter number OCN, the counter number that has counted the continuous number of the same data as the data set by the firmware at the time of loading, so that the count of the selected counter in the second counter circuit 50 is counted. Until is indicated, an unload suppression instruction is issued to the unload control circuit 30 using the second control signal C2. When the counter is turned on, the next data is
Unloaded from FO buffer 10.

〔The invention's effect〕

As described above, the present invention provides a data FIFO buffer for inputting / outputting data, a load control circuit including a plurality of registers in which data is set by firmware,
A second counter means comprising a plurality of individually numbered counters, a first counter means, and a counter number FIFO buffer for inputting / outputting the counter number; data transmitted from the load control circuit to the data FIFO buffer; Load signal, counter number load signal to the counter number FIFO buffer, and data FIFO from the unload control circuit.
A data unload signal directed to the buffer and the counter number FIFO buffer; a first selection signal directed from the first counter means to the second counter means; and an input counter directed from the second counter means to the counter number FIFO buffer. A first control signal from the load control circuit to the first and second counter circuits; a second control signal from the second counter means to the unload control circuit;
When the same data as the data set by the firmware is loaded into the data FIFO buffer according to the output counter number from the FIFO buffer to the second counter means, the load control circuit stops the data load signal and starts loading. In addition, one of the counters in the second counter means is selected by the first control signal and the first selection signal, and the same counter as the data set by the firmware is set by the selected counter. Counts whether data has been loaded, loads the counter number of the counter it manages into the counter number FIFO buffer,
When the buffer is unloaded, the counter number FIFO buffer is also unloaded at the same time, and the counter managed by the second counter means is controlled by the counter number (second selection signal) sent from the counter number FIFO buffer. Select, count down the selected counter, and suppress the unloading of the data FIFO buffer by the unload control circuit, so that if the firmware knows that the same data By setting, there is an effect that the data FIFO buffer can be used efficiently and more than the capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a data compression buffer according to one embodiment of the present invention. 10 ... FIFO buffer for data, 20 ... Load control circuit,
30 ... Unload control circuit, 40 ... First counter circuit, 50 ... Second counter circuit, 60 ... Counter number
FIFO buffer.

Claims (1)

(57) [Claims] An input data on an input data bus is loaded in response to a data load signal, the loaded input data is stored as storage data, and the storage data is loaded in response to a data unload signal. A data FIFO buffer for unloading the data as output data on an output data bus, and a plurality of resists each for holding data set by firmware and outputting the held data. When loading the input data, the input data on the input data bus is monitored, and when the input data equal to the held data continues, the transmission of the data load signal is stopped. A load control circuit for outputting a signal and a counter number load signal; and receiving the data while receiving the second control signal. An unload control circuit for stopping transmission of the data unload signal, a first counter means for counting up each time the first control signal is received, and outputting the counted up value as a first selection signal; And selecting a counter having a first counter number selected by the first selection signal as a first selected counter. The number of consecutive identical data equal to the held data is counted up from an initial value, the counted value is held as the number of data, the first counter number is output as an input counter number, and an output counter is output. Number as a second selection signal, and a counter having a second counter number selected by the second selection signal is stored in a second counter. Selecting the selected counter, and performing the second control until the second selected counter counts down from the data count held in the second selected counter to reach the initial value. Second counter means for outputting a signal; loading the input counter number in response to the counter number load signal; storing the loaded input counter number as a storage counter number; Counter number FIFO for unloading the storage counter number as the output counter number in response
A data compression buffer, comprising: a buffer;