JP2723507B2 - Electronic musical instrument - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument, and more particularly, to an electronic musical instrument that digitally generates an envelope signal. 2. Description of the Related Art In recent years, digitalization of electronic musical instruments has been promoted because of their good timbre and easy control. As a matter of course, envelope generation is also performed digitally (for example, Japanese Patent Laid-Open No. 52-102710). FIG. 2 is a block diagram of the conventional electronic musical instrument described above, and the description will be given below. When the key press signal KON indicating key press release changes from "0" to "1", the logic circuit 1 changes the A output to "1". As a result, an attack level is output from the gate 2, and zero is output from the gates 3 and 4. Since these are added by the adder 5, the adder 5 outputs the attack level as it is. The attack level D _a, when the value of the register 10 and E _n, the output ΔE of the subtractor 6 is a (D _a -E _n). The multiplier 7 shifts the value ΔE right by 8 bits by τ. Therefore, the output M of the multiplier 7 is τ · (D _a −E _n ). This value M is provided to the adder 9 via the gate 8. The adder 9 values E _n and the gate 8 outputs the register 10
Is added. Thus the output S _n of the adder 9 is the _{E n + τ · (D a} -E n). Storing the value S _n to the register 10. The value E _n of the order register 10 will be updated as follows. _{E n + 1 = E n +} τ · (D a -E n) ...... (1) the value E _n of the register 10 in this way increases with the changes such as when charging the capacitor (3 (A section in the figure). The output E _n of the register 10 is used as an envelope signal. Here increases E _n gradually, becomes equal to the attack level D _a, the output of the subtractor 6 is Z ₀ = "1" will be zero.
Then, the output A of the logic circuit 1 becomes "0", the output B becomes "1", the gate 2 is closed, and the gate 3 is opened. Thus the adder 5 outputs the sustain level D _s. Following the a is calculated according to the form of a "D _a" to "D _s" At a a manner (1) Similarly performed, the register output E _n gradually approaches the sustain level D _s (FIG. 3 B section). Here, the output state of the logic circuit 1 even when the E _n = D _s is as unchanged. Next, when the key is released, the key press signal KON becomes "0", the output S of the logic circuit 1 becomes "0", and the output R becomes "1". Then, the gate 3 is an adder 5 for opening the closed gate 4 outputs Ficoll Lee null level D _f. Hereinafter, in the same manner as above,
(1) "D _a" to "D _f" and the operation according to the form is carried out register output E _n gradually approaches the final level D _f At a (FIG. 3 C section). Attack, decay, sustain,
An envelope signal such as a release is formed. INVENTION In trying to problems, however, such as the above-described configuration resolution, a transfer from the attack to decay, the envelope value E _n must wait until it equals a D _a is the target value. (1) to the value exponential change in E _n recurrence formula represented by the formula, from the envelope values E _n becomes 90% of the target value D _a 99
% To become time it is equal to the time the envelope value E _n is from 0% to 90% of the target value D _a. That is, the envelope value _En
There it takes considerable time to actually from attack from nearly equal to the target value D _a until decay. Further, with the above configuration, the decay mode cannot be set before the slope of the envelope signal during the attack is not zero. That is, there is a problem that it is impossible to obtain an envelope signal that generates a pulsative musical tone having an attack portion (section A) as shown in FIG. The present invention has been made in view of the above problems, and has as its object to provide an electronic musical instrument that generates an envelope that can shift from attack to decay even if the slope of the envelope is not zero. Means for Solving the Problems In order to solve the above problems, the electronic musical instrument of the present invention has a memory for storing a level D representing a change in an envelope signal, a time constant τ, and a value T representing a predetermined time for each address. And an address counter for designating an address of the memory, and an envelope signal which, based on the value (D, τ) output from the memory, asymptotically approaches a value determined by the D with an amount of change determined by τ. It has an envelope signal generating means for generating and an updating means for updating the output value of the address counter when a time determined by the T elapses. Operation The present invention has the above-mentioned configuration, and does not wait until the value determined by D becomes equal to the envelope signal.
Since the calculation time is managed and the value of (D, τ) is updated when a predetermined time elapses, the envelope signal approaches the value determined by D as shown in the conventional example, and ｛τ Even if (E _n −D) 一定 becomes zero, (D, τ) is updated after a certain time, so that it is not necessary to increase the bit length of the envelope signal. Further, since the value of (D, τ) can be updated irrespective of the value determined by D and the envelope signal value by the time information T, (D, τ) can be obtained when the slope of the envelope signal is not zero.
τ) can be updated, and a steep attack portion can be formed. Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an electronic musical instrument according to an embodiment of the present invention. In FIG. 1, reference numeral 20 denotes an ENV register which stores envelope data. 21 is an adder, the terminal A is connected to the A bus, the terminal B is connected to the B bus,
The value of terminal B is inverted and added to the value of terminal A, and
(Carry input) data is added and output to the C bus.
When the terminal R becomes "1", the data on the terminal A
Set to “0” to perform the addition operation. Reference numeral 22 denotes a shifter.
Is shifted rightward according to the input to the terminal C and output from the terminal O. The terminal C are given b ₅ ~b ₂ below. 23 is a multiplier, a terminal A is a C bus, a terminal B
Is connected to the D bus, multiplies the data supplied to the terminals A and B, and outputs the result to the E bus. Reference numeral 24 denotes a rate data register, which can be rewritten at any time by a microcomputer or the like. Reference numeral 25 denotes a waveform data generator, which outputs a periodic waveform signal. 26 is a level detector,
When the absolute value of the value given to the terminal A becomes “0” or “−1”, “1” is output from the terminal Y. Reference numeral 27 denotes a timer counter which counts a predetermined time in accordance with the input from the terminal A, and outputs "1" from the terminal Y when the time elapses. Reference numeral 28 denotes a selector, which selects and outputs an input supplied to a terminal A and a terminal B according to an input signal supplied to a terminal S.
An address counter 29 increments address data based on a clock signal supplied from a terminal CK when a signal supplied to a terminal EN is "1". 30 is EN
It is a V data memory, reads data using a signal given from a terminal A as an address, and outputs 20-bit data from a terminal D. The data format of the data stored in the ENV data memory is as shown in Table 1. 31 and 39 are latches for latching the signal given to the terminal D by the signal given to the terminal G. 32 to 37 are tri-state gates (hereinafter simply referred to as gates).
Reference numeral 38 denotes a sequencer, which includes a key press signal KON and a clock signal C.
The necessary timing signals S _{1 to} S _N are generated based on LK. Next, the operation of this embodiment will be described with reference to FIG. First, when the key press signal KON changes from "0" to "1" due to a key press or the like, the first timings 0 to 10 perform an operation as an initial mode, then enter a normal mode, and repeat the normal mode timings 0 to 10. . <Initial mode> First, at the timing 0, the data from the ENV data memory 30 based on the output of the address counter 29 is read (timing signal S ₈ to the initial mode is "1"
, And the address counter 29 is reset, so that data is read from address 0). The timing signal S ₅ at the timing 1, the data is latched by the latch 31. At timing 2, the gate 34 and the gate 37 are turned on,
ALL “0” is supplied to the A bus, and b _{13 to} b _A (D), which are the upper 10 bits of the ENV data memory, are supplied to the B bus. At the same time the adder 21 when the timing signal S ₁₁ is "1" is output A bus and the C bus performs addition of B bus at the timing 3. Here, considering this addition operation,
Since “1” is given to the terminal CI of the adder 21 and the data of the B bus is inverted and added, (terminal A input = 0) −D (2) is calculated. Become. At timing 4, the multiplier 23 multiplies the data on the C bus by the output RD of the rate data register 24 and outputs the result to the E bus. The output of the E bus is (0-D) × RD (3). At timing 5, the timing signals S ₁ and S ₂ become “1”, and the gates 32 and 33 are turned on. Here, the gate 33 shifts the data of the E bus right by 2 bits and
I give it to the bus. At timing 6, at the same time when the timing signal S ₁₁ is "1", performs addition of data with reference to a signal from the adder 21 is supplied to the terminal R, and outputs to the C bus. Therefore, the addition output is Becomes That is, in this addition, a multiplication of 0.75 times (0-D) is performed. At timing 7, the shifter 22 performs a bit shift of the data based on the data (b _{5 to} b ₂ ) given to the terminal C, and outputs the data from the terminal 0. Therefore, the output of shifter 22 is However, m = b _{5 to} b ₂ . That is, a multiplication of 0.5 m is performed. Also, this value is given to the level detector 26, and this value is
If “0”, ALL “1”, “1” is output. Where the selector
28 in accordance with the output b ₀ of the latch 31, the level detector 26 of the above
And the output of this timer counter 27, and outputs it from the terminal Y. The address counter 29 receives the output of the selector 28, and if the output is "1", increments the address. In the timing 8, the gate 35 and 37 is turned on, the ALL "0" to the A bus, a timing signal S ₁₁ at the same time the output is given of the shifter 22 becomes "1" to the B bus. For this reason,
The output of the adder 21 is Becomes At timing 9, this value becomes ENV through the C bus.
The data is written to the register 20 and sent to the multiplier 23 at the same time. At this time, the waveform data generator 25 generates periodic waveform data and supplies it to the D bus. Therefore, the multiplier 23 multiplies the envelope data and the waveform data represented by the equation (7) and outputs the result from the E bus. At timing 10, the latch 39 latches the output of the multiplier 23 and sends it out as a tone output, ending the initial mode. <Normal mode> In the normal mode, “0” is set in the ENV register 2 in the equations (2) to (7) in the initial mode.
The thing that was replaced by the output E _n of 0. Therefore, in normal mode, equation (7) becomes However, b ₁ = 0. Since this value is stored in ENV register 20, ENV
The value E _n of the register 20, Becomes In this way, the value of the ENV register 20 gradually approaches “D”. Also, address counter
When the value of 29 changes and the value of D changes, it changes based on the new values of m, b ₁ and b ₀ so as to asymptotically approach the new value of D. Next, when the key is released and the key press signal KON becomes “0”, the gate 34 does not turn on at the timing 3 and the gate 36 turns on. Therefore, the value becomes equal to D = 0 in the equation (9), and the value of the ENV register 20 gradually decreases toward “0”. Now consider the timer counter 27, the timer counter 27 and timer data T is given by b ₉ ~b ₆ of the latch 31, and outputs a pulse signal at time intervals corresponding to the timer data T. Here, if it is assumed that b ₀ = 0, the output of the timer counter 27 is given to the address counter 29. Therefore, after the above-described operations at timings 0 to 10 are performed several times, the timer counter 27 outputs In response to the pulse signal, the address counter 29 is incremented, and the value of (D, τ) is updated, and the value of the timer data T is also updated. This makes it possible to freely control the number of operations by each (D, τ) in the ENV data memory. In this embodiment, the adder 21 and the multiplier 23 are used in a time-division manner. However, these arithmetic units may be individually provided for each operation. Conversely, in this embodiment, one channel of the envelope is generated. However, it is a matter of course that the envelope signal of a plurality of channels can be generated by using the circuit shown in FIG. 1 in a time division manner. It is. As described above, according to the present invention, based on the value (D, τ) read from the memory, the envelope signal is generated so as to approach the value determined by D with the variation determined by τ. In the electronic musical instrument, the predetermined time T is read out from the memory together with the (D, τ), and when the time determined by the predetermined time T elapses, the (D, τ) and T
Is updated, the envelope signal approaches the value determined by D as shown in the conventional example, and ｛τ
Even if (E _n −D) 一定 becomes zero, (D, τ) is updated after a certain time, so that it is not necessary to increase the bit length of the envelope signal. In addition, since the value of (D, τ) can be updated by the time information T independently of the value determined by D and the envelope signal value, the value of (D, τ) can be updated when the slope of the envelope signal is not zero. Can be updated, and a steep attack portion can be formed. Also, if the current envelope value and the values of D and τ are determined, the time until the envelope value and D match is uniquely determined. Therefore, if a predetermined time T is determined for that value,
Since the D and τ values are updated in the same manner as in the conventional example, it is possible to perform envelope control in a form including the conventional example.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional electronic musical instrument, and FIG. 3 is generated by the electronic musical instrument shown in FIG. FIG. 4 is a waveform diagram showing an envelope signal of the present invention, and FIG. 4 is a waveform diagram showing an envelope signal of the present invention. 20: ENV register, 21: Adder, 22: Shifter, 23
... Multiplier, 24 ... Rate data register, 25 ... Waveform data generator, 27 ... Timer counter, 29 ... Address counter, 30 ... ENV data memory, 31 ... Latch, 32
~ 37 ... Gate, 38 ... Sequencer, 39 ... Latch.

Continuation of front page    (72) Inventor Katsuyoshi Fujii               1006 Kadoma Kadoma Matsushita Electric Industrial               Inside the corporation (72) Inventor Daisuke Mori               1006 Kadoma Kadoma Matsushita Electric Industrial               Inside the corporation                (56) References JP-A-52-102710 (JP, A)                 JP-A-55-138798 (JP, A)                 Japanese Patent Publication No. 58-9958 (JP, B2)

Claims (1)

(57) [Claims] A memory for storing, for each address, a level D representing a change in the envelope signal, a time constant τ, and a value T representing a predetermined time, an address counter for designating an address of the memory, and a value (D, τ), an envelope signal generating means for generating an envelope signal asymptotic to a value determined by τ toward a value determined by D, and an output value of the address counter when a time determined by T elapses. An electronic musical instrument having updating means for updating.