JP2723609B2 - Microprocessor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to maintaining synchronization between microprocessors in an environment in which a plurality of microprocessors operate in parallel.

2. Description of the Related Art As one method of constructing a highly reliable system using a microprocessor, a redundant or triple system having redundancy by a plurality of microprocessors can be considered. In order to support these highly reliable systems, microprocessors having a function of assisting fault detection have been disclosed.

As a microprocessor having such a failure detection function, in addition to a mode for executing a normal instruction (hereinafter, referred to as a normal execution mode), the microprocessor itself does not drive an external bus and each input / output signal line Compares the output signal of the microprocessor operating in the normal execution mode connected one-to-one with its own output signal (not output to the outside of the microprocessor) every bus cycle,
If they do not match, some modes have a mode of performing an operation of notifying a mismatch detection to an external circuit (hereinafter, referred to as a monitoring mode).

FIG. 5 is a diagram showing a configuration example of a bus control unit of a microprocessor having the above-described functions.

The bus control unit 22 of the microprocessor 21, which operates under the CLK input signal 6 serving as the basic clock, is connected to the READY input signal terminal 3 which requests the extension of the bus cycle.
An EADY sample circuit 13 and a bus timing generation circuit 16 to which IREADY9 output from the READY sample circuit 13 is input.
And a data bus control unit 17 and an address bus control unit 18 to which the bus control signal group 12 output from the bus timing generation circuit 16 is input. The data bus control unit 17 and the address bus control unit 18 control the data bus 7 and the address bus 8 under the control of the bus control signal group 12, respectively.

A signal for requesting extension of the bus cycle is input to the READY input signal terminal 3, and upon receiving the signal, the READY sample circuit 13 outputs the IREADY signal 9 as an internal READY signal of the microprocessor indicating that the READY has been accepted. Is output. I READY signal 9 is the bus timing generator 1
6 and the bus timing generation circuit 16
Based on the state of the signal 9, it is determined whether or not to insert a WAIT cycle into the bus cycle, and control timing is generated for the data bus control unit 17 and the address bus control unit 18 through the bus control signal group 12.

FIG. 6 shows a configuration example of a system in which a pair of microprocessors A and B provided with a bus control unit as shown in FIG. 5 are connected to a common bus and signal line. FIG.

In this system, the microprocessor A is set to the normal execution mode, and the microprocessor B is set to the monitoring mode. That is, microprocessors A and B
Executes the same program, and the microprocessor B set to the monitoring mode compares the output signal of the microprocessor A with its own processing result every bus cycle.

FIG. 7 is a timing chart showing the bus cycle timing of the above-described processing.

The basic bus cycle of the microprocessors A and B consists of two clock cycles of T1 and T2, and samples the READY signal as a bus cycle extension request signal at the rising edge of CLK at the end of each bus cycle.

Here, in a system requiring high-speed processing, the READY signal is used as the basic clock CLK of the microprocessor.
Often returned to non-moving period. Further, even when a microprocessor having the same configuration is used, it is rare that the input characteristics of the READY input terminals of the microprocessor completely match. Therefore, when the READY signal changes near the rising edge of CLK, the two microprocessors A and B do not necessarily sample in the same manner and start processing at the same timing.

In the example shown in FIG. 7, in the bus cycle A-1, the microprocessor A is sampling the READY signal, but the microprocessor B is unable to sample the READY signal. In this case, in the latter half of bus cycle B-1 of microprocessor B, WA
IT cycle TW is inserted.

In such a system, the READY signal is controlled by the microprocessor A in the normal execution mode, and after the bus cycle A-1 the bus cycle A-2.
READY signal is returned.

On the other hand, the microprocessor B operates in the bus cycle B-1.
Attempts to sample the READY signal with TW, but the first T
The sampling cannot be performed in W, and the READY signal of the bus cycle A-2 of the microprocessor A can be sampled for the first time in the second TW. Thus, the microprocessor B can also escape from the WAIT state, but the synchronization of the bus cycles of the microprocessors A and B is shifted after the bus cycles A-3 and B-2, and the normal parallel operation as a duplex system is no longer possible. Not guaranteed.

In view of the above, the present invention has been made to solve the problems of the above conventional example, and to provide a microprocessor having a novel configuration capable of securing effective parallel operation even when a system is configured using a plurality of microprocessors. The purpose is.

In other words, according to the present invention, in a microprocessor having a configuration capable of operating a plurality of units in parallel and having a failure detection function, a READY signal which is a bus cycle extension request signal is provided. READY AC indicating that the
Display means for outputting a K signal; monitoring means for monitoring the READY ACK signal output by another microprocessor; and control means for controlling an extension cycle of the bus based on the output of the display means and the monitoring means. A microprocessor is provided. Thus, according to the present invention, a data bus, an address bus, an execution microprocessor connected to the data bus and the address bus, and performing input and output of data and address via the data bus and the address bus, A monitoring microprocessor connected to the data bus and the address bus, for monitoring data on the data bus and addresses on the address bus without outputting data and addresses to the data bus and the address bus; A monitoring microprocessor having the same configuration as the execution microprocessor, wherein the execution microprocessor and the monitoring microprocessor commonly receive a bus cycle extension request signal, and the monitoring microprocessor Is the bus cycle extension request Means for notifying the execution microprocessor of a control signal in response to the supply of the control signal, wherein the execution microprocessor performs the bus cycle without receiving the control signal from the monitoring microprocessor. In response to the extension request signal being supplied,
An information processing apparatus having means for inserting a WAIT cycle is provided.

The microprocessor according to the present invention provides a READY signal which is a signal indicating that a READY signal which is a bus cycle extension request signal has been accepted in the microprocessor.
Means for generating an ACK; and an input signal for monitoring the READY ACK signal output from another microprocessor, and means for controlling an extended cycle of the bus according to the state of the signal and the state of the READY signal. .

That is, in a parallel system configured using the microprocessor according to the present invention, the RE of another microprocessor
Since the operation is controlled while monitoring the ADY ACK signal, there is no occurrence of a synchronization shift due to a difference in the configuration or characteristics of each microprocessor.

Hereinafter, the present invention will be described more specifically with reference to the drawings. However, the following disclosure is merely an example of the present invention, and does not limit the technical scope of the present invention.

Embodiment FIG. 1 is a block diagram showing a configuration of a bus control unit of a microprocessor configured according to the present invention in contrast to FIG. The same components as those of the conventional microprocessor shown in FIG. 5 are denoted by the same reference numerals.

That is, as shown in FIG. 1, the bus control unit 2 of the microprocessor 1 operating under the CLK input signal 6 includes a READY sample circuit 13 connected to the READY input signal terminal 3 for requesting extension of the bus cycle. , A bus timing generator 16 to which IREADY 9 output from the READY sample circuit 13 is input, and a READY ACK generator 14. The bus control signal group 12 output from the bus timing generation circuit 16 is input to the data bus control unit 17 and the address bus control unit 18. On the other hand, the output of the READY ACK generation circuit 14 is connected to a READY signal line as described later. Further, the bus control unit 2 reads the READY A output from another microprocessor.
WATCH RDY input signal terminal 5 for monitoring the state of the CK output signal, and WATCH RDY input signal terminal 5 connected thereto.
And a READY ACK monitoring circuit 15 for inputting an output corresponding to the state of the above to the bus timing generation circuit.

FIG. 2 is a block diagram showing a configuration example of a duplex system configured by using a pair of microprocessors as shown in FIG.

As shown in FIG. 2, in this system, a microprocessor A and a microprocessor B are connected in parallel to each other with respect to a data bus 7, an address bus 8, a clock signal line, and a READY signal line. On the other hand, the aforementioned WATCH RDY input signal terminal 5 and the READY ACK signal output terminal 4 are connected to each other.

FIG. 3 is a timing chart for explaining the operation of the duplex system shown in FIG. FIG. 4 is a state transition diagram of the duplex system shown in FIG.

Hereinafter, the operation of the duplex system according to the present embodiment will be described with reference to these drawings.

The basic bus cycle of the microprocessors A and B consists of two clock cycles T1 and T2, and the READY signal is sampled at the rising edge of CLK at the end of each bus cycle. The READY signal is "L" and requests to extend the bus cycle.

In the bus cycle A-1 in FIG. 3, the microprocessor A can sample the READY signal, and the microprocessor B cannot sample the READY signal.

The READY ACK monitoring circuit 15 of the microprocessor A monitors the state of the READY ACK output signal of the microprocessor B through the signal line 20, and at the bus timing T1,
READY ACK signal is “H” (WATCH READY input terminal is “H”)
If so, the bus timing generation circuit 16 of the microprocessor A transitions to the state of T2 and outputs the signal 11. READY A
The CK generation circuit 14 is controlled by the state of the signal 11 and IREADY9.
The READY ACK output signal 4 is activated ("H"), and the operation of the next bus cycle A-2 is started.

On the other hand, the READY ACK monitoring circuit 15 of the microprocessor B
Similarly, the RE of the microprocessor A through the signal line 19
The state of the ADY ACK output signal is monitored, and the timing generation circuit 16 of the microprocessor B transits to the T2 state.
However, since the READY signal has not been sampled by the microprocessor B, the IREADY signal 9 does not become active, and the bus timing generating circuit 16 which has received the IREADY signal 9 transitions to the TW state, and the microprocessor A
Wait for the Y ACK output signal to become active.

At this time, when the READY ACK output signal of the microprocessor A is confirmed by the READY ACK monitoring circuit 15, the microprocessor B completes the B-1 cycle, and
Activate the output signal 4 to make the next bus cycle B-2
Start working.

The READY ACK monitoring circuit 15 of the microprocessor A transmits the signal of the microprocessor B at T1 of the bus cycle A-2.
When confirming that the READY ACK output signal is not active, the bus timing generation circuit 16 unconditionally transitions to the state of TWa after transitioning to the state of T2a. In other words, unconditionally WAI
Insert a T cycle. Next, the READY AC
The READY ACK output signal 4 output from the K generation circuit 14 is made inactive, and waits until the I READY signal 9 becomes active.

The ready acknowledgment circuit 15 of the microprocessor B outputs the signal of the microprocessor A at T1 of the bus cycle B-2.
When it is confirmed that the READY ACK output signal is active, the bus timing generation circuit 16 transitions to the state of T2, and the signal 11 outputs the READY A
CK output signal 4 is deactivated and I READY signal 9
Go check the status.

Bus cycle A-2 of microprocessors A and B
When the READY signal is sampled by the READY sample circuit 13 and the I READY signal 9 becomes active in both the microprocessors A and B, the microprocessors A and B both
The ADY ACK output signal 4 is activated to start the operation of the next bus cycle A-3 and B-3.

Bus cycles A-3 and B-3 in FIG.
The microprocessor A cannot sample the READY signal, and the microprocessor B can sample the READY signal. In this state, the operation is completely the same except that the states of the bus cycles A-1 and B-1 and the microprocessors A and B are interchanged, so that the description is omitted.

As described above, the microprocessor according to the present invention realizes reliable parallel operation even when a multiplex system in which a plurality of microprocessors operate in parallel is configured.

Although the present embodiment has been described with reference to the case where the basic bus cycle consists of two clock cycles, it goes without saying that the present invention is similarly effective for a microprocessor consisting of different clock cycles. Further, the present invention can be extended to a triple system using more microprocessors.

Effect of the Invention As described above, the microprocessor according to the present invention mutually monitors the state of the READY ACK signal output from each microprocessor when a plurality of the microprocessors are configured to operate in parallel with each other. By doing so, it is configured to determine its own state according to the state of another microprocessor. Therefore, the synchronization of each microprocessor can be maintained without deteriorating the performance, and a highly reliable parallel operation environment can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a microprocessor according to the present invention, particularly focusing on a bus control unit. FIG. 2 is a configuration example of a duplex system using the microprocessor shown in FIG. FIG. 3 is a timing chart for explaining the operation of the duplex system shown in FIG. 2, and FIG. 4 is a state transition explaining the operation of the duplex system shown in FIG. FIG. 5 is a block diagram showing a configuration example of a conventional microprocessor, particularly focusing on a bus control unit. FIG. 6 is a block diagram showing a duplex system using the microprocessor shown in FIG. FIG. 7 is a timing chart for explaining the operation of the duplex system shown in FIG. [Main reference numbers] 1, 21: microprocessor, 22: bus control unit, 3: READY input terminal 4, READY ACK output terminal 5, WATCH READY input terminal 6, CLK input terminal 7 ... Data bus, 8 ... Address bus 9 ... Internal READY (I READY) signal 10 ... Output signal of READY ACK monitor circuit 11 ... Output signal to READY ACK generation circuit 12 ... Bus control signal group 13 ... READY sample circuit 14 READY ACK generation circuit 15 READY ACK monitoring circuit 16 Bus timing generation circuit 17 Data bus controller 18 Address bus controller

Claims (2)

(57) [Claims] A data bus; an address bus; an execution microprocessor connected to the data bus and the address bus for inputting and outputting data and addresses via the data bus and the address bus; A monitoring microprocessor connected to the address bus for monitoring data on the data bus and addresses on the address bus without outputting data and addresses to the data bus and the address bus; An information processing apparatus having a microprocessor and a monitoring microprocessor having the same configuration,
The execution microprocessor and the monitoring microprocessor commonly receive a bus cycle extension request signal, and the monitoring microprocessor sends a control signal to the execution microprocessor in response to the supply of the bus cycle extension request signal. The execution microprocessor has a WAIT cycle in the bus cycle in response to the bus cycle extension request signal being supplied without the control signal being supplied from the monitoring microprocessor. An information processing apparatus having means for inserting. 2. An execution microprocessor connected to the data bus, the address bus, the data bus and the address bus, for inputting and outputting data and addresses via the data bus and the address bus, and the data bus. A monitoring microprocessor connected to the address bus for monitoring data on the data bus and addresses on the address bus without outputting data and addresses to the data bus and the address bus; An information processing apparatus having a microprocessor for performing the same processing simultaneously with the microprocessor, wherein the execution microprocessor and the monitoring microprocessor commonly receive a bus cycle extension request signal, and the execution microprocessor The bus cycle extension request signal And a means for notifying the monitoring microprocessor of a first control signal in response to the supply of the bus cycle extension request signal. Means for notifying the execution microprocessor of a second control signal, wherein the execution microprocessor receives the bus cycle extension request signal without receiving the second control signal from the monitoring microprocessor. Means for inserting a WAIT cycle into the bus cycle in response to the execution of the bus cycle extension request signal without the first control signal being supplied from the execution microprocessor. Information processing means for inserting a WAIT cycle into a bus cycle in response to the supply of Equipment.