JP2723830B2 - Data line terminator with pseudo carrier control function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data line terminating apparatus, and more particularly to a data line terminating apparatus in a half-duplex communication or a full-duplex communication in which a modulated carrier (hereinafter, referred to as a carrier) is controlled by a transmission request (RS) signal. The present invention relates to a data line termination device with a pseudo carrier control function used.

[0002]

2. Description of the Related Art For example, referring to FIG. 3, transmission and reception of data between a data terminal equipment (DTE) 3-1 and a DTE 3-2 are performed by a data line terminating equipment (DCE) 4-1 and a DTE 3-2.
A data line terminating device according to a first prior art used in half-duplex communication or full-duplex communication of a data communication system performed via CE4-2 uses an RS signal as a control signal of a transmission carrier, and performs internal transmission. A modem (MODEM) 40 which receives a data (MSD) signal and a reception carrier as input signals, and outputs a transmission carrier, an internal reception data (MRD) signal, an internal transmission permission (MCS) signal, and an internal carrier detection (MCD) signal as output signals. have.

[0003] Referring also to the timing chart of FIG. 4, this type of data line terminating apparatus controls a transmission carrier by an RS signal in order to perform half-duplex communication or full-duplex communication. , RS signal is ON (O
In N), the main transmission data of the transmission data (SD) signal is modulated and the carrier is transmitted. Also, when the RS signal is off (OFF), the receiving carrier is monitored, the presence or absence of the receiving carrier is detected, and the detection result is output as a carrier detection (CD) signal. When a carrier is detected as being present, the received carrier is demodulated and a received data (RD) signal including main received data is output. In addition, when detecting a carrier disconnection, an RD signal holding the main reception data in a Z pattern is output.

[0004] However, in monitoring the received carrier, the detection of carrier disconnection monitors the complete disappearance of the received carrier. Therefore, due to the residual carrier due to the transient characteristics of the carrier, extra bits other than the original main received data called extra bits are caused by extra bits. There is a problem that a bit is generated and that the residual carrier delays the OFF of the CD signal, so that the ON of the RS signal is also delayed. As a result, it takes extra time to switch from the data reception state to the data transmission state.

[0005] As a second prior art which solves the problem of the data line terminating device which is the first prior art, a "reception signal processing system in a communication system" (Japanese Patent Laid-Open No. Sho 60-2).
There is a known technique described with reference to FIG. 1 to FIG.

The data line terminating device according to the second prior art will be described again by translating FIGS. 1 to 3 of Japanese Patent Application Laid-Open No. 60-254953 into FIGS. For example, CPU and data terminal equipment (DTE)
Is generally configured as shown in FIG. 5, and the SD signal is transmitted from the CPU 10 to the MODE.
The modulator in M6-1 determines the modulation information corresponding to the transmission data, and the MODEM 6-1 transmits a carrier based on the modulation information. And
On the receiving side DTE7 side, the above carrier is MODE
The modulation information is extracted by demodulation by the demodulator in M6-2, and the reception data (RD) corresponding to the transmission data described above is created based on the extracted modulation information.

At this time, the receiving side MODEM 6-2 detects that a carrier is being input, and raises a detection signal, that is, a CD signal.
While the signal is rising, the input carrier is demodulated. However, since this CD signal is created by performing threshold processing or the like on the integral signal of the carrier, as shown in FIG. 6, the falling of the CD signal is inevitable from the time when the carrier corresponding to the original transmission data is lost. It will be delayed by a short time Te (10 ms to 20 ms). For this reason, the MODEM 6-2 recognizes that the carrier exists even during the time Te when there is no actual carrier, and as a result, a signal such as line noise input during that time is demodulated. The received data to be created is data in which meaningless data, that is, an extra bit described in the first related art is added after a portion corresponding to the original transmission data.

Therefore, on the receiving side of an ordinary communication system, various reception signal processing methods for removing the extra bits as described above have been considered. Among them, a data line terminating device according to a second prior art adds a different data to original transmission data, that is, dummy data for removing extra bits to transmission data transmitted from a transmission side. Has been adopted.

[0009] This will be described in detail with reference to FIG. 7. Dummy data Dd (here, binary all “ 1 ” data) immediately after the carrier corresponding to the original transmission data on the transmission side is described. On the other hand, on the receiving side, the carrier detection signal is caused to fall after a predetermined time To since the detection of the dummy data Dd, and the reception data created at the timing of the fall of the carrier detection signal is added. A predetermined value, for example, binary " 1 "
(So-called Z clamp). The time To is set to substantially half the time during which the dummy data Dd is transmitted.

[0010] According to such a method, the received data to be created is obtained by adding predetermined dummy data Dd (that is, all binary " 1 ") after the portion corresponding to the original transmission data. , The extra bits of unknown meaning as described above are removed.

In other words, in this method, the transmitting side and the receiving side preliminarily decide on the dummy data Dd, for example, on the transmission time and contents.

[0012]

In the data line terminating apparatus according to the second prior art, a carrier detection signal rises.
Under rising timing, fix the received data to "1" in binary is a predetermined value (i.e., Z clamps) because it so that, by line noise, etc., when the carrier detection signal rises again, extra bits There is a problem that the removal of ash is not performed reliably.

[0013]

A data line terminating apparatus with a pseudo carrier control function according to the present invention is connected to each other via a data communication line and connected between external data terminals or through a data modem incorporated in the apparatus. A data line terminating device for performing data communication between an external data terminal and an external center device;
In the data communication in which the carrier control is performed by the RS signal , the reception data (RD) of the opposite-side data modem is used.
Residual carriers generated at the output and ITU-T Recommendation
13 by applying the pseudo carrier control function of FIG.
When switching the carrier on / off of the modem
Generated on the receive data (RD) output of the opposing data modem
Extra bits resulting from the generated first pattern are
Scrambled binary in said pseudo carrier control
Said first pattern of "1" and scrambled
Extract to be removed using the binary "0" second pattern
It is provided with a trabit removing unit.

Further, the data line terminating apparatus with a pseudo carrier control function according to the present invention can be connected to each other via a data communication line.
Data modulation and demodulation device built-in
Through external data terminals or with external data terminals
Data line for data communication between external center devices
In the terminating device, the data line terminating device detects the presence of a continuous Z pattern of N bits in a first SD signal from an external first data terminal or an external first center device. When it is detected, the N signal of the first SD signal is detected.
From SD inverting means and said first data terminal or said <br/> first center device for outputting a second SD signal by adding at least one bit of the A pattern immediately successive Z pattern of bits the changed from said modulation and demodulation means from the time the first data terminal or said first CS signal sent back to the center apparatus from oFF state state when the first RS signal is changed from the oFF state to the oN state The second SD of the output of the SD inversion means, on which the main transmission data has not yet been superimposed after the elapse of X time before the change to
A-clamping is performed to add a K-bit A pattern to the signal, and when the first RS signal changes from the on-state to the off-state, the second SD signal starts from the time when the change occurs.
SD clamp means for performing a Z clamp for adding a Z pattern of M bits or more immediately after the main transmission data of the signal and outputting it as a third SD signal, and the third SD signal from the SD clamp means is predetermined. Scrambler means for scrambling according to the generated generator polynomial and outputting it as a fourth SD signal, and changing the first RS signal from the first data terminal or the first center device from an on state to an off state Off delay means for delaying the second RS signal by a predetermined time, and outputting the second RS signal from the off delay means, and the K bit of the K bit A pattern of the third SD signal From the on-state to the off-state at the time when the first RS signal changes from the on-state to the off-state within the time, Wherein from said scrambler means and outputting the transmission carrier to an on state time of the second RS signals with outputs the falling CS signal is sent to the first data terminal or said first center device first with 4 of the SD signal communication through said channel first data terminal or said first center device opposed to sending to the outside of the second data terminal or outside of the second center device and facing the second wherein the data terminal or the second center device and the transmission carrier to be delivered through the data communication lines fourth SD
And a modulating / demodulating means for receiving a signal and outputting a first CD signal and the scrambled first RD signal, and descrambles the first RD signal from the modulating / demodulating means to form a second RD signal. Output descrambler means, and when detecting the presence of the scrambled Z-bit continuous Z pattern in the second RD signal from the descrambler means, immediately after the N-bit continuous Z pattern Said at least one added
RD inverting means for deleting the A pattern of bits and outputting as a third RD signal;
First scramble binary detection means for detecting the K-bit A pattern scrambled on the opposite side from the RD signal of the opposite side and outputting a first scramble pattern detection signal; and the first RD signal from the modulation / demodulation means. A second scramble binary detecting means for detecting an R to S bit Z pattern of the M bits or more and a Z pattern scrambled on the opposite side from the signal and outputting a second scramble pattern detection signal; When the first scramble pattern detection signal is input from the scramble binary detection means, the first CD signal from the modulation / demodulation means is turned on, and the second scramble binary signal is received from the second scramble binary detection means. When a pattern detection signal is input, And CD control means for sending said to first said CD signal as a second CD signal in the off state the first data terminal or the first center device, wherein said C
When the second CD signal input from the D control means is on, the third RD signal from the RD inversion means is output as a fourth RD signal, and the second CD signal from the CD control means is output. When the CD signal is input in the off state, the first RD signal from the RD inverting means is Z-clamped, held in the descrambled R to S bit Z pattern and output, and the first data terminal is output. Or, RD clamp means for sending to the first center device.

Further, in the data modulation / demodulation device with a pseudo carrier control function according to the present invention, the K-bit A pattern, the M-bit or more Z pattern, and the R to S-bit Z pattern may be in accordance with ITU-T Recommendation V.3. There are 13 8-bit A patterns, 128-bit or more Z patterns, and 48-64 bit Z patterns.

Still further, in the data modulation / demodulation apparatus with a pseudo carrier control function according to the present invention, the generator polynomial may have an ITU
-T Recommendation V. 13 1 + X ^-3 + X ^-7 .

[0017]

Next, the present invention will be described with reference to the drawings. Referring to FIG. 1 showing an embodiment of the present invention, FIG. 1 shows a data line terminal (DCE) having each modem (MODEM) 21 between a data terminal equipment (DTE) 1-1 and a DTE 1-2. 2) shows a system configuration for transmitting and receiving data via 2-1 and DCE2-2. Here, each of DCE2-1 and DCE2-2 is a DTE
When the presence of an N-bit continuous Z pattern in the SD signal from 1-1, that is, the first SD signal, is detected, a 1-bit continuous Z pattern of the first SD signal is immediately followed by one bit. An SD inverting circuit 201 for adding a pattern A and outputting the second RS signal as a second SD signal; and a modulating / demodulating unit to be described later when the first RS signal from the DTE 1-1 changes from an off state to an on state. (MODEM)
After a lapse of X time before the CS signal returned from 21 to the DTE 1-1 changes from the OFF state to the ON state, an 8-bit signal is added to the second SD signal output from the SD inversion circuit 201 on which the main transmission data has not yet been superimposed. When the A-clamp for adding the A-pattern is performed and the first RS signal changes from the on-state to the off-state, the second RS immediately after the change is turned on.
Of 128 bits or more after the main transmission data of the SD signal
An SD clamp circuit 202 for performing Z-clamping for adding a pattern and outputting as a third SD signal; and a fourth SD signal obtained by scrambling the third SD signal from the SD clamp circuit 202 using a predetermined generator polynomial. That is, a scrambler circuit 203 that outputs an MSD signal,
An off-delay circuit 200 for delaying a change of the first RS signal from the on state to the off state from the DTE 1-1 from the on state to the off state and outputting it as a second RS signal, and a second RS signal from the off delay circuit 200 Is entered and the third SD
Outputs a CS signal that rises from the off state to the on state within the 8 bit time of the 8 bit A pattern of the signal and falls from the on state to the off state when the first RS signal changes from the on state to the off state. Data terminal device 1
-1 and outputs a transmission carrier during the ON state time of the second RS signal, and together with the fourth SD signal from the scrambler circuit 203, that is, the MSD signal, the DTE1-2 facing the DTE1-1 through the data communication line. And a fourth SD signal, that is, an MSD signal, which is transmitted from the DTE 1-2 through the data communication line, and outputs a first CD signal and a scrambled first RD signal, that is, an MRD signal. And a descrambler circuit 2 that descrambles the first RD signal, that is, the MRD signal from the MODEM 21 and outputs it as a second RD signal.
04 and the second RD from the descrambler circuit 204.
When the presence of a scrambled N-bit continuous Z pattern in the signal is detected, the 1-bit A pattern added on the transmission side immediately after the N-bit continuous Z pattern is deleted and used as a third RD signal. An output RD inversion circuit 205, and a scrambled binary that detects an 8-bit A pattern scrambled on the opposite side from the first RD signal from the MODEM 21 and outputs a first scramble pattern detection signal (SB0 detection signal) 0 ”(S
B0) The detection circuit 206 detects a 48- to 64-bit Z pattern of 128 bits or more and a Z pattern scrambled on the opposite side from the first RD signal from the MODEM 21, that is, the MRD signal, and generates a second scramble pattern detection signal ( A scramble binary “1” (SB1) detection circuit 207 that outputs an SB1 detection signal) and an MO when an SB0 detection signal is input from the SB0 detection circuit 206.
The first CD signal from the DEM 21 is turned on, and when the SB1 detection signal is input from the SB1 detection circuit 207, the first CD signal from the MODEM 21 is turned off and the DTE1-1 is set as the second CD signal. To the CD control circuit 208 which is sent to the CD control circuit 208 and RD when the second CD signal input from the CD control circuit 208 is in the ON state.
The third RD signal from the inverting circuit 205 is output as the fourth RD signal, and the second RD signal from the CD control circuit 208 is output from the second RD signal.
When the CD signal is input in the OFF state, the third RD signal from the RD inversion circuit 205 is Z-clamped, held in a descrambled 48-64 bit Z pattern, output, and sent to the DTE 1-1. Clamp circuit 20
9.

Next, FIG. 2 will be described in detail with reference to FIG. Here, when data is transmitted from DTE1-1 to DTE1-2, that is, DTE2-1 is a DCE on the transmitting side.
The case where 2-2 is the receiving side will be described.

The DCE 2-1 on the transmitting side is the same as the DT on the same transmitting side.
When the RS signal from E1-1 changes from OFF to ON, that is, when the MRS signal output from the off-delay circuit 200 changes from OFF to ON, the inside of the MODEM 21 from the MODEM 21 to the opposite receiving side DCE 2-2 is changed. After transmitting a synchronization signal for adjusting the equalizer and the like for X time, the SD clamp circuit 3 outputs a third SD signal to which an 8-bit A pattern is added. This 8-bit A
The pattern is scrambled by the scrambler circuit 203, that is, A-scrambled together with the main transmission data immediately following the pattern, and output as an MSD signal.
1 through the data communication line to the receiving DCE 2-2. In the receiving DCE2-2, the MODEM
21 detects a transmission carrier from the transmission side DCE 2-1 as a reception carrier and outputs it as an MCD signal, and detects an 8-bit A pattern scrambled on the transmission side from the MRD signal output from the MODEM 21 by the SB0 detection circuit 206 And outputs the SB0 detection signal, and the CD control circuit 208 outputs the CD based on the SB0 detection signal.
The signal is turned on from OFF and supplied to the RD clamp circuit 209 and DTE1-2. Also, the transmitting DCE2-
1 is returned to the transmitting side DTE 1-1 by the RS signal RS
Processing is performed inside the modem 21 so that the signal is turned on within the elapse of the transmission time of the 8-bit A pattern after the elapse of X time after the signal is turned on.

Next, the SD signal from the DTE 1-1 is S
When a D-inverting circuit 209 detects a continuous Z pattern of N bits in the SD signal, a 1-bit A pattern is added immediately after the Z pattern, and an RS signal is further generated in the SD clamp circuit 202. When the signal changes from OFF to ON, an A-clamp for adding an 8-bit A pattern is performed after a lapse of X time before the CS signal changes from OFF to ON and immediately before the main transmission data. And the RS signal is ON
When the state changes from "OFF" to "OFF", Z-clamping for adding a Z-pattern of 128 bits or more is performed after the main transmission data immediately after the change, and is output as a third SD signal. Then, the third SD signal is scrambled by the scrambler circuit 203 and converted into a fourth SD signal by M
The data is input to the ODEM 21 and transmitted from the MODEM 21 to the receiving DCE 2-2 through the data communication line.
Then, the receiving side DCE2- 2, and outputs the first RD signal, that MRD signal by demodulating the transmission side sending signal sent from the transmitting side DCE2-1 in MODEM21,
In the descrambler circuit 204, the MRD signal is descrambled and output as a second RD signal.
When the RD inversion circuit 205 detects a continuous Z pattern of N bits in the descrambled second RD signal from the descrambler circuit 204, the next one bit of the Z pattern, that is, on the transmission side, The added 1-bit A pattern is deleted and output to the RD clamp circuit 205 as a third RD signal.

Further, when the RS signal from the transmission side DTE1-1 changes from ON to OFF, the transmission side DCE2
-1 is at least 128 by the off-delay circuit 200
Ignore the turning off of the RS signal during the bit time. That is, the RS signal is turned from ON to OFF after a predetermined off-delay time of the off-delay circuit 200 has elapsed. In the SD clamp circuit 202, the transmitting side DTE1-1
When the RS signal from ON changes from ON to OFF, S
Immediately after the main transmission data of the second SD signal output from the D inversion circuit 201, Z clamping of adding a Z pattern of 128 bits or more is performed, and the resultant signal is output to the scrambler circuit 203 as a third SD signal. The scrambler circuit 203 scrambles the third SD signal, that is, A-scrambles the 8-bit A pattern and Z-scrambles the Z pattern of 128 bits or more, and outputs the fourth SD signal, that is, the MSD signal. To the data communication line through

The first RD signal output from the MODEM 21 of the receiving side DCE 2-2, that is, the MRD signal including the Z-scrambled 128-bit Z pattern and the extra bits due to the residual carrier is descrambled by the descrambler circuit 204. The signal is supplied to the RD clamp circuit 209 as a third RD signal through the RD inversion circuit 205. When the Z-scrambled 48- to 64-bit Z pattern is output from the MRD signal input from the MODEM 21, the SB1 detection circuit 23 outputs the SB1 detection signal as a CD.
It outputs to the control circuit 208 and controls the CD signal output from the CD control circuit 208 to OFF. On the other hand, in the RD clamp circuit 209, when the output of the CD control circuit 208 is controlled to OFF, the Z pattern descrambled to the third RD signal input from the RD inversion circuit 205 due to the control of the CD signal OFF. , That is, Z
The signal is clamped, held in a 48 to 64 bit Z pattern, output, and transmitted to the receiving side DTE1-2 as a fourth RD signal. Therefore, no extra bit due to the residual carrier occurs in the RD signal input to DTE1-2.

Here, if the RS signal changes to ON and the RS signal is turned on within 8 bit time of the MSD signal after X time has elapsed.
When the signal is turned off, the transmission of the 8-bit A pattern from the SD clamp circuit 202 is stopped when the RS signal is turned off, so that the CD from the receiving DCE 2-2 to the receiving DTE 1-2 is stopped. The signal does not turn on. As a result, there is no possibility that the problem occurs in the second related art, that is, the CD signal rises again due to line noise or the like and extra bits are generated. Thus, in the present invention, the O of the CD signal is
Not only FF control but also ON control of CD signal can be performed.
It is possible.

[0024]

As described above, according to the present invention, I
TU-T Recommendation V. By using the pseudo carrier control of No. 13, the generation of extra bits due to the remaining carrier of the received carrier can be prevented, and high-quality data communication can be performed. Further, by controlling the CD signal not by the reception carrier but by the reception data, the speed of switching from the data reception state to the data transmission state is increased, the throughput can be improved, and the CD signal rises again due to line noise or the like. There will be no extra bits.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a data line termination device according to one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the data line terminating device of the embodiment.

FIG. 3 is a block diagram showing a first conventional example.

FIG. 4 is a timing chart for explaining the operation of the first conventional example.

FIG. 5 is a block diagram showing a second conventional example.

FIG. 6 is a first timing chart for explaining the operation of the second conventional example.

FIG. 7 is a second timing chart for explaining the operation of the second conventional example.

[Explanation of symbols]

 1-1, 1-2 Data terminal device 2-1, 2-2 Data line termination device 20 Transmitter 21 Modulator / demodulator 22 Receiver 200 Off-delay circuit 201 SD inversion circuit 202 SD clamp circuit 203 Scrambler circuit 204 Descrambler circuit 205 RD inversion circuit 206 SBO detection circuit 207 SB1 detection circuit 208 CD control circuit 209 RD clamp circuit

Claims (4)

(57) [Claims] 1. An external device which is connected to each other via a data communication line and connected via a data modulation / demodulation device built in the own device.
A data line terminating device that performs data communication between data terminals or between an external data terminal and an external center device.
Oite, the data line terminal is the opposite side data variable in data communication performing carrier controlled by RS signal
Residual carriers generated in the received data (RD) output of the demodulator and ITU-T Recommendation 13 pseudo carrier controls
Apply the function to the carrier of the data modem on the opposite side
When performing on / off switching, the opposite-side data modem
The first pattern generated in the output of the received data (RD)
Extra bits caused by the pseudo carrier control
The first eye of the scrambled binary "1" in the first eye
Dollar pattern and scrambled binary "0"
Extra bit removal using pattern 2
Artificial carrier control function data line terminal, characterized in that it comprises means. 2. A mutually opposing connection via a data communication line.
Externally through the built-in data modem
Between data terminals or between external data terminals and external
Data line terminating equipment that performs data communication between
When the data line terminating device detects the presence of an N-bit continuous Z pattern in a first SD signal from an external first data terminal or an external first center device, SD inverting means and said first data terminal or said first output as the second SD signal by adding at least one bit of the a pattern immediately successive Z pattern of said N bits of the first SD signal off CS signal first RS signal from the center apparatus is returned from the modulation and demodulation means from the time of the changed when changed from the oFF state to the oN state to the first data terminal or said first center device A K-bit A pattern is applied to the second SD signal output from the SD inversion means, on which the main transmission data has not yet been superimposed after X time before the state changes to the ON state. When the A-clamp is added, when the first RS signal changes from the on-state to the off-state, a Z pattern of M bits or more is added immediately after the main transmission data of the second SD signal from the point of the change. Output as a third SD signal after performing Z clamp
Clamping means; and the third from the SD clamping means.
And a scrambler for scrambling the SD signal according to a predetermined generator polynomial and outputting it as a fourth SD signal, and an on state of the first RS signal from the first data terminal or the first center device. Off-delay means for delaying the change from the off state to the off state for a predetermined time and outputting as a second RS signal, and the second RS signal from the off-delay means being input and the K signal of the third SD signal being inputted. The CS signal which rises from the off state to the on state within the K bit time of the bit A pattern and which falls from the on state to the off state when the first RS signal changes from the on state to the off state is output. the scan outputs a transmission carrier in the on-state time of the second RS signal sends out the first data terminal or said first center device The fourth SD from Rambla means
The first data terminal or the with signal through the data communication line first center device opposed to sending to the outside of <br/> second data terminal or outside of the second center device and the opposite second first, which is the data terminal or the <br/> first CD signal and the scrambling from the second center device is input and the SD signal of the transmission carrier fourth delivered through the data communication lines Modulating / demodulating means for outputting an RD signal of the above, and descrambler means for descrambling the first RD signal from the modulating / demodulating means and outputting as a second RD signal;
When detecting the presence of the scrambled Z pattern of the N bits continuous in the second RD signal from the descrambler means, the Z bits of the N bits continuous
A of the at least one bit added immediately after the pattern
RD that deletes the pattern and outputs it as a third RD signal
Inverting means, and first scramble binary detection means for detecting the K-bit A pattern scrambled on the opposite side from the first RD signal from the modulation and demodulation means and outputting a first scramble pattern detection signal And outputting a second scramble pattern detection signal by detecting from the first RD signal from the modulating / demodulating means an R to S bit Z pattern of the M or more Z pattern scrambled on the opposite side and outputting a second scramble pattern detection signal. (2) when the first scramble pattern detection signal is inputted from the first scramble binary detection means, the first CD signal from the modulation / demodulation means is turned on; 2 from the second scramble binary detection means. Second C with the first CD signal from the modulation and demodulation means in the OFF state when the but entered
A CD control means for transmitting a D signal to the first data terminal or the first center device; and a second signal from the RD inversion means when the second CD signal input from the CD control means is in an ON state. 3 is output as a fourth RD signal, and when the second CD signal from the CD control means is inputted in an off state, the third RD signal from the RD inversion means is Z-clamped. RD clamp means for holding and outputting the descrambled R-S bit Z pattern and sending it out to the first data terminal or the first center device. Data line termination. 3. The K bit A pattern, the M bit or more Z pattern and the RS bit Z pattern are
TU-T Recommendation V. 3. The data line terminating device with a pseudo carrier control function according to claim 2, wherein the data is a 13-bit A pattern, a Z pattern of 128 bits or more and a Z pattern of 48 to 64 bits. 4. The generator polynomial according to ITU-T Recommendation V.4. 1
4. The data line termination device with a pseudo carrier control function according to claim 2, wherein 1 + X ^-3 + X ^-7 .